TWI236095B - Pattern and method for testing interconnects - Google Patents

Abstract

Pattern and method for testing interconnects are provided. The pattern for testing interconnects including several testing via plugs in a dielectric layer of a wafer. These testing via plugs connect with a metal layer of the wafer, and they surround a tested via plug to define a predictive area. After providing a testing condition to the wafer, then electrical properties of the tested via plug are measured to diagnose if the via plug of the wafer is open.

Description

1236095 Case No. 92115454 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor. The invention relates to a process for modifying and inserting a bulk body circuit, and in particular, a test pattern and method for interconnecting Θ types. In particular, [prior art] integrated circuits use various types of microchips as needed. When the components / circuits are reduced together, the manufacturing method provides enough area to increase the accumulation of electricity, so that when the wafer is absent, the interconnections required for the design of the multilayer metal layer are used. . Gradually become a must for many integrated circuits

Between each metal layer, ^^ κ (via nll,, metal interconnect structure, such as interposer plug, v 1 a ρ 1 u g) is used to reach each other's loop. In order to develop the second, a complete inter-layer dielectric (inter-layer dielectric; 1〇) made of a galvanic material is formed by a short circuit caused by a structure in which the two metal layers are in contact with each other except a plug. Isolate. In traditional semiconductor manufacturing, aluminum (A 丨) is the most commonly used conductor material. Because aluminum is extremely conductive, inexpensive, and easy to deposit and etch, semiconductor factories traditionally use aluminum as a component. wire. As the integration degree of integrated circuits continues to increase, the capacitive effect between metal wires is relatively

The phenomenon of "Resistance-Cap acitance time de 1 ay", which is relatively large, will also increase, and the speed of current conduction between metal wires will be slowed down accordingly. At present, the factors that affect the speed are the resistance of the metal wire itself and the size of the parasitic capacitance between the wires.

Page 6 1236095 s _case number 92115454__ year month day _ five, the description of the invention (2) the key to sex. Among them, to improve the parasitic capacitance between the wires, a low-dielectric constant material (generally below 3 · 5) can be used as the insulation layer between the multilayer metal wires. To reduce the effect of the wire resistance, a low resistance value can be used. Metal material. Among all metals, copper has gradually replaced aluminum as a metal wire material due to its high melting point, low resistance coefficient (approximately 1.7 μΩ-cm) and high resistance to electromigration. Early IC processes were reluctant to use copper as the metal connection line because copper metal had a high expansion coefficient, and it would diffuse to the substrate quickly after contacting with silicon or silicon dioxide, causing deep energy level problems. In addition, copper metal itself is prone to oxidation, easily reacts with other materials at low process temperatures, and lacks effective dry-cut technology. These problems limit the development of copper metal in the I c process. However, with the advancement of materials and process technology, various diffusion barriers have been continuously researched, and the success of the damascene process and the copper chemical mechanical polishing (CMP) technology have solved these problems. Traditionally, in the production of copper metal mosaic structures, non-isotropic dry decoration is usually used to engrav the mosaic openings in the dielectric layer, exposing the next copper conductive layer, and then using chemical plating (ECP) or The chemical vapor deposition (CVD) technology forms a copper metal layer on the dielectric layer and fills the damascene opening, and then uses CMP to remove the excess copper metal part on the dielectric layer, leaving the part inside the damascene opening. Form the required interconnect structure. Figure 1A is a three-dimensional audio diagram showing a conventional plug structure between two metal layers. In FIG. 1A, the interposer plug structure 100 is a metal layer / two = layer / metal layer structure, and the metal layer i 〇4 is through the intermediary plug j 08 and the metal ^

Page 7 1236095 ^ 0 —_ Case No. 92115454 A — ^ ± —— ^ _ 巨 ..___. Jlj: _ 5. Description of the invention (3) Layers 1 0 6 are connected. For a clearer explanation, 'FIG. 1B is a side view of a part of FIG. As shown in Fig. 1B, the two metal layers 104 and 106 are separated by a dielectric layer 102 (not shown in Fig. 1A). However, according to FIG. 1B, when the metal layer 104 is formed, very small vacancy will inevitably exist at the edges of the grains, and these vacancies will be affected by changes in stress. It is driven to focus on the via plug bottom 1 1 2 to form a stress-induced void (SIV). The hole caused by this stress is located at the bottom 112 of the interposer plug, which will cause the interposer plug 108 to break, which will cause the entire integrated circuit to produce errors. In general, holes caused by stress will be driven and concentrated by thermal stress gradients to cause holes. The change of the stress gradient caused by the different expansion coefficients and the unmatched material will cause the thermal stress gradient in different areas to drive the holes. The formation mechanism is interpreted as: thermal stress gradient in different regions due to thermal expansion changes in different regions. The integrated circuit is temperature-matched during the manufacturing process or changes in temperature during the operation pass through the thermal stress gradient. At this time, the growth condition of the crystals is generally caused by the above-mentioned concentration of vacancies in the original metal layer. For example, the metal layer: will affect the quality of the interposer plug of the wafer. The number of vacancies in crystal growth / ς / dagger holes. That is, Xiao: # 到 1236095 exists in the metal layer _Case No. 92115454_year month day__ 5. Description of the invention (4) On the other hand, Different process conditions of the interposer plug will also affect the thermal stress gradient distribution at the bottom of an interposer. The interposer structure manufactured under different process conditions has different ability to gather voids to form holes. Therefore, in order to test a After the wafer has changed its process conditions, whether it is easy to generate holes and interrupt the intervening plugs, an interconnect test method is needed to test whether an interconnect structure is prone to generate holes due to thermal stress gradients. The force line of the test ladder for the production of the production plan should be connected to the thermal line as a cause. Whether the confession will be provided for a while, the test is issued in the test volume of the connected line 1 to issue the test copy. t factor According to the above purpose of the present invention, a test pattern and method for interconnects are proposed. The present invention uses a test pattern for interconnects to test a wafer, and the structure of the wafer is a metal layer / dielectric layer / Metal layer, and there is an interposer plug in the dielectric layer to connect the two metal layers. The interconnect test pattern of the present invention includes a plurality of test interposer plugs located in the dielectric layer. One end of these test interposer plugs and The metal layer is connected and arranged around the interposer plug to be tested to surround a predetermined area. After the wafer is placed in a test environment, the electrical characteristics of the interposer plug to be tested are measured to know this. Whether the dielectric plug in the wafer is open. According to a preferred embodiment of the present invention, the material of the above metal layer, the tested interposer plug and the tested interposer are metal copper, and the material of the dielectric layer is low. Dielectric materials. The present invention can use the above-mentioned combination of area sizes to test the same

Page 9 1236095 Case No. 92115454 Month, Amendment V. Description of the Invention (5) A metal in a process condition The surface diffusion area of a predetermined area. In addition to the diffusion region, the present invention is easy to apply due to thermal stress. The present invention is used to test whether the wafer can accommodate holes, and then another layer of testing is created. Intermediate plug test piece is easy to test the same. It can also be used to test a new easy to use. It can be used in the pattern and process bar thermal stress plug plug effect vacancy expansion with the process bar can also adjust the number of plugs in the intermediary. The crystals of the insertion process are different, and the intervening method is not only a piece, but it is broken by a gradient. Bulk area, or use the shape of the effective predetermined area of the same metal layer or test to diagnose the gap at the bottom of the plug. For wafers with effective processing conditions for metal layers in the circle, holes are created at the bottom of the plug. Simple and systematic, it can be used to solve the gaps in the bottom of the plug structure of the new process strip, which is broken and formed into a wide piece. [Embodiment] In order to test whether the interconnect structure will generate holes due to thermal stress gradient The present invention provides a test pattern and method for interconnecting. In the present invention, a wafer is tested by using a test pattern of interconnects. The structure of the wafer is a metal layer / dielectric layer / metal layer, and a dielectric plug is connected to the two metal layers in the dielectric layer. The interconnect test pattern of the present invention includes a plurality of test interposer plugs located in the dielectric layer. One end of these test interposer plugs is connected to the metal layer and is arranged around the interposer plugs to be tested to surround a predetermined area. After placing the wafer in a test environment, measure the electrical characteristics of the tested interposer plugs to know if the interposer plugs in this wafer are open.

Page 10 1236095 Case No. 92115454 _ Shengyue ____ g_ ^ V. Description of the invention (6) The present invention can use the above-mentioned combination of area size to test the effective void diffusion area of the metal layer under the same process conditions, or use the same To determine the effective void diffusion area of the metal layer under different process conditions. On the other hand, the shape of the predetermined area or the number of intervening plugs in the test surrounding the predetermined area can also be adjusted to perform a test.

Whether the processing conditions of the wafer are likely to generate a vacancy at the bottom of the interposer plug. According to a preferred embodiment of the present invention, the material of the aforementioned metal layer, the tested interposer plug and the tested interposer plug are all metallic copper, and the material of the dielectric layer is a low dielectric material. However, the above structure composed of other metal materials and other dielectric layer materials that can be used to isolate the two metal layers of the present invention can also use the test method of the interconnections of the present invention and is not subject to the preferred embodiments of the present invention. Restricted. Please refer to FIG. 2, which illustrates a three-dimensional schematic view according to a preferred embodiment of the present invention. The present invention adds a plurality of test interposer plugs 202a to the interposer structure in FIG. 丨 A. These test interposers 202a are located in the dielectric layer 102 (not shown in FIG. 2), and One end of the test interposer plug 202 & was connected, belonging to 1 1/4 connection. In this embodiment, in order to test the second process of the interposer plug, the other end of the two interposer plugs 002a is a metal layer 204 connected by a metal layer 204 to provide a larger opening. Rate (aperture ratl0) in order to test the production of the intermediary plug 202a. In Figure 2, the test interposer plugs 2 0a that are too much in the test pattern of the interposer plugs 108 A ^ are shown in a row. The center of Figure ^ is a plan view of a row of mediation plugs 108 and ΘΓ2 in a predetermined area. Figure 3A illustrates the relationship between Φ Xi Lima Z test mediation plug 2 023 in Figure 3A. , Not shown day 2

1236095 _ Case number 92Π5454_ 年月 日 __ V. Description of the invention (7) Please refer to Figure 3 A, test the interposer plugs 2 0 2 a are all distanced from the interposer plug 1 0 8—the predetermined distance R, so test the interposer plug The plug 2 2 a will be centered on the interposer plug 108, and surrounds the interposer plug 108 to surround a predetermined area 3 0 2. The shape of the predetermined area 3 2 2 is a circle. Furthermore, the test interposer plugs 2 2 a in FIG. 3A are arranged substantially symmetrically with the interposer plug 108 as the center. However, in this embodiment, the test interposer 2 0 2 a of the present invention is not made below the metal layer 106 because the process of the interposer is considered. However, the predetermined area surrounded by the test intervening plug may have other shapes, and is not limited to the circular shape of the predetermined area 3 02 in Fig. 3A. FIG. 3B is a schematic diagram illustrating another embodiment of the present invention. Please refer to Figure 3B. The test of the interposer plug 2 0 2 b will center on the interposer plug 1 0 8 and surround the interposer plug 1 0 8 to surround a predetermined area 3 0 4 and the shape of the predetermined area 3 0 4 It is a square. As described above, in addition to the circles and squares shown in FIGS. 3A and 3B, the predetermined area of the present invention can be used in various shapes as long as it can surround the interposer plug 108. in. The ability of the test pattern on the wafer to collect vacancies in the metal layer to prevent holes in the center of the interposer plug from being generated is determined by the area of a predetermined area surrounded by it. That is, if the area of the predetermined area is larger, its ability to collect vacancies in the metal layer to prevent holes at the bottom of the intervening plug in its center is worse. Conversely, the smaller the area of the predetermined area, the better its ability to collect vacancies in the metal layer to prevent holes in the center of the interposer from generating holes at the bottom. In order to test whether the interposer plug structure 100 will generate a hole caused by stress, in general, a semiconductor factory will perform a reliability test (r e 1 i a b i 1 y t e s t) after the interposer plug structure 100 is manufactured. As applied here

Page 12 1236095 _Case No. 92115454_ ^ V. Description of the invention (8) The test of amended A-degree test is mainly a test of thermal stress. The test condition is that the interposer plug structure 1 0 0 is placed at 1 7 5 ° After 500 hours in the environment of C, the electrical characteristics between the human layer 104 and the metal layer 106 are usually electrical resistance 'to check whether there is a hole in the bottom of the interposer plug Π2. Disconnection of plug 008 occurred. During the thermal stress test of the wafer, the vacancies in the metal layer 104 are driven by the thermal stress gradient and concentrated to form holes. In Fig. 1B, in the intervening cold structure 100, the vacancies in the metal layer 104 will usually gather at the bottom 1 12 of the intervening plug, causing the intervening plug 108 to break. "

The present invention uses the area enclosed by the test pattern in FIG. 2 (the area of the predetermined area 3 2 as shown in FIG. 3A) with a thermal stress test to detect whether the interconnect structure is likely to be generated by the thermal stress gradient. Holes. Because the test pattern of the present invention is composed of a plurality of test interposer plugs 202a, each of the test interposer plugs 202a has the ability to concentrate the voids in the metal layer 104. Therefore, the test pattern of the present invention can be used to adjust the area of the test interposer plug 002a around the predetermined area 3202 of the interposer plug 108, and then match the thermal stress test to determine the metal of the wafer. Effective void vacancy diffusion area for layer 1 0 4

FIG. 4 is a flowchart showing a method for testing the internal connection of the present invention in green. In step 401, a plurality of wafers having an interposer structure are provided, and the above-mentioned test patterns are formed on these wafers. These wafers with test patterns are then placed in a test environment. According to an embodiment of the present invention, the test environment is a thermal stress test environment, and its condition is i 7 5. Let it stand for 500 hours at 〇, as shown in step 402. Then in step 403, after the treatment in the test environment, measure the two metal layers of each wafer, namely the interposer plug.

Page 13 1236095 _Case No. 92115454_ Year Month Amendment_ Five. Description of the invention (9) electrical characteristics, such as resistance. After the above steps 401 to 403, the interposer structure of the wafer can be tested to see if it is prone to holes. In the following, various applications of the present invention are described separately to clearly explain the various application modes of the present invention. First, how to apply the test method of the present invention to test the effective void diffusion region of a wafer. A plurality of wafers are provided first, and the processing conditions of these wafers are the same. For example, the growth conditions of the metal layer or the process conditions of the interposer are the same, and these wafers all have the above-mentioned interposer structure. The test patterns of the present invention are then formed on these wafers. It is worth noting that the multiple wafers with the same process conditions mentioned above may be provided by cutting the same wafer into multiple small wafers, or multiple wafers with the same process conditions may be used. According to a preferred embodiment of the present invention, the test patterns on these different wafers have predetermined areas with the same shape, but different areas with different sizes. These wafers with test patterns are then placed in a test environment. After the test environment is processed, the electrical characteristics of the interposer, such as resistance, are measured between the two metal layers of each wafer. So 'because the predetermined areas of these wafers' have different area sizes, and the test pattern on each wafer has the ability to collect voids in the metal layer to prevent holes at the bottom of the plug in the center, It is determined by the area of the predetermined area surrounded by it. Therefore, when the area of the predetermined area is smaller than a certain area, there will be no holes at the bottom of the interposer plug, that is, the interposer plug will not be short-circuited. The present invention can use the area of the predetermined area to determine the effective void diffusion area of the metal layer of the wafer.

Page 14 1236095 _Case No. 92115454_ Year Month Day __ V. Description of the invention (10) The above-mentioned predetermined area may be changed due to some special applications in its shape or the number of intervening plugs formed in the test forming this predetermined area. . For example, different shapes of predetermined regions can be used on each wafer to test the effective void diffusion region of the metal layer of the wafer. At this time, the areas of these different shaped predetermined areas may have the same area. However, because different shapes have different collection capabilities for the vacancy of the metal layer, the combination of these predetermined areas to implement the test method of the present invention can also determine a Effective void diffusion area of the metal layer of the wafer. Furthermore, another implementation method of this application method is to change the number of interposer plugs in the test surrounding the predetermined area to test the effective void diffusion region of the metal layer of the wafer. For a predetermined area with the same shape and area, its ability to collect vacancies in the metal layer to prevent holes in the center of the intervening plug from being generated can be determined by the number of intervening plugs in the test that surrounds this predetermined area. If the number of intervening plugs in the test is smaller, its ability to prevent holes in the center of the intervening plug is worse. On the contrary, the greater the number of intervening plugs in the test, it is preventing the holes in the center of the intervening plug from being formed. The better your ability. Although the predetermined areas have the same shape and the same area size, the number of intervening plugs in the test surrounding the predetermined area is different. By using a combination of predetermined regions with different numbers but the same shape and area of these interposer plugs to implement the test method of the present invention, an effective void diffusion region of a metal layer of a wafer can also be determined. In addition to the above-mentioned application methods for testing the effective vacancy diffusion region of the metal layer of the wafer, the present invention can also be used to compare wafers with different process conditions, which is easy to generate holes in the bottom of the interposer because of thermal stress gradients

Page 15 1236095 Case No. 92115454 Amendment V. Description of the invention The following will say that it is easy to apply the above-mentioned pilot pattern first because of the application. The test pattern then passes through the test ring to interpose the plug area, which is the same hole as the circle where the holes are collected. The present invention is easy to remove the diffusion area because the present invention is applied to the wafer and it is a hole. Although the present invention (11) states that the test of this application invention is to provide a plurality of non-plugging structures for the thermal stress ladder in accordance with the present invention. Invented, the test environment of the test strip in the predetermined area has a test strip with the same electrical characteristics, area, and capability in the metal layer after the treatment. Method to compare wafers with different process conditions, and when a hole is generated at the bottom of the interposer, the wafers with the same process conditions have these. A preferred embodiment of the present invention is then formed on these wafers. The areas on these different wafers have the same shape and area. The patterned wafers are placed in a test environment, and between the two metal layers of each wafer is measured, that is, for example, resistance. Because the wafers are scheduled to be the same, the test pattern on each wafer is vacant to prevent the bottom of the interposer from being centered. In this way, it is possible to compare the wafers of different processes (predetermined areas of the same shape and area), in which the holes at the bottom of the plug are prone to produce holes, which can be used to test the effective vacancy of the metal layer in the wafer of the same process. It is used to compare wafers with different process conditions, which are caused by thermal stress gradients and holes in the bottom of the plug. The Ming test pattern and method are not only simple and systematic, and can be tested extensively for a new process condition to understand whether the application of this new process condition is prone to be formed at the bottom of the interposer structure due to thermal stress gradients and cause the interposer plug to break. Ming has disclosed the above with a preferred embodiment, but it is not intended to limit it. Any person skilled in the art will not depart from the spirit and scope of the present invention.

Page 16 1236095 Case No. 92115454 Amendment

Page 17 1236095 Case No. 92115454 Revised Schematic Brief Description [Schematic Description] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below. In conjunction with the accompanying drawings, detailed descriptions are as follows: FIG. 1A is a schematic perspective view showing a conventional plug structure between two metal layers. Figure 1B is a partial side view of Figure 1A. FIG. 2 is a schematic perspective view of a preferred embodiment of the present invention. Figure 3A is a top view of Figure 2. Figure 3B is a top view of another preferred embodiment of the present invention. FIG. 4 is a flow chart showing a method for testing the interconnections in the present invention. [Simple description of component representative symbols] 100 Intermediate plug structure 102 Dielectric layer 104 Metal layer 106 Metal layer 108 Intermediate plug 2 0 2 a, 2 0 2 b: Test interposer plug 2 0 4: Metal layers 302, 304: Scheduled area 4 (Π, 4 0 2, 4 0 3 ·· Procedure

Page 18

Claims (1)

1236095 Case No. 92115454 _ Amendment VI. Patent Application Scope 1. A test pattern for an interconnect, the interconnect is connected to a first metal layer separated by a dielectric layer with a first interposer plug And a second metal layer, the test pattern of the interconnect includes at least: a plurality of second interposer plugs arranged around the first interposer plug to surround a predetermined area, wherein the second interposer plugs are Located in the dielectric layer, and the first ends of the second interposer plugs are connected to the first metal layer. 2. The test pattern for interconnects as described in item 1 of the scope of patent application, wherein the material of the first metal layer is copper. 3. The test pattern for the interconnections as described in item 1 of the scope of the patent application, wherein the material of the second metal layer is copper. 4. The test pattern for interconnects as described in item 1 of the scope of patent application, wherein the material of the dielectric layer is a low dielectric material. 5. The test pattern of the inner wiring according to item 1 of the scope of patent application, wherein the material of the first interposer plug is copper. Φ 6. The test pattern of the interconnects as described in item 1 of the scope of the patent application, wherein the material of the second interposer plugs is copper. 7. The inner-connected test pattern as described in item 1 of the scope of patent application, where 1236095 _ case number 92115454_ year month date ___ 6, the scope of the patent application for the second intermediary plug is to use the first intermediary plug The plugs are arranged substantially symmetrically at the center. 8. The inner-line test pattern according to item 1 of the scope of patent application, wherein the second interposer plugs are arranged substantially symmetrically with the first interposer plug as the center, and each of the second The intermediate plug has a predetermined distance from the first intermediate plug, so that the predetermined area forms a circle. 9. The inner-line test pattern according to item 1 of the scope of patent application, wherein the predetermined area is a square. 10. The test pattern of the interconnects as described in item 1 of the scope of the patent application, wherein the second ends of the second interposer plugs are connected to a third metal layer. 1 1 · The test pattern of the interconnecting wire as described in item 10 of the scope of patent application, wherein the material of the third metal layer is copper. 1 2 · A method for testing an interconnect, the interconnect is connected to a first metal layer and a second metal layer separated by a dielectric layer with a first interposer plug. The test method includes at least the following steps: providing a plurality of wafers having the interconnects and forming an interconnect test pattern on each of the wafers, wherein the interconnect test pattern includes a plurality of second interposers Plugs, arranged around the first interposer plug to surround a predetermined area, the second interposer plugs are located in the dielectric layer, and the second interposer Page 20 1236095 ____Case No. 92115454_Year Month Date__ VI. One end of the patent application scope interposer is connected to the first metal layer; the wafers are placed in a reliability test environment, where the reliability The test environment has a predetermined temperature and a predetermined time; and measures the electrical characteristics of each of the first interposer plugs. 1 3 · The test method for interconnects as described in item 12 of the scope of patent application, in which the wafers have the same process conditions (recipe). 14. The test method for interconnects as described in item 12 of the scope of patent application, wherein the predetermined area of each of the wafers has the same shape. 1 5 · The test method for interconnects as described in item 12 of the scope of patent application, wherein the area of the predetermined area of each of the wafers is different. 16. The test method for interconnects as described in item 12 of the scope of the patent application, wherein the number of the second interposer plugs of each of the wafers is the same. 17. The test method for interconnecting as described in item 12 of the scope of patent application, wherein the reliability test environment is a reliability thermal stress test environment. 1 8. The test method for an internal connection as described in item 17 of the scope of patent application, wherein the predetermined temperature of the reliability thermal stress test environment is 1 751, and the predetermined time is 500 hours. Page 21 1236095 Case No. 92115454 Amendment 6 、 Applicable patent scope 1 9 _As described in the patent application scope item 12 inline test method, wherein the second intermediary plugs are based on the first The intervening plugs are arranged substantially symmetrically at the center. 2 0. The test method for interconnecting as described in item 12 of the scope of the patent application, wherein the second interposer plugs are arranged substantially symmetrically with the first interposer plug as the center, and each of these The second interposer plug has a predetermined distance from the first interposer plug, so that the predetermined area forms a circle. 2 1 _ The method for testing the interconnects as described in item 12 of the scope of patent application, wherein the predetermined area is a square. 2 2 · The test method for interconnecting as described in item 12 of the scope of patent application, wherein the step of measuring the electrical characteristics of each of the first interposer plugs includes at least measuring each of the first interposers The resistance value of the plug. Page 22