1235306 玖、發明說明： 【發明所屬之技術領域】 本發明係有關於一種位址表之管理方法及其相關裝置，特別地關 於媒體存取控制位址表之管理方法及其相關媒體存取控制晶片。 【先前技術】1235306 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for managing an address table and related devices, and particularly to a method for managing a media access control address table and related media access control. Wafer. [Prior art]
乙太網路交換器可以提供多埠之網路連結，每一個埠可供線速度 (line speed)10M/100M/1000M(lM=106)之全雙工資料傳收。乙太網路交 換器之核心為媒體存取控制器(medium access controller，簡稱MAC controller)，典型地負責網路七層運作中第二層及部分第三層以上之工 作’媒體存取控制器搞接實體層(physical layer，簡稱PHY)，以提供多 埠之網路連結，負責與遠端實體訊號之傳收。媒體存取控制器先暫存 所有連接埠所接收之封包資料，再轉送至指定之目的連接埠，媒體存 取控制器通常利用外掛記憶趙晶片或者内建整合之有限記憶體進行封 包資料之暫存，例如内建1M位元(相當於128K位元組)之靜態隨機存 取記憶體，而乙太網路交換器典型地為8埠/16埠/24埠，有限的記憶 體空間要同時供多個連接埠之資料暫存與轉送，因此記憶體之有效利 用非常重要。 乙太網路交換器接收到的封包可以區分為單播(uni—cast)封包、多播 (multi-cast)封包、以及廣播(broadcast)封包，單播封包從乙太網路交換 器其中一埠接收後從另一埠轉送出去，多播封包從乙太網路交換器其 中一埠接收後從其他複數個埠轉送出去，而廣播封包從乙太網路交換 器其中一埠接收後從其他所有埠轉送出去。一般而言，乙太網路封包 之最大長度為1522位元組長，而在NAS/SAN系統中更有9.6K(1K=103) 位元組長之特長封包(jumbo packet)之應用。媒體存取控制器利用外掛 或内建記憶體以緩衝暫存封包資料，媒體存取控制器於初始化階段便 規劃該外掛或内建之記憶體以建立適當的資料結構與格式，以利後續 之運用。 圖一顯示乙太網路封包100之結構，乙太網路封包1〇〇包含目的 1235306 媒體存取控制(destination medium access control，簡稱 DMAC)位址 110、來源媒體存取控制(source medium access control，簡稱 SMAC)位 址 120、酬載(payload)130、以及循環冗餘檢查碼(cyclic redundant code， 簡稱CRC)140,乙太網路交換器會利用内建之128K位元組之靜態隨機 存取記憶體，規劃出一塊位址表，用以記錄MAC位址與連接槔之間之 關聯性，以利乙太網路交換器自接收到乙太網路封包1〇〇後，能快速 地藉由查詢表格找到乙太網路封包100應該被轉送之連接埠，靜態隨 機存取記憶體大多是用來緩衝暫存從諸多連接埠湧入之乙太網路封 包，每個乙太網路封包進入乙太網路交換器之後，會利用SMAC位址 120與其來源埠(sourceport)，適當地記錄於位址表中(稱為學習過程）， 以供稍候之查詢，另一方面，乙太網路交換器會將DMAC位址110進 行查表，若可以找到對應資料，便可知道其相關聯之埠遮罩(port mask);但若無法查詢到對應資料，便會將其廣播出去。 圖二顯示雙槽位址表200之示意圖，習知之雙槽位址存取技藝， 舉例而言，將位址表200規劃成2K(K=21Q)個桶(bucket)，每個桶具有兩 個槽，可以用特定之桶位址指到桶之位置，桶210具有槽210A及槽 210B，而桶220具有槽220A及槽220B，也就是說，共有2K個桶， 每個桶具有A槽與B槽，每個槽用以顯示一 MAC位址之相關資訊， 每個MAC位址具有48位元，以MAC[47 : 0]表示之，因此最多可以 記載4K筆MAC位址之相關資訊，可以利用直接映射(direct map)或者 雜湊(hash)映射之方式，將每個欲記載之MAC位址映射至特定的桶位 址以及槽，典型地，於MAC位址學習階段，每個MAC位址可利用 CRC-11多項式雜湊運算得到雜湊值Hash[10 : 0]共11位元之桶位址， 例如映射到桶250，優先選擇存入槽250A，如果槽250已經存在資料， 才選擇存入槽250B，以將MAC[47 : 11]共37位元及該MAC位址之相 關資訊存入。若直接採用直接映射方式，則將MAC[10 : 0]當做是桶位 址，以將MAC[47 : 11]共37位元及該MAC位址之相關資訊存入適當 之槽中；採用雜湊映射之優點係用來增加MAC位址之混亂度，以避免 1235306 鄰近MAC位址搶用同一位址桶中之A槽與B槽，而增加廣播送出封 包之機會。 當查詢乙太網路封包之DMAC位址時，利用DMAC位址進行 CRC-11多項式雜湊運算得到雜湊值Hash[10 : 〇]共11位元之桶位址， 例如映射到桶250，優先比對槽250A，如果槽250中之MAC[47 : 11] 資料與乙太網路封包之DMAC[47: 11]相同，則可以獲得其相關聯之資 訊，若與槽250A不吻合，才選擇比對槽250B中之MAC[47 : 11]，若 是其A槽與B槽之MAC位址皆不吻合，則將其廣播轉送出去。 要從有限之靜態隨機存取記憶體劃分出一部份位址表供查詢，能 夠記錄之項目(entry)有限，而如何有效率的運用極有限之位址表實有關 於乙太網路交換器之交換效率，也確實是乙太網路交換器之媒體存取 控制器之一大課題。 【發明内容】 本發明揭示一種媒體存取控制位址(簡稱MAC位址)之學習方法， 包含下列步驟··藉由雜湊函數將該體存取控制位址運算出雜湊值，而 根據該雜湊值一對一地映射該指定槽，而根據MAC位址映射至位址表 之指定槽以及伴隨槽；若指定槽是空的，則將MAC位址學習至指定 槽，以及若指定槽係非空的、伴隨槽係空的、且指定槽之内容係非靜 態的，則將指定槽之内容搬移至伴隨槽，並修改伴隨槽内容中之較高 部MAC位址之第四十位元，然後將mac位址學習至指定槽中。更進 一步地，若指定槽係非空的且伴隨槽係非空的，則將MAC位址學習進 CAM中；而若指定槽係非空的且伴隨槽係空的，則修改位址之 較高部MAC位址之第四十位元，並將該修改過後之位址學習至 伴隨槽中，以回應於非靜態學習命令，因此發揮雙槽式位址表之學習 優點，又可節省位址表之硬體閘數。舉例而言，位址表共有2x個存取 槽，而各存取槽可用以存取MAC位址之(48-X)個位元及相關資訊，而 MAC位址係為四十人個位元，其中X麟―正整數，相，訊較佳地 包含埠遮罩、逾時計數器、以及靜態旗標。 1235306 本發明亦揭示一種mac位址之查詢方法，包含下列步驟··根據 MAC位址映射至位址表之指定槽以及伴隨槽；將指定槽之第一内容及 伴隨槽之第二魄讀出；選擇性地還原該第二内容；將MAC位址與第 一内容進行比較以及將MAC位址與還原之第二内容進行比較；以及根 據該些比較結果產生查詢結果，例如埠遮罩，舉例而言，選擇性地還 原步驟係根據第二内容之靜態旗標以及較高部MAC位址之第四十位 元選擇性地還原該第二内容。 本發明進一步揭示一種媒體存取控制晶片，包含··具有位址表之 緩衝記憶體，用以暫存封包；用以耦接實體層控制晶片之複數個連接 埠控制單元；具有内容可定址記憶體(簡稱CAM)i轉送控制單元，耦 接於連接埠控制單元；耦接轉送控制單元及連接埠控制單元之佇列控 制單元；以及用以耦接該緩衝記憶體、該佇列控制單元及該些連接埠 控制單兀之緩衝器控制單元；其中，轉送控制單元根據MAC位址映射 至位址表之指定槽以及伴隨槽，若指定槽是空的，則將MAC位址學習 至指定槽；而若指定槽係非空的、伴隨槽係空的、且指定槽之内容係 非靜態的，則將指定槽之内容搬移至伴隨槽，並修改伴隨槽内容中之 較咼部MAC位址之第四十位元，然後將mac位址學習至指定槽中。 【實施方式】 將圖二位址表200規劃成2K個存取桶，每個桶具有a槽與B槽， 根據本發明之一較佳具體實施例，可以採用CRC_12(或者直接映射法） 多項式雜湊運算得到雜湊值Hash[ll :〇]共12位元之位址，以雜湊映射 到特定槽之位置，舉例而言，採用Ρ^+χ^+χΒ+χΖ+χ+Ο之CRC_12多 項式雜湊運算得到雜湊值Hash[ll: 0]共12位元之雜湊位址，Hash[ll :The Ethernet switch can provide multi-port network connections, and each port can transmit and receive full-duplex data at line speed of 10M / 100M / 1000M (lM = 106). The core of the Ethernet switch is a medium access controller (MAC controller), which is typically responsible for the second layer and part of the third layer and above in the operation of the seven layers of the network. The physical layer (PHY) is connected to provide a multi-port network connection and is responsible for transmitting and receiving remote physical signals. The media access controller first temporarily stores the packet data received by all the ports, and then transfers it to the designated destination port. The media access controller usually uses the external memory Zhao chip or the built-in integrated limited memory to temporarily store the packet data. Storage, such as built-in 1M bit (equivalent to 128K bytes) of static random access memory, while Ethernet switches are typically 8-port / 16-port / 24-port, and limited memory space must be at the same time For the temporary storage and transfer of data from multiple ports, the effective use of memory is very important. The packets received by the Ethernet switch can be divided into unicast packets, multicast packets, and broadcast packets. Unicast packets are received from one of the Ethernet switches. After receiving the port, it is forwarded from the other port. Multicast packets are forwarded from one port of the Ethernet switch. After receiving the packets, it is forwarded from one of the other ports. The broadcast packets are received from one port of the Ethernet switch. All ports are forwarded. Generally speaking, the maximum length of an Ethernet packet is 1522 bytes, and in the NAS / SAN system, there is an application of a jumbo packet with a length of 9.6K (1K = 103) bytes. The media access controller uses plug-in or built-in memory to buffer the temporarily stored packet data. During the initialization phase, the media access controller plans the plug-in or built-in memory to establish an appropriate data structure and format for subsequent use. use. Figure 1 shows the structure of Ethernet packet 100. Ethernet packet 100 includes destination 1235306 destination medium access control (DMAC) address 110, source medium access control (source medium access control). , Abbreviated as SMAC, address 120, payload 130, and cyclic redundant check code (CRC) 140, the Ethernet switch will use the built-in static random storage of 128K bytes. Take the memory and plan an address table to record the association between the MAC address and the connection card so that the Ethernet switch can quickly receive the Ethernet packet 100. Find the port to which the Ethernet packet 100 should be forwarded through the query table. Most of the static random access memory is used to buffer the temporary Ethernet packet inflow from many ports. Each Ethernet After the packet enters the Ethernet switch, it will use the SMAC address 120 and its source port (sourceport) to appropriately record it in the address table (called the learning process) for later inquiry. On the other hand, B Ethernet switch The DMAC address 110 will be looked up in the table. If the corresponding data can be found, the associated port mask will be known; but if the corresponding data cannot be queried, it will be broadcast. Figure 2 shows a schematic diagram of the dual-slot address table 200. The conventional dual-slot address access technique is, for example, planning the address table 200 into 2K (K = 21Q) buckets, each bucket having two buckets. You can use a specific bucket address to point to the location of the bucket. Bucket 210 has slots 210A and 210B, and bucket 220 has slots 220A and 220B. That is, there are 2K buckets in total, and each bucket has an A slot. With slot B, each slot is used to display related information of a MAC address. Each MAC address has 48 bits, which is represented by MAC [47: 0], so it can record up to 4K related MAC addresses. You can use direct mapping or hash mapping to map each MAC address to be recorded to a specific bucket address and slot. Typically, during the MAC address learning phase, each MAC The address can use the CRC-11 polynomial hash operation to obtain a hash value of Hash [10: 0], which is a total of 11-bit bucket addresses. For example, if it is mapped to bucket 250, it is preferred to store it in slot 250A. The storage slot 250B is used to store a total of 37 bits of MAC [47:11] and related information of the MAC address. If direct mapping is used directly, MAC [10: 0] is used as a bucket address to store MAC [47:11] a total of 37 bits and relevant information of the MAC address into the appropriate slot; hashing is used The advantage of mapping is to increase the confusion of MAC addresses, to avoid 1235306 adjacent MAC addresses from grabbing slots A and B in the same address bucket, and increasing the chance of sending packets by broadcast. When querying the DMAC address of an Ethernet packet, use the DMAC address to perform a CRC-11 polynomial hash operation to obtain a hash value Hash [10: 〇] with a total of 11-bit bucket addresses, such as mapping to bucket 250. For slot 250A, if the MAC [47: 11] data in slot 250 is the same as the DMAC [47: 11] of the Ethernet packet, the associated information can be obtained. If it does not match the slot 250A, the ratio is selected. For MAC [47: 11] in slot 250B, if the MAC addresses of slot A and slot B do not match, the broadcast is forwarded. To partition a part of the address table from the limited static random access memory for query, the entries that can be recorded are limited, and how to efficiently use the extremely limited address table is really about Ethernet exchange Switching efficiency is indeed a major issue for media access controllers of Ethernet switches. [Summary of the Invention] The present invention discloses a learning method of a media access control address (referred to as a MAC address for short), which includes the following steps: a hash value is calculated from the body access control address by a hash function, and according to the hash The value maps the designated slot one-to-one, and maps to the designated slot and accompanying slot of the address table according to the MAC address; if the designated slot is empty, the MAC address is learned to the designated slot, and if the designated slot is not The empty, companion slot is empty, and the content of the designated slot is non-static, then the content of the designated slot is moved to the companion slot, and the fortieth bit of the higher MAC address in the companion slot content is modified. Then learn the mac address into the specified slot. Further, if the designated slot system is not empty and the accompanying slot system is not empty, the MAC address is learned into the CAM; and if the designated slot system is not empty and the accompanying slot system is empty, the comparison of the address is modified. The fortieth bit of the upper MAC address, and the modified address is learned into the companion slot in response to the non-static learning command. Therefore, the learning advantages of the dual-slot address table can be used, and the bit can be saved. Number of hardware gates in the address table. For example, the address table has a total of 2x access slots, and each access slot can be used to access the (48-X) bits of the MAC address and related information, and the MAC address is forty people. Yuan, where X Lin-positive integer, phase, message preferably includes a port mask, a timeout counter, and a static flag. 1235306 The present invention also discloses a method for querying a MAC address, which includes the following steps: · Mapping to a designated slot and a companion slot of an address table according to the MAC address; reading the first content of the designated slot and the second companion of the companion slot Selectively restore the second content; compare the MAC address with the first content and compare the MAC address with the restored second content; and generate a query result based on the comparison results, such as a port mask, for example In other words, the selective restoring step is to selectively restore the second content according to the static flag of the second content and the fortieth bit of the upper MAC address. The invention further discloses a media access control chip, which includes a buffer memory with an address table for temporarily storing packets; a plurality of port control units for coupling to a physical layer control chip; and a content addressable memory Body (referred to as CAM) i transfer control unit, coupled to the port control unit; queue control unit coupled to the transfer control unit and the port control unit; and for coupling the buffer memory, the queue control unit and The port control unit controls the buffer control unit of the unit. Among them, the transfer control unit maps to the designated slot and the companion slot of the address table according to the MAC address. If the designated slot is empty, the MAC address is learned to the designated slot. ; If the designated slot is non-empty, the accompanying slot is empty, and the content of the designated slot is non-static, the content of the designated slot is moved to the companion slot, and the MAC address of the higher part of the companion slot is modified Forty bits, then learn the mac address into the specified slot. [Embodiment] The address table 200 in FIG. 2 is planned into 2K access buckets, each bucket having a slot and B slot. According to a preferred embodiment of the present invention, a CRC_12 (or direct mapping method) polynomial can be used. The hash operation obtains a hash value of Hash [ll: 〇] with a total of 12 bits. The hash is mapped to the position of a specific slot. For example, the CRC_12 polynomial hash of P ^ + χ ^ + χΒ + χZ + χ + 〇 The hash value of the hash value Hll [ll: 0] is 12 bits. Hash [ll:
1]指定桶位址，而由Hash[0]指定是哪一個槽，舉例而言，Hash[0]為〇 代表A槽’而Hash[0]為1代表B槽，所以每個MAC位址之雜湊結果 Hash[ll : 0]皆指定到特定之槽，於MAC位址學習階段，將MAC[47 : 12]共36位元及該MAC位址之相關資訊存入。相較於習知技藝，每個 MAC位址可節省一個位元，於此實施例中，最多可以記載4K筆MAC 1235306 位址之相關資訊，共可節省4K位元，對於有限之記憶體空間而言，具 有顯著之成本效益。 媒體存取控制器利用轉送控制單元(未示)進行MAC位址及其相關 資訊之查詢及學習功能，MAC位址及其相關資訊之學習，可以區分為 單播位址以及多播位址之學習，關於單播位址之學習，可以利用每一 個接收到之封包之SMAC位址及其來源埠建立該MAC位址之相關資 訊，以利後續欲傳給該SMAC位址之封包查詢之用；關於多播位址之 學習，則可由媒體存取控制器外掛一顆處理器或者由網管人員利用軟 體規劃於位址表200中。 於此較佳實施例中，媒體存取控制器内實施内容可定址記憶體 (content access memory，簡稱CAM)儲存複數筆位址以進行完美匹配 (perfect match)查詢，例如提供8筆MAC位址之學習與查詢；將單播位 址及多播位址之學習分類為動態(dynamic)學習及靜態(static)學習，於外 掛處理器之例子中，多播位址之學習較佳地皆由處理器經由前述位址 映射方式規劃於位址表200中指定位置，並且會長期停駐於該指定位 置，不會進行逾時(aging)淘汰。每個MAC位址具有48位元，以 MAC[47 : 0]表示，由其中之MAC[40]顯示該MAC位址是否為多播位 址0 就MAC位址之學習而言，在MAC位址之雜湊結果Hash[ll : 0] 之Hash[0]為0，且Hash[ll : 1]所指之桶之A槽内容也擊中(hit) MAC 位址之較高部分MAC[47 ·· 12]之情況下（擊中代表内容比對吻合），當 收到靜態學習之「靜態清除(clear)」指令時，則直接清除Hash[ll : 1] 所指之桶之A槽内容；而當收到靜態學習之「靜態增加(add)」指令時， 也直接將MAC位址之較高部分MAC[47 : 12]及其相關資訊寫入 Hash[ll : 1]所指之桶之A槽中。 圖三顯示根據本發明之具體實施例之一 MAC位址學習流程圖，當 接收到封包時，封包包含有DMAC位址以及SMAC位址，由步驟300 開始，步驟310首先查詢MAC位址，步驟312判斷是否擊中CAM或 1235306 MAC位址表，若擊中則步驟314可更新MAC位址之相關資訊，包括 埠遮罩以及逾時計數器等相關資訊，然後結束流程；若未擊中則由步 驟320判斷是否指定槽是空的，若指定槽是空的，則步驟直接將 MAC位址之較高部分MAcp? : 12]及相關資訊寫入；若指定槽不是空 的，則步驟330判斷是否Hash[ll :0]所代表桶之相關伴隨槽為空的， 其中若Hash[ll : 0]指定槽為A槽，則相關伴隨槽為b槽，反之亦然； 若伴隨槽為非空，則步驟332檢查CAM中是否有空位或者非靜態項目 已經老舊者，再由步驟334將欲學習之MAC位址寫入CAM中空位或 者非靜態項目已經老舊者，然後結束流程，其中所謂項目老舊係可依 照設計者之彈性而不同，舉例而言，若逾時計數器設計為計數3至〇， 可以視當計數器值小於3者皆為老舊，以避免非靜態項目佔據CAM過 長之時間；若沒有適當地方可以寫入，則步驟336將學習内容丟棄， 然後結束流程；若伴隨槽為空，則步驟340檢查Hash[ll : 0]之指定槽 是否為非靜態（non-static);若指定槽為非靜態，則步驟342將指定槽 之非靜態内容搬移至相關伴隨槽，並將相關伴隨槽中MAC位址之第四 十位元(MAC[39])更改為1，最後由步驟344將欲學習之mac位址(包 括靜態與非靜態MAC位址)增加至Hash[ll : 0]之指定槽，然後結束流 程；若Hash[ll : 0]之指定槽之内容為靜態項目；則步驟350根據此命 令是否為靜態學習命令而執行步驟332或360，若為靜態學習命令前進 至步驟332，將欲學習之MAC位址寫入CAM中空位或者非靜態項目 已經老舊者，或者將學習内容丟棄；若為非靜態學習命令，則步驟360， 將欲學習之MAC位址及相關資訊寫入相關伴隨槽，並將相關伴隨槽中 MAC位址之第四十位元(MAC[39])更改為1，於步驟370結束此學習流 程。 於前述揭示之MAC位址學習流程中，靜態增加(static-add)之學習 命令，將欲學習之MAC位址可增加至指定槽或CAM中，而非靜態項 目與非靜態增加之學習命令可以利用指定槽、相關伴隨槽以及CAM進 行學習’非靜態項目可以記錄於或搬移至相關伴隨槽中，並藉由修改 1235306 第四十位元之值而予以辨識。 圖四，示根據本發明之具體實施例之—儲存槽結構，儲存槽結構 包括’較高部MAC位址及相關資訊，而祖。位址之相關資訊較 佳地包括有痒遮罩(p0rtmask)42()、逾時計數器43〇、以及靜態旗標物， 逾時計數器430用以計數非靜態學f之時間狀態，舉例而言，逾時計 數器430為兩個位元計數，包括3、2、卜〇，用以計數3⑽秒之時間 長度’當逾時计數器43〇由3倒數至〇時，代表這個館存槽中之非靜 態項目已經逾時，當下次有任何靜態或非靜態項目欲使用這個儲存槽 儲存MAC位址資訊時，皆可予以覆蓋過去。 圖五顯示根據本發明之具體實施例之- MAC位址查詢流程圖，其 滅參考於圖三之學習流程，由步驟5〇〇開始，步驟51〇首先看收到參 之封包是否為CRC正確，若CRC不正確則步驟515將封包丟棄；若 封包之CRC正霉’則步驟no檢查是否擊中c·，若擊中匸施則步 驟仍可快速地回報痒遮罩；若未擊中c·則應進一步查詢雙槽位址 表200 ’相應於圖三之流程，步驟53〇將封包之DMAC位址進行crci2 雜湊運算得聰湊值Η_1:縣12位元之祕概，_他拳：’ 1]獲得桶紐，由HaSh_旨定哪_靖為指定槽；步驟54()，根據雜 - 凑值Hash[ll : 0]將指定槽與糊伴隨槽之内容同時讀出來，·步驟55〇 檢查是否DMAC位址擊中指定槽，若擊中指定槽則步驟525回報蜂遮 罩；若未擊中指定槽則步驟560利用靜態旗標檢查被讀丨之相關伴隨籲 槽之内容是否為靜態’若相關伴隨槽之内容為靜態 束；若相關伴隨槽之内容為非靜態項目，檢查其内容之第=== 否為1 ’若第四十位元為0表示其學習過程中係佔據指定槽，故由步驟 580結束查詢流程；若第四十位元為i，則表示此項目於學習過程中係 佔據相關槽，於是步驟575將相關伴隨槽之内容之第四十位元 (MAC[39])由1修改還原為〇然後將還原後之較高部位址與封包 之DMAC位址進行比對，若是封包之DMAC位址擊中還原後之較高 部MAC位址’則回報蟑遮罩，否則便由步驟测結束查詢流程，若此 11 1235306 MAC位址查詢流程皆未查詢到適當結果，則應將封包廣播出去。 圖六顯示根據本發明之硬體方塊圖之一具體實施例，乙太網路交 換器之内主要包含媒體存取控制(media access c〇ntr〇1，簡稱MAC)晶片 600，以及實體層控制(phySicai iayerc〇ntr〇1，簡稱ρΗγ^晶片68〇，較佳 地，媒體存取控制晶片600藉由精簡媒體獨立界面(reduced medium independent interface ’簡稱RMII)耦接實體層控制晶片58〇。媒體存取 控制晶片600包含連接埠控制(p〇rt contr〇i)單元61〇至617(以前述八埠 乙太網路交換器為例，分別對應埠0至埠7)、轉送控制(f〇rwarding control)單元620、佇列控制(queue contr〇i)單元63〇、緩衝器控制單元 650、以及緩衝記憶體660 ,連接埠控制單元61〇耦接轉送控制單元 620、佇列控制單元630以及緩衝器控制單元65〇，緩衝器控制單元65〇 輕接緩衝記憶體660 ’緩衝記憶體660中規劃有位址查詢表，而轉送控 制單元620中以硬體實施可儲存複數個mac位址及相關資訊之 CAM622。實體層控制晶片680負責乙太網路交換器對外實體電氣訊號 之傳收，而以上本發明所揭示之流程方法則與媒體存取控制晶片6〇〇 内部之轉送控制單元620之運作設計有關，舉例而言，由乙太網路交 換器之埠0所接收到封包資料，經由實體層控制晶片680首先到達連 接埠控制單元610，封包之DMAC位址藉由本發明之查表方式(k)〇k_up table)產生對應之埠遮罩，而封包之SMAC位址藉由本發明之學習方式 將較高部SMAC位址學習(learn)進有限之查詢表662或CAM622中， 並由緩衝器控制單元650於緩衝記憶體660配置(allocate)適當之緩衝器 大小以供該封包資料之暫存，然後由佇列控制單元63〇根據埠遮罩建 立佇列連結，佇列控制單元630可依照各埠之輸出佇列長度判斷各連 接埠消粍緩衝記憶體660之狀況，而發訊給連接琿控制單元61〇適當 地進行擁塞控制(congestion control)。根據本發明之揭示，雙槽式查詢 表662藉由每個maC位址可以將每個桶之雙槽架構區分為指定槽及伴 隨槽，並利用第四十位元與靜態旗標進行MAC位址之靜態學習與非靜 態學習，而節省查詢表662之實際空間，另一方面，於位址查詢階段 12 1235306 也可增加查詢效能，利用CAM622可於轉送控制單元620同時對複數 個MAC位址進行硬體比對，於一個時脈後即可知道是否擊中 CAM622，而由查詢表662利用DMAC位址同時將指定槽及伴隨槽讀 回，將伴隨槽之内容選擇性地還原，同時判斷是否擊中指定槽或伴隨 槽，而回報相關結果。 圖六之實施例依照製程之進步可有不同程度之整合實施方式，舉 例而言，緩衝記憶體660可以整合於媒體存取控制晶片600之中或者 是外掛晶片，依照存取速度不同可以是靜態隨機存取記憶體(SRAM)、 同步動態隨機存取記憶體(SDRAM)、或者DDR動態隨機存取記憶體等 等，實體層控制晶片680由於製程特殊以及需要提供多個埠之實艘層 控制，通常屬於外掛晶片，但隨著未來整合度提高也有可能整合進媒 體存取控制晶片600之中。 縱上所述，本發明揭示一種媒體存取控制位址(簡稱MAC位址)之 學習方法，包含下列步驟：藉由雜湊函數將該體存取控制位址運算出 雜湊值，而根據該雜湊值一對一地映射該指定槽，而根據MAC位址映 射至位址表之指定槽以及伴隨槽；若指定槽是空的，則將mac位址學 習至指定槽；以及若指定槽係非空的、伴隨槽係空的、且指定槽之内 容係非靜態的，則將指定槽之内容搬移至伴隨槽，並修改伴隨槽内容 中之較高部MAC位址之第四十位元，然後將MAC位址學習至指定槽 中。更進一步地，若指定槽係非空的且伴隨槽係非空的，則將MAC位 址學習進CAM中；而若指定槽係非空的且伴隨槽係空的，則修改mac 位址之較高部MAC位址之第四十位元，並將該修改過後之mac位址 學習至伴隨槽中，以回應於非靜態學習命令，因此發揮雙槽式位址表 之學習優點，又可節省位址表之硬體閘數。舉例而言，位址表共有2X 個存取槽，而各存取槽可用以存取MAC位址之(48_X)個位元及相關資 訊，而MAC位址係為四十八個位元，其中X係為一正整數，相關資 訊較佳地包含埠遮罩、逾時計數器、以及靜態旗標。 本發明亦揭示一種MAC位址之查詢方法，包含下列步驟：根據 13 1235306 MAC位址映射至位址表之指定槽以及伴隨槽；將指定槽之第一内容及 伴隨槽之第二内容讀出；選擇性地還原該第二内容；將MAC位址與第 一内容進行比較以及將MAC位址與還原之第二内容進行比較；以及根 據該些比較結果產生查詢結果，例如埠遮罩，舉例而言，選擇性地還 原步驟係根據第二内容之靜態旗標以及較高部MAC位址之第四十位 元選擇性地還原該第二内容。 本發明進一步揭示一種媒體存取控制晶片，包含：具有位址表之 緩衝記憶體，用以暫存封包；用以耦接實體層控制晶片之複數個連接 埠控制單元；具有内容可定址記憶體(簡稱CAM)之轉送控制單元，耦 接於連接埠控制單元；搞接轉送控制單元及連接埠控制單元之仔列控 制單元；以及用以耦接該緩衝記憶體、該佇列控制單元及該些連接埠 控制單元之緩衝器控制單元；其中，轉送控制單元根據MAC位址映射 至位址表之指定槽以及伴隨槽，若指定槽是空的，則將MAC位址學習 至指疋槽，而若指定槽係非空的、伴隨槽係空的、且指定槽之内容係 非靜態的，則將指定槽之内容搬移至伴隨槽，並修改伴隨槽内容中之 較高部MAC位址之第四十位元，然後將mac位址學習至指定槽中。 以上所揭示之具體實施例之說明及圖式，係為便於闡明本發明之 技術内容及技術手段’並不欲拘限本發明之範脅。舉凡一切針對本發 明之結構細部修飾、變更，或者是元件之等效替代、置換，當不脫離 本發明之發明精神及範疇，其範圍將由以下之申請專利範圍來界定之。 【圊式簡單說明】 圖一係顯示乙太網路封包之結構； 圖二顯示雙槽位址表之示意圊； 圖三顯示根據本發明之具艘實施例之一 MAC位址學習流程圖； 圖四顯不根據本發明之具艘實施例之一儲存槽結構； 圖五顯示根據本發明之具艘實施例之一MAC位址查詢流程圖； 圖六顯示根據本發明之硬體方塊圖之一具體實施例。 1235306 110 目的位址 130 酬載 200 位址表 【元件符號簡單說明】 100 乙太網路封包 120 來源位址 140循環冗餘檢查碼 210、220、250 存取桶 210A、210B、220A、220B、250A、250B 存取槽 300 開始 312擊中？ 310 查詢MAC位址 314更新該MAC位址之相關資訊 320 Hash[ll:0]之指定槽是空的？ 322執行寫入命令 φ 330 Hash[ll:0]之伴隨槽是空的？ 332 CAM中有空位或者非靜態項目已經老舊者？ 334寫入學習内容至CAM 336丟棄學習内容 340 Hash[ll:0]之指定槽之内容為非靜態的？ 瀹 342將指定槽之内容搬移至伴隨槽，並將第四十位元修改為i 344將學習内容寫入指定槽 · 350靜態學習？ 360將學習内容寫入至伴隨槽，並將第四十位元修改為1 370結束 鲁 410較高部MAC位址 420埠遮罩 430逾時計數器 440靜態旗標 500 開始 510 CRCOK? 515丟棄封包 520擊中CAM? 525回報埠遮罩 530回報埠遮罩 540將Hash[ll:〇]之指定槽與相關伴隨槽同時讀出 550 DMAC擊中指定槽？ 560相關伴隨槽内容為靜態？ 15 伴隨槽内容之第四十位元為1 ? 擊中還原後之伴隨槽内容？ 結束 媒體存取控制晶片 610〜617連接埠控制單元 轉送控制單元 622 CAM 仔列控制單元 650緩衝器控制單元 緩衝記憶體 實艎層控制晶片 662位址表 161] Specify the bucket address, and Hash [0] specifies which slot. For example, Hash [0] is 0 for slot A 'and Hash [0] is 1 for slot B, so each MAC address The hash result Hash [ll: 0] is assigned to a specific slot. In the MAC address learning phase, a total of 36 bits of MAC [47: 12] and related information of the MAC address are stored. Compared with the conventional technique, each MAC address can save one bit. In this embodiment, a maximum of 4K MAC 1235306 addresses can be recorded, and a total of 4K bits can be saved. For limited memory space In terms of cost effectiveness. The media access controller uses the transfer control unit (not shown) to query and learn the MAC address and related information. The learning of the MAC address and related information can be divided into unicast addresses and multicast addresses. Learning. For the learning of unicast address, you can use the SMAC address of each received packet and its source port to establish the relevant information of the MAC address, so as to facilitate the subsequent query of packets that are to be sent to the SMAC address. ; About the learning of the multicast address, the processor can be plugged into the address table 200 by a processor attached to the media access controller or by a network administrator using software. In this preferred embodiment, a content access memory (CAM) is implemented in the media access controller to store a plurality of addresses for perfect match query, for example, to provide 8 MAC addresses. Learning and querying; classify unicast address and multicast address learning into dynamic learning and static learning. In the case of plug-in processors, the learning of multicast addresses is best performed by The processor is planned at a specified position in the address table 200 through the foregoing address mapping method, and will be parked at the specified position for a long time without performing aging elimination. Each MAC address has 48 bits, which is represented by MAC [47: 0]. The MAC [40] in it shows whether the MAC address is a multicast address. 0 For the learning of MAC addresses, The hash result of the address Hash [ll: 0] is 0, and the contents of slot A of the bucket indicated by Hash [ll: 1] also hit (hit) the higher part of the MAC address MAC [47 · · In the case of 12] (hits the content content match), when receiving the "static clear" instruction of static learning, it will directly clear the contents of the A slot of the bucket indicated by Hash [ll: 1]; And when receiving the "static add" instruction of static learning, the higher part of the MAC address MAC [47: 12] and its related information are also directly written into the bucket indicated by Hash [ll: 1] A slot. FIG. 3 shows a MAC address learning flowchart according to a specific embodiment of the present invention. When a packet is received, the packet includes a DMAC address and an SMAC address, starting from step 300, and step 310 first queries the MAC address. 312 determines whether the CAM or 1235306 MAC address table is hit. If it is hit, step 314 can update the relevant information of the MAC address, including the port mask and the timeout counter, and then the process is ended; if it is not hit, it is determined by Step 320 determines whether the designated slot is empty. If the designated slot is empty, the step directly writes the higher part of the MAC address MAcp ?: 12] and related information. If the designated slot is not empty, step 330 determines Whether the associated companion slot of the bucket represented by Hash [ll: 0] is empty, where if Hash [ll: 0] specifies slot A, then the associated companion slot is b, and vice versa; if the companion slot is non-empty Then, step 332 checks whether there are vacancies or non-static items in the CAM are old, and then the step 334 writes the MAC address to be learned into vacant or non-static items in the CAM, and then ends the process. Old projects can be relied on It varies according to the designer ’s flexibility. For example, if the timeout counter is designed to count from 3 to 0, you can treat the counter value as less than 3 as old to avoid non-static items occupying the CAM for too long; if not If it can be written in an appropriate place, step 336 discards the learning content and then ends the process; if the accompanying slot is empty, step 340 checks whether the specified slot of Hash [ll: 0] is non-static; if the specified slot If it is non-static, then step 342 moves the non-static content of the specified slot to the associated companion slot, and changes the fortieth bit (MAC [39]) of the MAC address in the associated companion slot to 1, and finally it is changed by step 344 The mac address (including static and non-static MAC addresses) to be learned is added to the designated slot of Hash [ll: 0], and then the process is ended; if the content of the designated slot of Hash [ll: 0] is a static item, then steps 350 performs step 332 or 360 according to whether this command is a static learning command. If it is a static learning command, proceed to step 332, and write the MAC address to be learned into a vacancy in the CAM or the non-static project is old, or will learn Content discarded; if not static Learning command, step 360, write the MAC address and related information to be learned into the associated companion slot, and change the fortieth bit (MAC [39]) of the MAC address in the associated companion slot to 1, and in step 370 ends this learning process. In the previously disclosed MAC address learning process, a static-add learning command can add a MAC address to be learned to a specified slot or CAM, instead of static items and non-statically added learning commands. Using designated slots, related companion slots, and CAM for learning 'Non-static items can be recorded or moved to related companion slots and identified by modifying the value of the fortieth bit of 1235306. FIG. 4 shows a storage tank structure according to a specific embodiment of the present invention. The storage tank structure includes a 'higher MAC address and related information, and an ancestor. The address-related information preferably includes a p0rtmask 42 (), a time-out counter 43, and a static flag. The time-out counter 430 is used to count the time status of non-static learning f, for example. The overtime counter 430 counts two bits, including 3, 2, and 0. It is used to count the length of 3 seconds. When the overtime counter 43o counts down from 3 to 0, it represents the library slot. The non-static item has timed out. It can be overwritten when there is any static or non-static item to use this storage slot to store MAC address information next time. Figure 5 shows a MAC address query flow chart according to a specific embodiment of the present invention, which is referenced to the learning flow of Figure 3. It starts from step 500 and step 51 starts with checking whether the received packet is CRC correct. If the CRC is incorrect, then step 515 will discard the packet; if the CRC of the packet is bad, then step no checks whether it hits c ·, if it hits the application, the step can still quickly report the itch mask; if it does not hit c · You should further query the double-slot address table 200 'corresponding to the process in Figure 3. Step 53: The DMAC address of the packet is crci2 hashed to get a smart value. _1: The secret of the 12-bit county, '1] Obtain a bucket button, which is determined by HaSh___ which is designated slot; step 54 (), read out the contents of the specified slot and the paste accompanying slot at the same time according to the hash-value Hash [ll: 0], step 55. Check whether the DMAC address hits the designated slot. If the designated slot is hit, step 525 returns a bee mask; if the designated slot is not hit, then step 560 uses a static flag to check whether the content of the associated accompanying appeal slot is read. Is static 'if the content of the associated companion slot is a static bundle; if the content of the associated companion slot is It is a non-static item. Check if its content is === No. 1 'If the fortieth bit is 0, it means that the designated slot is occupied during the learning process, so the query process ends at step 580; if the fortieth bit is i, it means that this item occupied the relevant slot during the learning process, so step 575 will modify the fortieth bit (MAC [39]) of the content of the associated companion slot from 1 to 0 and then restore the higher part after the reduction The address is compared with the DMAC address of the packet. If the DMAC address of the packet hits the higher MAC address after restoration, the cockroach mask is reported; otherwise, the query process is completed by step test. If this 11 1235306 MAC bit If no proper result is found in the address query process, the packet should be broadcast. FIG. 6 shows a specific embodiment of the hardware block diagram of the present invention. The Ethernet switch mainly includes a media access control (MAC) chip 600 and a physical layer control. (phySicai iayerc0ntr〇1, referred to as ρΗγ ^ chip 68 °, preferably, the media access control chip 600 is coupled to the physical layer control chip 58 through a reduced medium independent interface (RMII). Media The access control chip 600 includes port control (port contr oi) units 61 to 617 (taking the aforementioned eight-port Ethernet switch as an example, corresponding to ports 0 to 7 respectively), and forwarding control (f. rwarding control) unit 620, queue contr0i unit 63, buffer control unit 650, and buffer memory 660, port control unit 61, coupled to transfer control unit 620, queue control unit 630, and The buffer control unit 65, the buffer control unit 65, is lightly connected to the buffer memory 660. An address lookup table is planned in the buffer memory 660, and the transfer control unit 620 is implemented in hardware to store a plurality of mac addresses. Relevant information is CAM 622. The physical layer control chip 680 is responsible for transmitting and receiving external physical electrical signals of the Ethernet switch, and the process method disclosed in the present invention and the media access control chip 600 internal transfer control unit 620 The operation design is related. For example, the packet data received by port 0 of the Ethernet switch reaches the port control unit 610 through the physical layer control chip 680 first. The DMAC address of the packet is checked by the table of the present invention. Method (k) 0k_up table) generates the corresponding port mask, and the SMAC address of the packet learns the higher SMAC address into the limited lookup table 662 or CAM622 by the learning method of the present invention, and The buffer control unit 650 allocates an appropriate buffer size in the buffer memory 660 for temporary storage of the packet data, and then the queue control unit 63 establishes a queue connection according to the port mask, and the queue control unit 630 The status of each port's buffer memory 660 can be determined according to the output queue length of each port, and a signal is sent to the connection control unit 61 to properly perform congestion control (congestion co ntrol). According to the disclosure of the present invention, the dual-slot lookup table 662 can distinguish the dual-slot architecture of each bucket into a designated slot and an accompanying slot by using each MAC address, and use the fortieth bit and the static flag to perform the MAC bit. The static and non-static learning of the address saves the actual space of the lookup table 662. On the other hand, the address query phase 12 1235306 can also increase the query performance. With the CAM 622, the forwarding control unit 620 can simultaneously analyze multiple MAC addresses. Perform a hardware comparison. After a clock, you can know whether you hit CAM622. The lookup table 662 uses the DMAC address to read back the designated slot and the companion slot at the same time, and selectively restore the content of the companion slot. Whether to hit the specified slot or the companion slot and report the relevant result. The embodiment of FIG. 6 can be implemented in different degrees according to the progress of the process. For example, the buffer memory 660 can be integrated into the media access control chip 600 or an external chip, and can be static according to different access speeds. Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), or DDR Dynamic Random Access Memory, etc. The physical layer control chip 680 is due to the special manufacturing process and needs to provide multiple port physical control. Is usually an external chip, but it may also be integrated into the media access control chip 600 as the integration level increases in the future. As described above, the present invention discloses a method for learning a media access control address (referred to as a MAC address for short), which includes the following steps: a hash value is calculated from the body access control address by a hash function, and according to the hash Value maps the designated slot one-to-one, and maps to the designated slot and accompanying slot of the address table according to the MAC address; if the designated slot is empty, the MAC address is learned to the designated slot; and if the designated slot is not The empty, companion slot is empty, and the content of the designated slot is non-static, then the content of the designated slot is moved to the companion slot, and the fortieth bit of the higher MAC address in the companion slot content is modified. Then learn the MAC address into the specified slot. Furthermore, if the specified slot system is not empty and the accompanying slot system is not empty, the MAC address is learned into the CAM; and if the specified slot system is not empty and the accompanying slot system is empty, the MAC address is modified. The fortieth bit of the upper MAC address, and the modified mac address is learned into the companion slot in response to the non-static learning command. Therefore, the learning advantages of the dual-slot address table can be used. Save the hardware gates of the address table. For example, the address table has a total of 2X access slots, and each access slot can be used to access the (48_X) bits of the MAC address and related information, and the MAC address is 48 bits, of which X It is a positive integer, and the related information preferably includes a port mask, a timeout counter, and a static flag. The present invention also discloses a method for querying a MAC address, which includes the following steps: Mapping a MAC address to a designated slot and a companion slot of an address table according to 13 1235306; reading out the first content of the designated slot and the second content of the companion slot Selectively restore the second content; compare the MAC address with the first content and compare the MAC address with the restored second content; and generate a query result based on the comparison results, such as a port mask, for example In other words, the selective restoring step is to selectively restore the second content according to the static flag of the second content and the fortieth bit of the upper MAC address. The invention further discloses a media access control chip, comprising: a buffer memory having an address table for temporarily storing packets; a plurality of port control units for coupling to a physical layer control chip; and a content addressable memory (Referred to as CAM) a transfer control unit coupled to the port control unit; a queue control unit connected to the transfer control unit and the port control unit; and used to couple the buffer memory, the queue control unit and the Buffer control unit of some port control units; among them, the transfer control unit is mapped to the designated slot and the companion slot of the address table according to the MAC address, and if the designated slot is empty, the MAC address is learned to the instruction slot, And if the designated slot is non-empty, the accompanying slot is empty, and the content of the designated slot is non-static, the content of the designated slot is moved to the companion slot, and the higher MAC address in the companion slot is modified. The fortieth bit, and then learn the mac address into the specified slot. The descriptions and drawings of the specific embodiments disclosed above are for the convenience of clarifying the technical content and technical means of the present invention, and are not intended to limit the scope of the present invention. All modifications, changes, or equivalent substitutions or replacements of the structural details of the present invention without departing from the spirit and scope of the present invention will be defined by the scope of the following patent applications. [Brief description of the formula] Figure 1 shows the structure of an Ethernet packet; Figure 2 shows a schematic diagram of a double-slot address table; Figure 3 shows a MAC address learning flowchart according to one of the embodiments of the present invention; Figure 4 shows a storage tank structure according to one embodiment of the present invention; Figure 5 shows a MAC address query flowchart according to one embodiment of the present invention; and Figure 6 shows a hardware block diagram according to the present invention. A specific embodiment. 1235306 110 Destination address 130 Payload 200 Address table [Simple description of component symbols] 100 Ethernet packet 120 Source address 140 Cyclic redundancy check code 210, 220, 250 Access buckets 210A, 210B, 220A, 220B, 250A, 250B access slot 300 start 312 hits? 310 Query MAC address 314 Update related information of the MAC address 320 The specified slot of Hash [ll: 0] is empty? 322 execute write command φ 330 Hash [ll: 0] companion slot is empty? 332 Are there vacancies or non-static items in the CAM? 334 Write learning content to CAM 336 Discard learning content 340 The content of the specified slot of Hash [ll: 0] is non-static?瀹 342 moves the content of the designated slot to the companion slot, and modifies the fortieth bit to i 344 writes the learning content to the designated slot · 350 static learning? 360 writes the learning content to the companion slot, and modifies the fortieth bit to 1 370. End Lu 410 Higher MAC address 420 Port mask 430 Timeout counter 440 Static flag 500 Start 510 CRCOK? 515 Drop packet 520 hits CAM? 525 returns port mask 530 returns port mask 540 reads the designated slot of Hash [ll: 〇] and the associated companion slot at the same time 550 DMAC hits the designated slot? 560 related companion slot content is static? 15 The fortieth bit of the content of the companion slot is 1? The content of the companion slot after hitting the restoration? End Media Access Control Chip 610 ~ 617 Port Control Unit Transfer Control Unit 622 CAM Line Control Unit 650 Buffer Control Unit Buffer Memory Real Layer Control Chip 662 Address Table 16