TWI234755B - Current steering circuit for amplifier - Google Patents

Abstract

The present invention provides improved techniques for controlling current flow in an output stage of a full range analog amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a full range of voltage output to drive an LCD display without necessitating a full range amplifier configuration. Further, many specific embodiments can be realized in smaller space on an IC chip than in conventional technologies.

Description

1234755 Case No. 91112771 Rev. V. Description of the Invention (1) Field of the Invention The present invention relates to an amplifying circuit, and in particular to a method for controlling errors in an analog output of a row driver (c ο 1 umndriver). technology. Description of Related Technology Liquid crystal displays (Liquid Crystal Display, LCD for short) have become popular and well known to the public. They are commonly used in flat-panel displays such as laptops, car navigation displays, and personal computers. In each of these applications, a row driver is used to enable the operation of each liquid crystal display unit. L C D includes a plurality of individual picture elements called pixels (p i X e 1), which can be individually addressed by the arrangement of columns and rows, and the row driving circuit provides the driving voltage to the rows of L C D. In a typical application, a 13.3-inch XGA liquid crystal display includes 10 2 rows of 3 colors, a total of 3 07 2 independent rows. These rows are typically arranged by 8 3 8 4 driver chips. To drive. The physical-based liquid crystal display technology needs to exchange the polarity of the driving voltage. That is, if one of the displays is driven by +5 volts during a specific period, the same line is driven by -5 volts in the next time interval. The peak-to-peak voltage is 10 volts, but the individual driving voltages of each cycle are 0 volts. Failure to drive the LCD in this way will cause the display to degrade until it is no longer available. The line driving circuit element serves as a medium between the electronic digital format for information processing and the analog format for displaying the results to the user. Therefore, the line driving circuit includes a digital-to-analog converter element for integrating the processing unit, the bus, and the memory. The digital signals are converted into analog signals. However, this analog signal must be able to drive L C D, although some are converted by digital to analog

9180twf3.ptc Page 6 1234755 Case No. 911127Ή Revised Year 5. Description of the Invention (2) The arrangement of the device directly driving the LCD display line, but another technology is to insert an amplifier between the converter and the display to improve the driving characteristics of the display . While some of the advantages of the conventional approach can be understood, there are opportunities for further improvement. For example, many conventional amplifier design methods introduce errors in the output signal of the amplifier, which do not necessarily cover most of the circuit operation, but the error characteristics will vary in different amplifier operation intervals. The amplifier is ideally combined as a buffer or boost signal and provides a highly accurate output signal. However, in the practical application of the amplifier, there are various restrictions that cause the output to deviate from the expected value. These limits include output errors such as dc offset (fixed errors relative to the desired output value) and gain errors (errors proportional to the output level). It is known to design a full-range input amplifier, which means that it can be used in multiple amplifier regions, including an over-differential region operating in the turn-in operating voltage domain. For example, when it is lower than half of the operating range, an amplifier with a differential input uses a PMOS input differential amplifier to receive the input signal. Among them, the NMOS input differential amplifier cannot operate, and it is more than half of the operating range. Under high conditions, the NMOS input differential amplifier is used to receive the input signal, and the PMOS input differential amplifier is not very effective. The additional components from NMOS and PM0S input differential amplifiers used to control switching have traditionally operated in the middle supply area. When such a device is allowed for full range operation, additional output errors will result due to the switching of the range of the amplifier. If the NMOS and PMOS amplifiers have only a fixed offset error of Vosp and Vosn, respectively, the combined full-range input amplifier will have Vosp's offset at a position lower than half of the range, and Vosn's at the south of the range. Offset and (Vosn- Vosp) / AV additional gain, where ΔΥ is tangent

9180twf3.ptc Page 7 1234755 _ Case No. 91112771_ year month day _M._ V. Description of the invention (3) The part that exceeds the input voltage range caused by the replacement. Therefore, the output error varies differently when the full-range amplifier operates between different ranges. In flat panel display applications using amplifiers, amplifiers are used to buffer the inputs of digital-to-analog converters that drive the rows or columns of flat-panel displays, because when voltages with errors switch, viewers can perceive changes in the image, and these errors can Unfortunately it affects the quality of the image. The color saturation and color of the image on the flat panel display are controlled by the voltage levels that are sequentially supplied to the display. When the amplifier is used to buffer the analog voltage supplied to the flat panel display, the output error of the amplifier will affect the accuracy of the voltage, and then affect the image on the display. The change in peak and peak drive voltage between different lines on a flat panel display will make the viewer aware, especially the small peak and peak swings. The peak-to-peak voltage is not affected by the amplifier's fixed errors, such as dc offset, but directly by, for example, the full range amplifier switching. Many conventional full-range amplifier topologies switch between different operating intervals near the intermediate supply level, where the output signal will increase gain errors (and peak-to-peak output errors) due to large swings in the output signal. It is common, for example, in the case of flat-panel displays, how to reduce switching gain errors that exceed the maximum operating range of the amplifier when switching between full-range amplifiers near positive and negative supply rails. However, it is known that full-range amplifiers that provide switching levels in the near middle are often limited to switching elements that switch between multiple amplifier ranges. A well-known method for a full-range amplifier to switch between multiple ranges is to switch the bias current between different ranges. Summary of the invention

9180twf3.ptc Page 8 1234755 _Case No. 91112771_ Rev. _ V. Description of the Invention (4) The present invention provides an improvement technique for controlling a current flowing in an amplifier circuit. These techniques, for example, can switch the bias current of the full-range amplifier to a positive or negative supply level in most amplifier operating ranges to reduce gain errors. The present invention further provides an improved technology for controlling the current flow in the output stage of a full-range analog amplifier circuit. In a specific embodiment, an analog output of a guided digital analog converter is provided to drive an LCD display. The embodiment can provide a full-range voltage output to drive an LCD display without the need for a full-range amplifier. Furthermore, many specific embodiments show that the IC chip space is smaller than that of the conventional technology. In a typical specific embodiment, the present invention provides a current steering circuit. The current steering circuit includes: a current input node is coupled to a first circuit path, and the first circuit path is in a first operation; In the mode, the self-current input node does not draw current; a comparator handle is connected to the current input node. When the comparator is in the first operation mode, the self-current input node does not take a very small amount of current. The current input node draws a large amount of current in order to transfer current from the first circuit path; a current mirror (currentmirror) connects the comparator, and when the current mirror is in the second operation mode, the current flow is maintained through a second circuit path, and It is not maintained during the first operation mode. In a specific embodiment, the current steering circuit of the first patent application scope further includes: a reference node coupled to the comparator, this reference node provides a reference voltage; a voltage input node may also be coupled to the comparator, this voltage input The node provides an input voltage. When the input voltage is a predetermined level related to the reference voltage, the comparator causes the current steering circuit to operate in the first operation mode or the second

9180twf3.ptc Page 9 1234755 _ Case No. 91112771_ Year Month Revision _ 5. Description of the invention (5) Operation mode. A specific embodiment of the current steering circuit further includes a P-type differential amplifier coupled to the first circuit path, and an N-type differential amplifier coupled to the second circuit path. In a specific embodiment, the current steering circuit further includes a current source, which is lightly connected to the current input node. The reference voltage is, for example, established by a transistor connected as a diode. In a specific embodiment, the voltage input node may include an input terminal of a P-type differential amplifier. In a more typical specific embodiment, the present invention provides a current steering circuit. The current steering circuit includes: a current input node is coupled to a first circuit path, and the first circuit path is Input node > and take current, a first transistor connected to the current input node 'When this first transistor is in the first operation mode, it can draw a negligible current from the current input node, and in the second operation mode, Current is drawn from the current input node to transfer current from the first circuit path; a second transistor is used to receive the current drawn by the current input node when the first transistor is in the second operation mode, and the second transistor is coupled to the coupling A third transistor connected to the second circuit path forms a current mirror. The current steering circuit also includes a reference node that provides a reference voltage to the fourth transistor, and a fifth transistor that forms a current mirror with the fourth transistor. The fifth transistor provides a reference current to the first transistor. The quantity is related to the reference voltage. The current steering circuit operates in the first operation mode or the second operation mode according to the voltage level of the voltage input node related to the reference voltage. In a specific embodiment, when the voltage level of the voltage input node is lower than the reference voltage, the current steering circuit operates in the first operation mode; and when the voltage

9180twf3.ptc Page 10 1234755 _Case No. 91112771_ Year Month Modification_ V. Description of the Invention (6) When the voltage level of the input node is higher than the reference voltage, it operates in the second operation mode. In a specific embodiment, when the voltage level of the voltage input node is higher than the reference voltage, the current steering circuit operates in the first operation mode; and when the voltage level of the voltage input node is lower than the reference voltage, the current steering circuit operates in the first operation mode. Two operating modes. In a specific embodiment, the first, second, third, fourth and fifth transistors are MOS transistors. In another more typical specific embodiment, the present invention provides a method for maintaining a substantially fixed error of an output voltage provided by a first circuit and a second circuit. According to an embodiment, the first and second circuits may be P-channel amplifiers and N-channel amplifiers, respectively, or N-channel amplifiers and P-channel amplifiers, respectively. This method includes driving the output voltage in the first operation interval of each of the first circuit and the second circuit. It is also a part of this method that the detection of the input voltage V i η reaches the reference voltage Vref. Switching from the first operation interval to the second operation interval of the second circuit is also part of the method. The reference voltage V r e f can be made large enough to provide a substantially fixed error within the output voltage range. Many advantages can be achieved by the present invention plus conventional techniques. Embodiments can provide a substantially fixed error term with a relatively large operating range of voltage output to drive the LCD display. In a specific embodiment, the non-fixed error range is limited to a portion of the display operating area that is not particularly sensitive to the human eye. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: A brief description of the drawing numbers: & 1 0 0, 2 0 0 current steering circuit

9180twf3.ptc Page 11 1234755 _ Case No. 91112771_ Year, month, and day five. Description of the invention (7) M4, M5, M6, M8, M10, M12, M13 ^ Ml 5, M19, M25, M28, M29, M30, M32, M46, M47, M48, M52, M53, M56, M5 7, M58, M59, M66, M6 7, M72, M80, M81, M82, M83, M 8 8, M89, M91, M98, M99, M101- M106, M118, 201-206, 218 MOS transistor 107, 108, 207, 208 Circuit 1 0 9, 1 1 0, 2 0 9, 2 1 0 Current source 1 1 2, 1 1 3, 1 2 1 2 1 2, 2 1 3, 2 2 1 Node 1 1 9, 2 1 9 Comparator 302, 304, 306 Method Step Examples The present invention provides an improvement technology for controlling the current flow in the output stage of a full-range analog amplifier circuit. The embodiment provides an analog output of a guided digital-to-analog converter to drive the LCD display. The embodiment can provide a full-range voltage input b to drive the LCD display without the need for a full-range amplifier. The Wang range differential amplifier is an output that can provide full-range operation V〇UJ ′, that is, 0 < = V〇Ut < = VDDA. In contrast, the operating range of the output voltage v0ut that can be provided by the non-full-range amplification f, with N channel '/ t two voltages as the threshold voltage (threshold Vol.) VT to the power supply voltage, t range ,, In other words, VT < = V0Ut < = VDDA, or the range between P channel rack, σ ,, 〇 and the power supply voltage VDDA minus the threshold voltage ντ, and 7, 0 < = V〇ut < = VDDA- VT. The full-range amplifier uses a coupling structure such as a power BS body, such as a p-channel. The architecture is like the first of an N-channel non-full-range amplifier! Architecture

1234755

In this field effect transistor system, the reference voltage Vref is used to make a difference. When the voltage V 1 η begins to exceed v r e f, the current flows from the first & so s input to the first-stage amplifier circuit of the first-stage Mu Fou Xi I f and the first-stage amplifier circuit of the wooden structure. This provides a private full-range amplifier, the first interval, one of the two circuits, two, two, and # for the interval (that is, there is a current flowing to it), and the second interval is between two and two, which is this example. N channels, all of which are in motion. /, Τ? Communication and N-channel circuits such as N-channel non-full-range amplifiers coupled to p-channels are shown in Figure 1. It shows one of the two (M0S) transistor M101_m106 according to the present invention. As one skilled in the art will know, The present invention is not limited to the number of transistors used and the type of power consumption described as circuit "A", circuit 107 and description as circuit, and B " For example, circuit H7 may be the temple of a full-range amplifier. The circuit circuit 108 of the model / larger can be a corresponding N-type amplifier. The i-th diagram also describes the non-essential components of the steering circuit 100-current sources 109 and 1 10. In the first In the operation mode, the steering circuit 1 0 〇 does not draw a large amount of current from the node 丨 2, that is, in the first operation mode, the current I 1 1 5 is approximately equal to the amount of current provided by the current source 10 9, and The current I 1 1 4 can be ignored (that is, very small). Therefore, the current (current I 1 1 6) flowing through the transistor M 1 0 3 in series with the transistor M 1 0 1 can also be ignored because the transistor M 1 0 3 forms a current mirror with the transistor M 1 1 8. As a result, the current flowing through M 1 1 8 (I 1 1 7) It can also be ignored. Therefore, relatively speaking, in the first operation mode of the steering circuit 100, a current flows through the circuit 107, but not through the circuit 108.

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V. Description of the invention (9) Φ ,, * In the 式 々 乍 乍 乍, the 'Guide Bow 丨 Circuit 1 〇 00 draws a lot from node 1 1 2 φ = Feng] (i 彳 /, in the second operation mode , The current 1 1 1 4 is approximately equal to the amount of A current 'and the current 1115 can be ignored. As a result, the flow 1 ϊ; ΐ ·; ΛΛ current and the mirror current flowing through the transistor ° 18 are also approximately dedicated to electricity = original 1 09 k supply The amount of current. So the circuit 107. Equation-current ▲ through the circuit m without flowing through "v Example: ―Guide 1 circuit 100 is called V 1 yq Μ Α 二 二 1 on the first 113 Switch between the first and second operation modes. When 6 Φ is approaching the limit level, the VGS of the transistor MI 0 1 (gate and y see wide τ) makes the electric solar body M01 01 conductive and flows the electric current 2, the circuit 100 is the first operation mode, and current will flow through circuit 107 without passing through circuit 108. The opposite case is when ^ 〇 & 113 is higher than the guidance threshold (1: 11 ^ 3) 1〇; ^) voltage At this time, the transistor 乂 101 (¥ 3; 3 will be 2T high, the voltage at which the body M1 01 turns on, so that the pilot circuit operates in the first mode of operation, and the current will flow through the circuit. 〇8 without flowing through circuit 1 7. 1 Suppressor M1 〇1, M1 〇2, M1 05 and M1 06 actually form a comparison together, the device is the comparator in the first figure 丨 丨 9, the comparator 丨 丨9 Compare the voltage at node m called V η ode 1 2 1π with the voltage at node 1 丨 3 (vn 〇de 1 丨 3) and use this to guide the steering circuit 丨 〇〇 Switch between the two operating modes. That is, when Vnodel 13 is smaller than Vnodel21, the VGS of transistor M 101 will be lower than the voltage that allows the current to flow, so that the guiding circuit operates in the first operating mode; otherwise When Vnodell3 is greater than Vn〇del21 ', then the v GS of transistor M 1 〇1 will be sufficient to allow current to flow, so that the pilot circuit 100 operates in the second operation mode. As is known, the pilot circuit 丨 〇〇 切

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Page 14 1234755 _ Case No. 91112771_ year month day __ Five 'invention description (10) The level and polarity of V η 〇de 1 1 3 where the operation mode is changed depends on its particular application, for example, appropriate changes In its routine design, when V η ode 1 1 3 is greater than Vnodel 21, the steering circuit 100 can also operate in the first operation mode. In this particular embodiment, V η 〇de 1 2 1 is obtained by using a current source 1 1 0 to provide a current flowing through a transistor M10 that is connected to a diode (di 〇de-c ο η nected), and the result is The drain voltage of transistor M 104, that is, Vnodel 21, will also appear at the gate of another transistor M 105 which is connected to a diode, so Vnodel 21 sets the gate voltage of transistor M 105 and controls The amount of current (current I 1 2 2) flowing through the transistor M 105. The transistor M 1 0 2 which forms a current mirror with the transistor M 1 0 6, and the current flowing therethrough is also approximately equal to the current I 1 2 2. The mirror M 1 0 6 is mirrored to the transistor M 1 0 2. The current will establish a voltage level between the source of the transistor μ 100 and the source of the transistor M 102, thereby affecting the amount of voltage required to turn on the transistors M101 and M102 on the node 131. FIG. 2 is a typical current steering circuit according to another embodiment of the present invention. In this specific embodiment, the steering circuit 2 0 0 includes transistors 2 0 1-2 0 6, which may be metal-oxygen half (M 0 S) transistor or the like. As known to those skilled in the art, the current steering circuit of the present invention does not limit the number and types of transistors used. The steering circuit 2 0 0 is coupled to the circuit 207 surrounded by a dashed line in Figure 2 and Figure 2 The circuit 208 is also surrounded by a dotted line. In a specific embodiment, the circuits 207 and 208 are p-type full-range amplifiers and corresponding N-type full-range amplifiers, respectively. However, the circuits 207 and 208 are not limited to any particular type of circuit, and Figure 2 also depicts the non-essential components of the steering circuit 2000. The current sources 209 and 2 1 ° are operated in the first operation. In the mode, the steering circuit 2000 does not draw a large amount of current from the node 212, that is, in the first operation mode, the current 2 5 is large.

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1234755 _ case number 91112771_ year month day _ correction _____ V. Description of the invention (11) is approximately equal to the amount of current provided by the current source 209, and the current 214 can be ignored (that is, very small). Therefore, the current (current 2 1 6) flowing through the transistor 2 03 in series with the transistor 2 01 can also be ignored, because the transistor 2 0 3 and the transistor 2 1 8 form a current mirror, and the result flows through 2 1 The current of 8 (2 1 7) can also be ignored. Therefore, relatively speaking, in the first operation mode of the steering circuit 2000, the current flows through the circuit 207, but not through the circuit 208. In the second operation mode, the steering circuit 2000 draws a large amount of current from the node 21 2. In other words, in the second operation mode, the current 2 1 4 is approximately equal to the amount of current provided by the current source 209, and the current The currents through the transistors M 1 1 and M 1 0 of the p-channel differential amplifier 207 are negligible. As a result, the current flowing through the transistor 203 and the mirror current flowing through the transistor 2 1 8 are also approximately equal to the amount of current provided by the current source 209. In contrast, in the second operating mode of the steering circuit 2000, current flows through the circuit 208, but not through the circuit 207. In this particular embodiment, the steering circuit 2000 is switched between the first and second operation modes according to the voltage called n Vnode2 13 "on the node 2 13. When V η ode 2 13 is lower than the voltage When approaching the limit level, the VGS (voltage between the gate and source) of the transistor 201 is lower than the voltage that can cause the transistor 201 to turn on and flow current. In this case, the guiding circuit 2 0 0 is In the first operation mode, the current will flow through the circuit 207 instead of the circuit 208. On the contrary, when Vnode213 is higher than the threshold threshold voltage, the VGS of the transistor 201 will be higher than the voltage that can turn on the transistor 201. , So that the steering circuit 2000 operates in the second operation mode, and the current will flow through the circuit 208 but not through the circuit 207. The transistors 201, 202, 205, and 206 actually form a comparator, that is, Comparator 2 1 9 in Figure 2 compares the reference voltage Vref called nVnode221ff on node 2 2 1 with the input voltage on node 213

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9180twf3.ptc Page 17 1234755 Case No. 91112771 V. Explanation of the invention (13) The first correction f 3 is not obvious-the output voltage provided by the specific real circuit and the second circuit of the present invention includes the first type program flow chart The first and second circuits have a fixed channel error of a typical channel amplifier and an N channel amplifier, or 1 can be a P channel amplifier, respectively. Figure 3 illustrates driving the output voltage 3 0 2 in each of the first emperor channel amplifier and the P-pass operating section; extracting the case of $ = two = the first voltage Vref of the circuit 3 0 4, and then resulting from each—two ^ ln reaches the first operation interval of the reference path and switches to the second operation region Y = and the second electric voltage Vref is sufficiently large to provide a substantially fixed °° to make the reference within. An additional feature of the circuit in the output voltage range is shown below. The circuit 208 is a -η pass input differential amplifier, which receives a differential input signal "disk VIPL" and outputs signals V0PL and v〇NL. Transistors M72 and M67 channel differential pairs, and receive differential The dynamic input signals v INL and v 丨 p [. Transistors M8 2 and M83 are used as series elements to control the transistor ㈣? And elbow ^ = no source voltage. Transistors M5, M25 and M30 form a current mirror The drain current of the transistor M67 is mapped to the output signal V0NL. The transistors M1 5, M28 and M 2 9 form a current mirror to map the drain current of the transistor μ 7 2 to the output signal VOPL. This n-channel difference The output terminal of the motor amplifier 208 is the current difference between the output flowing into the differential output terminals VONL and VOPL. The transistors M46, M99, M48 and M47 are the bias circuits of the transistors M82 and M83. The transistors M66, M91 and 218 It forms a current source that supplies bias current 2 17 to differential amplifier 208. Circuit 207 is a P-channel input differential amplifier that receives input signals VINL and VIPL and output signals VOPL and VONL. Transistor Ml 1 With M10 shape

9180twf3.ptc Page 18 1234755 ____ Case No. 91112771_ Year Month Day Amendment __ V. Description of the Invention (14) '^ Form a differential input pair of P channel and receive differential input signals VINL and VI PL respectively. The transistors M52 and M53 are used as series elements to control the drain-source voltages of the transistors M10 and M11, respectively. The output terminal of this ρ channel input differential pair is the current difference between the output flowing into the differential output terminals VONL and VOPL. Transistors M84, M89, M81 and M88 are bias circuits for transistors M52 and M53 = + Crystals M 2 0 9 and M19 form a current source that supplies a bias current of 215 to a differential amplifier pair of 20 /. The transistors M8, M58, M59 and M6 form a load circuit for differential amplifier pair 207 and η channel differential amplifier 208. The difference in current output from the p-channel differential pair 207 and the η-channel differential amplifier 208 is summed at the V0NL ^ V Ο P L differential output terminal and converted into a -difference 'voltage by the load circuit. VOPL and VONL are the differential output voltages of the combined p-channel differential pair 207 and the n-channel differential amplifier 208. Figure 2 includes another supporting circuit. For example, a torsion-strengthening circuit formed by the transistors μ 1, 2, M13, M32, M4, M56, and M57. The alternative circuit is described in the unpublished U.S. Patent Application No. 10/10063, which means that it is assigned to the same assignee as the present invention. M 98 is a series electric crystal, which is connected in series to the current source 210. Figure 2 depicts four bias voltages, ν Β 1 l, VB1H, VSON, and VSOP. VB1L is the bias voltage for the p-channel current source transistors M 1 3, 209 and M 4 6. V Β 1 Η is a bias voltage for n-channel current source transistors M88, 210 and M91. VSOP is a bias voltage for the p-channel tandem transistors M19, M29, M47, M30 and M80. VSON is a bias voltage for the n-channel series transistors M4, M84, M66 and M98. As described above, in the embodiment of FIG. 2, it includes a current steering circuit that guides the bias current flowing through the n-channel amplifier 208 and the p-channel amplifier 207. V η 〇de 2 2 1)

9180twf3.ptc Page 19 1234755 _Case No. 91112771_ Year Month Revision _ 5. Description of the invention (15) and input voltage Vin (or Vnode213). The two amplifiers 207 and 208 provide the same pair of differential output signals VOPL and VONL to the differential output nodes. However, the circuits 207 and 208 are not limited to any specific type of circuit. Similarly, the output signal circuits 207 and 208 are not limited to differential output signals. In a specific embodiment, the first operation interval includes an operation in which the N channel is relatively inactive while the P channel amplifier is active, and the second operation interval includes an operation in which the N channel is relatively inactive while the N channel amplifier is active. In another specific embodiment, the first operation interval includes operations where the N-channel amplifier is active and the P channel is relatively inactive, and the second operation interval includes operations where the P channel amplifier is active and the N channel is relatively inactive. FIG. 4 is a typical diagram of output voltage as a function of input voltage in a specific embodiment of the present invention. FIG. 4 illustrates a preferred embodiment of the present invention in which the input voltage Vi η over the entire operating range from 0 to VDDA is The function's output voltage Vout pattern, as shown in the typical graph of Figure 4, shows that the output voltage is substantially linear over the operating range of 0 to Vref. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

9180twf3.ptc Page 20 1234755 _Case No. 91112771_ Year Month Revision _ Brief Description of Drawings Figure 1 shows a schematic diagram of a typical current steering circuit in a specific embodiment of the invention; Figure 2 shows a book A schematic diagram of a typical current steering circuit in a specific embodiment of the invention; FIG. 3 is a flowchart showing a typical procedure for maintaining a substantially fixed error in output voltage in a specific embodiment of the invention; and FIG. 4 is a diagram showing a current invention Typical diagram of output voltage as a function of input voltage in a particular embodiment.

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Claims (1)

1234755 _ Case No. 91112771_ year month amendment _ six, patent application scope 1. A current steering circuit, comprising: a current input node coupled to a first circuit path, the first circuit path in a first operation mode Current is drawn from the current input node; a comparator is coupled to the current input node, and the comparator draws a very small amount of current from the current input node in the first operation mode, but the comparator is in a second In the operation mode, a large amount of current is drawn from the current input node to transfer current from the first circuit path; and a current mirror is coupled to the comparator, and the current mirror maintains a current flow through a second current mode during the second operation mode. The second circuit path is not maintained during the first operation mode. 2. The current steering circuit described in item 1 of the scope of patent application, further comprising: a reference node coupled to the comparator, the reference node providing a reference voltage; a voltage input node connected to the comparator, the The voltage input node provides an input voltage; and when the input voltage is a predetermined level related to the reference voltage, the comparator causes the current steering circuit to operate in the first operation mode or the second operation mode. 3. The current steering circuit described in item 1 of the scope of patent application, further comprising: a P-type differential amplifier coupled to the first circuit path; and an N-type differential amplifier coupled to the second circuit path . 4. The current steering circuit described in item 1 of the scope of patent application, more inclusive 9180twf3.ptc Page 22 1234755 Case No. 91112771_Year Month_Revision 6. The scope of the patent application includes a current source coupled to the current input 々 / τ, which is the point 0. Please refer to the electric power described in item 2 of the patent scope. The current reference voltage is established by a transistor connected as a diode. As described in item 2 of the patent scope, “Electricity; Suining L Guidance”, Where the voltage object j enters 々 / Γ, the point includes a P-type differential amplifier; i of it! Input terminal 0 7. A current steering circuit includes: a current m is connected to a first circuit path, and when the first circuit path is in a first operation mode, the current input node draws a current A transistor is coupled to the current input point, and the first transistor draws a negligible current from the current input point in the first operation mode and the current -V ΛΛ- input in a second operation mode. Immediately draw current in order to transfer the current in the second circuit path to a second transistor 5 to receive the first transistor in the second operation mode. The current drawn by the current into the node the second transistor A current mirror is formed with a second transistor that is connected to a second circuit path, and a reference Arhr point is provided to provide a reference voltage to a fourth transistor; a fifth transistor And the fourth transistor forms a current mirror, the fifth transistor provides a reference current to the first transistor, and the amount of the reference current is related to the reference voltage 9 and 5 of which the current steering circuit is related to the reference voltage _ A voltage input is the voltage level of the point, and is operated in the first-operating mode or the second operating mode. 0. The current steering circuit as described in item 7 of the patent scope, which should be used when When the voltage level of the voltage fm is lower than the reference voltage, the current is 5 9180twf3.ptc Page 23 1234755 _ Case No. 91112771_ year month day__ VI. Patent application guidance circuit operates in the first operation mode, and when the voltage level of the voltage input node is higher than the reference voltage, Operate in this second operation mode. 9. The current steering circuit according to item 7 of the scope of patent application, wherein when the voltage level of the voltage input node is higher than the reference voltage, the current steering circuit operates in the first operation mode, and when the When the voltage level of the voltage input node is lower than the reference voltage, it operates in the second operation mode. 10. The current steering circuit according to item 7 of the scope of patent application, wherein the first, second, third, fourth and fifth transistors are MOS transistors. 11. A method for maintaining a fixed fixed error in an output voltage, the output voltage comprising a first circuit and a second circuit, the method comprising: one of each of the first circuit and the second circuit Driving the output voltage in the first operation interval; detecting that the input voltage (V i η) reaches one of the reference voltages (V re 〇); and switching from the first operation interval of each of the first circuit and the second circuit to A second operation interval; wherein V ref can be set to provide a substantially fixed error within the output voltage range. 1 2. The method of maintaining the output voltage with a solid fixed error as described in item 11 of the patent application range, The first circuit is a P-channel amplifier, and the second circuit is an N-channel amplifier. 1 3. The method for maintaining a fixed fixed error in the output voltage as described in item 12 of the scope of patent application, wherein, 9180twf3.ptc Page 24 1234755 _ Case No. 91112771_ year month amendment _ 6. Patent application scope The first operating range includes the P-channel amplifier in operation, and the N-channel amplifier is relatively inactive operation; and the second The operation interval includes the operation of the N-channel amplifier while the P-channel amplifier is relatively inactive. 14. The method for maintaining a fixed fixed error in the output voltage as described in item 11 of the scope of the patent application, wherein the first circuit is an N-channel amplifier and the second circuit is a P-channel amplifier. 1 5. The method for maintaining a fixed fixed error in the output voltage as described in item 14 of the scope of the patent application, wherein the first operation interval includes the operation of the N-channel amplifier and the operation of the P-channel amplifier relatively inactive And the second operation interval includes an operation in which the P-channel amplifier is in operation, and the N-channel amplifier is relatively inactive. 1 6. The method for maintaining a fixed fixed error in the output voltage as described in item 11 of the scope of the patent application, wherein the Vref setting is sufficiently large compared to Vin to provide a substantially fixed error within the output voltage range. 1 7. The method for maintaining a fixed fixed error in the output voltage as described in item 11 of the scope of the patent application, wherein the Vref setting is sufficiently small compared to Vin to provide a substantially fixed error within the output voltage range. 18. —A device for maintaining a fixed fixed error in output voltage, comprising: a device for driving an output voltage in a first operation interval of each of a first circuit and a second circuit; detecting an input voltage (V i η) Reach a reference voltage (V ref) 9180twf3.ptc Page 25 1234755 9180twf3.ptc Page 26