TWI232524B - Simplified dual damascene process - Google Patents

Abstract

The present simplified dual damascene process includes: to form a first metal layer, an etch stopping layer and a dielectric layer sequentially on the semiconductor substrate having MOS devices; to form a via hole on the dielectric layer and then an organic layer by photolithographic etching technique; to form a trench in the dielectric layer by the organic layer so as to form a dual damascene structure composed of the via hole and the trench. The present invention simplifies the process as well as offer excellent dual damascene profile without increasing the dielectric constant K value of the dielectric layer (IMD) in between the metals.

Description

1232524 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a dual damascene process, particularly to a method that can omit the traditional complicated dielectric layer / etch stop layer / dielectric layer stacking step and reduce the habit. It is known that the dielectric constant of the intermetal dielectric layer is relatively high, and a dual damascene process that can simplify the process and obtain a good trench profile can be obtained. [Prior art]

With the increasing density of IC design circuits in semiconductor manufacturing processes and the increasing current per unit area of conductors, copper has lower resistance and higher resistance to electromigration, so traditional aluminum conductors The process is replaced by the copper wire process. When copper is used as a wire material, the copper halide vapor pressure is not high enough, which makes it difficult to engrav the copper wire with the existing etching technology. Therefore, the dual damascene process is generally used to complete the copper wire and plug at the same time. The process.

The main technical focus of the dual damascene process is the etching technology used to etch trenches for filling conductive metal. In the etching process before the dual damascene process, there are two known methods for making trenches with dual damascene structure. The first method As shown in the first figure, it is the first etching when the silicon nitride layer (S i N) is used as the etching trench 46 and the dielectric hole 44 of the lower dielectric layer 38 and the upper dielectric layer 42. A barrier layer (etchst ο pping 1 ayer) 4 0. In this method of using a nitride nitride layer as the first etch barrier layer 40, there is a dielectric constant (K value) of an intermetal dielectric (IMD) layer. The higher problem will make the capacitance of the dielectric layer higher, which will cause more interference (η 〇ise) in the dielectric layer, making the insulation effect of the dielectric layer relatively poor;

Page 5 1232524 V. Description of the invention (2) The manufacturing method is shown in the second figure. When the trenches 4 6 and the interlayer holes 4 4 are etched, no etch stop layer is used, but there are trenches 4 6 The shortcomings of both wheel profiling and depth are difficult to control, which makes it easy to cause process difficulties. Therefore, the present invention is directed to the above-mentioned problems, and proposes a dual damascene process that can simplify the manufacturing process, which can not only reduce the dielectric constant of the intermetal dielectric layer, but also reduce the time required for the dual damascene process and obtain a good trench profile. [Summary of the Invention] The main object of the present invention is to provide a dual damascene process which can simplify the manufacturing process, and the manufacturing process omits the complicated steps of the dielectric layer / etch stop layer / dielectric layer stacking in the traditional process. A secondary object of the present invention is to provide a dual damascene embedding process which can simplify the manufacturing process, and the structure produced by the method has a lower dielectric constant of the intermetal dielectric layer. Another object of the present invention is to provide a double-insertion process which can simplify the manufacturing process. The structure produced by the method has a good trench profile. Yet another object of the present invention is to provide a dual damascene process which can simplify the process, which can greatly reduce the time required for the process. Yet another object of the present invention is to provide a dual damascene process which can simplify the manufacturing process, and the structure produced by the process has relatively low dielectric layer capacitance. In order to achieve the above object, the present invention sequentially forms a first metal layer, a #resistance insulation layer, and a dielectric layer on a semiconductor substrate having a MOS device; a patterned first photoresist is formed on the dielectric layer. Layer to pattern first

1232524 V. Description of the invention (3)

The photoresist layer is a mask etching the dielectric layer to form a dielectric hole, and then the patterned first photoresist layer is removed; then an organic layer is formed on the dielectric layer and the dielectric hole is filled; A patterned second photoresist layer is formed thereon to define the trench size of the organic layer and the dielectric layer to be etched, and the trench size is larger than the via hole, and the patterned second photoresist layer is used as a mask. Using the high selectivity ratio of the organic layer to the dielectric layer, the exposed organic layer is over-etched until the organic layer is lower than the dielectric layer; the patterned second photoresist is used as a mask to interpose the dielectric layer. The electrical layer continues to be etched until the dielectric layer is lower than the organic layer; and the second photoresist layer and the remaining organic layer are removed to obtain a double damascene structure outline. In order to make your review members have a better understanding and understanding of the structural features and achieved effects of the present invention, I would like to refer to the preferred embodiment diagrams and detailed descriptions as follows: [Embodiment] The present invention is A dual damascene process that can simplify the process. It does not require the traditional process of complicated stacking of dielectric layers / etch stop layers / dielectric layers, and can relatively have a lower dielectric constant of the intermetal dielectric layer. Utilize the difference in etching selection between the dielectric layer and the organic layer to obtain a good trench structure.

Please refer to the third (a) to the third (h), which are cross-sectional views of the structure of each step of a preferred embodiment of the present invention. As shown in FIG. 3 (a), a first metal layer 12 of copper is deposited by chemical deposition on a semiconductor substrate 10 on which basic elements such as MOS have been formed, and an etching stopper layer 1 of silicon nitride is further deposited. 4 on the first metal layer 1 2

Page 7, 1232524 V. Description of the invention (4), and then a dielectric layer 16 is deposited on the etch stop layer 14 by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the dielectric The material of the layer 16 may be a silicon oxide compound or a fluorinated silicon glass (FSG). A photoresist layer is coated on the dielectric layer 16, and the photoresist layer is subjected to a development technique to form a patterned first photoresist layer 18. A patterned hole etching window has been formed on the patterned first photoresist layer 18. 20, using the via hole etching window 20 to define the size of the via hole 22 to be etched.

Next, the patterned first photoresist layer 18 is used as a mask to etch the dielectric layer 16 to form a via hole 22, and then the patterned first photoresist layer 18 is removed to form a third ( b) The structure shown in the figure. After the step of removing the patterned first photoresist layer 18 is completed, as shown in FIG. 3 (c), a layer of organic bottom anti-reflection (BARC) or an organic layer of other organic materials is spin-coated on the dielectric layer 16. 4, and the organic layer 24 completely covers and fills the dielectric layer 16 and the via 22 2. A patterned second photoresist layer 26 is formed on the organic layer 24, and the patterned second photoresist layer 26 has a trench etching window 28, and the trench etching window 28 is larger than the via etching window 2 0 to define the size of the trenches 30 to be etched by the organic layer 2 4 and the dielectric layer 16.

After the patterning of the second photoresist layer 26 is completed, the patterned second photoresist layer 26 is used as a mask, and a high selection ratio of the organic layer 24 to the dielectric layer 16 is used together with the dry etching technology to expose the The organic layer 24 is subjected to dry over-etching, as shown in FIG. 3 (d), until the surface of the organic layer 24 is slightly lower than the top surface of the dielectric layer 16 to form a trench structure. Preliminary outline 〇 After dry over-etching the organic layer 24, as shown in the third (e) diagram

Page 8, 1232524 V. Description of the invention (5), and then patterning the second photoresist layer 26 to continue the trench etching of the dielectric layer 16; this etching method uses the dielectric layer 16 to etch faster than the organic layer The etching rate is controlled by the etching rate of 24, when the etching depth reaches the top surface of the dielectric layer 16 is lower than the top surface of the organic layer 24. After the trench etching of the dielectric layer 16 is completed, the trench structure 30 can be obtained, and then the second patterned photoresist layer 26 and the remaining organic layer 24 are removed by ashing. Third (Fig. 0 shows the outline of the double mosaic structure composed of the trench 30 and the interstitial hole 22.

After the outline of the dual damascene structure is completed, a copper metal wire 32 process may be performed. As shown in the third (g) diagram, the exposed etching stopper layer 14 is removed first, and the semiconductor substrate 10 is cleaned. The atoms of the second metal layer 36 have a diffusion and penetration effect on the dielectric layer 16. A metal barrier layer 34 made of tantalum or a nitride group is deposited first, and then a second metal layer is deposited. 36 to form the structure shown in the figure. After the second metal layer 36 is deposited, the semiconductor substrate 10 is subjected to chemical mechanical polishing (CMP) to achieve so-called comprehensive flatness, so as to obtain a good metal wire 32, as shown in the third (h) diagram. .

In summary, the present invention is a dual damascene process that can simplify the manufacturing process. It does not require the traditional complicated and complicated stacking process, but uses a simpler spin coating method to form an organic layer, and uses the organic layer to intervene. The high selection ratio of the electrical layer is over-etched to form an organic layer filled in the via hole, so that when the trench is etched, the angle of the junction between the trench and the via hole can be protected and maintained, and a good dual damascene structure can be obtained. The invention is superior to the conventional stacking process in terms of process timeliness, and the present invention will have no

Page 9 1232524 V. Description of the invention (6) The lower the dielectric constant of the intermetal dielectric layer, which can improve the operation speed and function of the device; on the other hand, the invention The conventional manufacturing process can effectively control the contour and depth of the trench, so a better trench microload (trenchmicr 〇-1 〇ading) effect and bottom profile (bottom profile) can be obtained; therefore, the present invention does not increase the difficulty of the process, It greatly shortens the time required for the copper dual damascene process. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of implementation of the present invention. Therefore, all equivalent changes and modifications in accordance with the shape, structure, characteristics, and spirit described in the patent application scope of the present invention are provided. Shall be included in the scope of patent application of the present invention. [Comparison of drawing numbers] 10 Semiconductor substrate 12 First metal layer 1 4 Etching stop layer 1 6 Dielectric layer 1 8 Patterned first photoresist layer 2 0 Intermediate hole etching window 2 2 Intermediate hole 2 4 Organic layer 2 6 patterned second photoresist layer 2 8 trench etching window 3 0 trench 3 2 metal wire 3 4 metal barrier layer

Page 10 1232524 V. Description of the invention (7) 3 6 Second metal layer 3 8 Lower dielectric layer 4 0 First etch stop layer 4 2 Upper dielectric layer 4 4 Interlayer hole 4 6 Ditch 111 · Ι

Claims (1)

1232524 The six epsilon process S ο system M has a simple structure Γ can be mentioned for your attention. In the κκ step list, there is a sequence of inlays that includes the process system. The sequence is based on the base substrate. Half of the case plan should be, the layer 'electrical layer of the dielectric layer and the first layer of the resist layer engraved residual image. Layer, the electrical layer blocks the lithography ## curtain act as a layer, the blocking light shifts one after the first, and then the layering machine should have the Yuxuan = mouth; the hole sense layer is defined by the, The full layer is filled with resistance and light, and the second layer is organic. There is a plan to form an upper layer. The etching of the inch channel can be combined. The layer dielectric and the layer are connected with the layer. The plan of the second light-blocking plan should be in inches, and the ruler canal canopy should be exposed to the opposite side of the electricity, the surface should be selected from the high-level to high-level direct electricity, and the remaining layers should be etched. Machine shop To continue, the relay layer should be used as a dielectric layer, and the low surface of the screen should be a layer of resistive, optical, and dielectric materials. The figure should be etched with a channel inlay. The remaining layer blocks light. The second round of this round of removal and construction is a two-step process. The system is embedded with embedded silicon inlaid with silicon and doubled with oxygen. The second item is 1 second. The material is specially requested to apply for the application layer, such as Ru Rudian, which has the medium, 4 which has the medium, and the process inlay. It is advantageous for the layer to shoot the anti-1 anti-bottom machine for the special layer, so please apply for the layer as the first step. The above-mentioned embedded layer and electric double-layer dielectric are described in the integrated item Shen 1 type. The second side is coated with Fan Xuanli to apply for a layer application machine, such as page 13 1232524. 6. The scope of the patent application. 2 The photoresist layer and the organic layer. They are all removed by ashing. 6. The dual damascene process as described in item 1 of the patent application scope, wherein the etch stop layer is silicon nitride. 7 · The dual damascene process described in item 1 of the scope of patent application, wherein the over-etching of the organic layer is dry etching. 8. The dual damascene process according to item 1 of the scope of the patent application, wherein the dielectric layer is made by a physical vapor deposition method or a chemical vapor deposition method. 9 · The dual mosaic process as described in item 1 of the scope of patent application, in which After the double damascene structure outline, a metal wire process can be performed, which includes the following steps: removing the etch stop layer; cleaning the semiconductor substrate; depositing a second metal layer on the semiconductor substrate; and using chemical machinery A polishing process is performed on the second metal layer to obtain a good metal wire. 1 0. The dual damascene process according to item 9 of the scope of patent application, wherein the second metal layer is made of copper. 1 1 · The dual damascene process as described in item 9 of the scope of patent application, wherein a metal barrier layer may be deposited before depositing the second metal layer. 1 2 · The dual damascene process as described in item 11 of the scope of patent application, wherein the material of the metal barrier layer is tantalum or tantalum nitride. Page 14