TWI231979B - A semiconductor chips package with enhanced heat releasing character - Google Patents

Abstract

A package with semiconductor chips is provided. The package at least includes a substrate, a first semiconductor chip, a second semiconductor chip and a heat sink. The second semiconductor chip is thicker than the first semiconductor chip, and the first and second semiconductor chips electrically connect to a same face of the substrate. The heat sink having an opening. The heat sink is positioned on the first semiconductor chip and exposes the top surface of the second semiconductor chip through the opening. However, the height of the top surfaces of the second semiconductor chip and the heat sink are almost same.

Description

1231979

[Technical field to which the invention belongs] The present invention relates to a packaging structure of a semiconductor device with enhanced heat dissipation performance, and more particularly to a packaging structure of a flat semiconductor device with a high packaging density. [Previous technology] In the semiconductor industry, 'Integrated Circuits (1C) production is mainly divided into three stages: · Manufacturing of bare chips (die), production of integrated circuits (1C), and integrated circuits ( IC) package (package). The bare wafers are completed through wafer (Wafer) production, circuit design mask fabrication, and σ 彳 circle, and each of the bare wafers formed by wafer cutting is passed through a bare wafer. After the solder pad (B 〇η ^ soil ngpad) is electrically connected to the external signal, the bare chip is covered with a sealing material / the purpose of the package is to prevent the bare chip from being affected by moisture, heat and noise. And provide bare chips and external circuits, such as printed circuit boards (printed

Cucuit B0ard (PCB) or other medium for electrical connection between the substrates for packaging is thus completed the package step of the integrated circuit. In order to connect the bare chip and the substrate for packaging mentioned above, a flip technology (Fllp Chlp lnterconnect Technolgy) is usually used to form solder balls in an array of bare pads. After flipping the wafer, the wafer is used. The solder balls correspond to the contacts on the packaging substrate, so that the chip can be electrically connected to the packaging substrate through the solder balls, and then to the outside through the internal circuits and surface contacts of the packaging substrate.

V. Description of the invention (2) Signal electrical connection. Therefore, along with the accumulation of wafers, the structure of the acoustic package is also becoming more and more diversified. The use of the above = yin, plus, the package structure of the wafer has the advantages of reducing the chip packaging surface, the path of the bonding technology, etc. It is applied to the chip sealing and packaging of 1 number of chip size packages (Chip Scale Package, CSPJ, + members such as Ball Grid Array (BGA), and Multi-Chip Module Package (Multi-Chip Module) , MCM) and other types of packaging p: the scope of application of bonding technology. Among them, polycrystalline 'two: is flip-chip ^ 3¾ ^ ^ t (CSP) ^ ^ ^ ^ # ;;, M ^ ^ and electrical Connected with, to constitute-a half-two-f-plate package structure with different functions. The 7L pieces of beef conductors are equipped with dynamic random access memory (dynamic rand⑽aeeess 卩 'DRAM) and a central processor (cp = == Packaging structure can put multiple devices on three substrates, which not only improves the installation density and reduces the number of cases. 3 Γί Reduces the signal delay between the packaging modules, and achieves the output = 中 二 ί The purpose is therefore widely used in communication and portable electronics The figure shows the conventional method of using blank: installation, "see the schematic diagram. Please refer to the following: beautiful jealousy, = a + conductor 7" piece 11 and the second semiconductor element 112, of which the surface of the two inn has more than 10 A contact (not shown) is used as an output human medium for the internal circuit of the US board 100. In addition, the -semiconductor Λ is the base 1231979 V. Invention description (3) 110 and the second semiconductor element 丨 12 respectively It is disposed on the surface 102 ′ of the substrate 10 and the first semiconductor element 11 is, for example, a central processing unit (cpu), and is disposed on the substrate 100 using a flip chip package. On the central area of the surface 102 of the substrate 100, the first semiconductor element 110 is electrically connected to the substrate through the bumps 1 through the configuration of a plurality of bumps 111. The second semiconductor element 112 is, for example, a dynamic random access memory (DRAM) system that uses a wafer size structure. Therefore, the second semiconductor element 112 is thicker and is distributed on four corner areas of the substrate 100 and the surface 102. , The second piece 11 2 for example by the solder ball 1 0 6 The contact of the surface 10 of the substrate 100, and each semiconductor element f and the substrate are connected by a solder ball, and a filler material 108 (Under fill) is filled in the solder ball 106. Between them to fix the solder ball 106 and disperse their thermal stresses' to avoid the tensile stress between the semiconductor element and the substrate due to the difference in the Coefficient of Thermal Expansion (CTP) between the two, and As a result, the solder ball j 〇6 has a gap due to fatigue and affects the signal transmission performance between the semiconductor element and the substrate. Heat sinks 114 need to be provided above the first and second semiconductor elements 11 () and 112 to dissipate the heat generated by the first and second semiconductor elements 11 and 112 during operation. Since a wafer structured with a general wafer size has a thicker thickness', when the first semiconductor element 112 is structured with a wafer size, its thickness is relatively thick. In order for the heat sink 114 to effectively contact the first semiconductor element 110 and to effectively conduct the heat generated from the first semiconductor element 110, a dummy die must be stacked above the first semiconductor element 110.

1231979 V. Description of the invention (4) 116 to compensate for the difference in thickness between the first semiconductor element 110 and the second semiconductor element 112. Then, a layer of a thermal interface material (Thermal Interfacial) is applied on the second semiconductor element 112 and the blank wafer n6. Material) 11 8 'For example, heat sink, then install heat sink! i 4 on it. A layer of Thermal Interfacial Material 120 also needs to be coated between the blank wafer 116 and the first semiconductor element 110. The thermal interface material 120 may also be a thermally conductive adhesive. Finally, a heat radiating fin 122 is disposed on the heat radiating fin 114 to improve the heat dissipation effect. The heat radiating fin 122 extends to cover the back of the second semiconductor element 112. A layer of thermal interface material is also applied between the heat sink fin 4 and the heat sink 122. Fig. 2 is a schematic side view of another conventional solution for packaging a semiconductor device in a package structure with different chip heights. The difference between Figure 2 and Figure 2 is that the blank wafer is abandoned to compensate for the difference in thickness between the first semiconductor element 110 and the second semiconductor element 丨 2, and a heat sink 126 having a protrusion P 124 is used instead. On the periphery of the heat sink 126, there can be 21 丄 2V protrusions 124, which can effectively perform the heat conduction effect through the thermal interface material 1, 20: contacting the element 110. Similarly, there is no heat dissipation device 122 above the heat dissipation = 126 to enhance the thermal mechanism 122 system to extend the coverage of 篦 _ | 遒 # — # / ,,, and release the eighth month: wearing 12? Is the ancient second f On the back of the first + conductor element 112, there is a poison display. "There are gates of several Sanskate girls. ★ Ling-shaped pills ..." A layer of thermal interface material is also applied between the politic heat piece 126 and the heat sink 122. 11 8. = On the solution proposed in Fig. 1 or Fig. 2, the thickness of the package is the same as that of the county ^: Ding Zhuang said that the film is not her ... "The two are the same," that is, the packaging phase The total thickness D is the thickness of the base plate, the first-three-dimensional conductor, and the heat sink.

Page 9 1231979

The sum of the 'can't achieve light, thin, short sealing tools. In addition, the price of solving the multi-functional exhibition of Japanese and Japanese films is not the cost of the first semiconductor element's path to increase the heat dissipation of heat. _ .. ^ ,,. In addition, the heat sink 26 shown in Fig. 2 has the disadvantage of running down. First, the thickness of the scattered slabs is thick and thick, not Jiang Liang 4. Gu Yuewen ..., the monthly thickness of the seasonal sacral thickness makes the overall thickness of the sacrifice dry and does not pay, and the second is the convex extension of the heat sink 126. 0 / 1 The cavity formed by several millimeters, although it has the ability to accommodate and position the fourth = convex edge piece, the temperature gradually rises. Once the temperature exceeds its normal path, a calculation error will occur. The chip achieves lightly solved problems. The heat sink with the recesses is not made, so the cost is not increased. : Generally a, the wafer inside the first semiconductor element has a high frequency of calculations and a high speed of movement. Therefore, the heat generated is also large, but it needs a thicker heat transfer V f to dissipate heat. Of course, the effect of heat dissipation is not as good. It is better to attach the heat sink directly to the first semiconductor element. When the thermal energy is continuously accumulated, the crystal M 4 4 k — 丄 1 ^ ^ It is worth noting that when the wafer itself is in the temperature range, the internal electricity of the wafer may temporarily fail. Therefore, thin, short, and small objects become idiotic characters. [Summary of the Invention] In view of this, the object of the present invention is to propose a packaging and packaging structure with semiconductor elements, in which the semiconductor elements are arranged on the same surface of the substrate. , Used to reduce the thickness of the packaging structure to achieve light, thin, short, small. Another object of the present invention is to provide a semiconductor device package structure with enhanced heat dissipation performance. The semiconductor devices are arranged on the same surface of the substrate, and a notch is provided on the heat sink to avoid thick semiconductor devices and can be directly attached.

Page 10 1231979 V. Description of the invention (6) Attached to the thinner semiconductor components, so the package structure can reduce the thickness of the package and achieve the purpose of lightness, thinness, shortness and smallness. -& Another object of the present invention is to propose a semiconductor element packaging structure with enhanced heat dissipation performance. The semiconductor elements are arranged on the same surface of the substrate, and a notch is provided on the heat sink to avoid thicker semiconductor elements and be attached to On thinner semiconductor components, such a package structure can increase the heat dissipation efficiency of the chip and accelerate the cooling rate of the chip. θ 39 Another object of the present invention is to propose a semiconductor device package structure with enhanced heat dissipation performance. The semiconductor devices are arranged on the same surface of the substrate, and = on-chip? Place openings to avoid thicker semiconductor components: can be directly attached on top of the body components, so the packaging structure can reduce packaging = two, light, short, small, and can increase the thermal efficiency of the wafer. Month b, and speed up the cooling of the wafer. In order to achieve the above-mentioned object of the present invention, a kind of right car company hibiscus is proposed, and the main II ^ / 禋 has a package of cattle conductor components. The structure is mainly composed of a substrate, at least one of the first abundant twilight-μ, Λ f 筮-Dust _-w / conductor components, and at least abundant conductive * Sister semiconductor components and the second thousandth conductor 7G The pieces are placed on the upper surface of the substrate and the flute was thinner at one time and the -Fengtoya Kaidu AAr + conductor element is thick and flat, while the first bovine conductor element is thicker. Passing the chip, but the cracked ;; medium + conductor element can be: or more chip wafer size structure or =: said chip, the heat sink has an open D or missing σ ^ ^ for the position of the system of heat The second semiconductor element or the notch is arranged on the heat sink when the heat sink is installed at the position of the first semiconductor. Or notch can dissipate heat: = = duct == ^ 1000 conductors

Page 11 1231979 V. Description of the invention (?) The semiconductor element dissipates the thermal interface and attaches it directly and qualitatively, so that the second heat dissipation mechanism can be covered by ‘,,, =. In addition, the heat sink or its extension covers C attached to the heat sink. The heat dissipation mechanism can also be arranged on the back of the first + conductor element. The thickness of the heat sink provided is approximately equivalent to the thickness of the first semiconductor element and the semiconductor element. The upper surface of the wafer is substantially the same as the back surface of the second semiconductor element. The size of the opening or notch on the political heat sink is equal to or 2 in size 1. This heat sink can avoid the second semiconductor. In addition, the second semiconductor element can be radiated by a heat dissipating device or other heat dissipating mechanism attached to it. /. Since the heat sink avoids the position of the second semiconductor element, the thickness of the packaging structure of the entire semiconductor element can be thinner than the conventional packaging structure, and the purpose of lightening, thinning, short, and small on the package can be achieved, and the thickness can be increased. The cooling performance of the chip 'and accelerates the cooling rate of the chip. [Embodiment] In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes two preferred embodiments, which will be described in detail in conjunction with the accompanying drawings. '' Embodiment 1 Please refer to FIG. 3A and FIG. 3B at the same time, wherein FIG. 3A illustrates a preferred embodiment of the present invention in which a packaging structure with a semiconductor element is arranged on a substrate

Page 12 1231979 V. Description of the invention (8) The plan view is not intended. Figure 3β is a schematic cross-sectional view of the packaging structure of Figure M along line 2. The substrate 300 has a surface 302, and a plurality of contacts (not shown) on the surface q302 above the substrate qnn are used as the input / output medium of the inner circuit of the substrate ρ circuit. In this embodiment, the substrate paste The first surface 302 is provided with a first semiconductor element 31 and four second body 7L pieces 312. The first semiconductor element 31o may be a flip-chip package, such as a controller (Processor) or a processor (Processor), and is located on the central area of the substrate 300 above the substrate 300. The first semiconductor element 31o is electrically connected to the substrate 300 through the bump by the configuration of the plurality of bumps 311. In addition, the four second semiconductor elements 312 may be a wafer having a wafer size, such as a dynamic random access memory (DRAM), which is disposed on four corner regions of the upper surface 302 of the substrate 300. In general, the thickness of a package wafer with a wafer size of 8'2 'is larger than that of a flip-chip package wafer. In this embodiment, a cross-shaped heat sink 32o is disposed on the first semiconductor element 310, and the heat sink 320 has at least one peripheral notch 322. Preferably, the notch 322 is located at the heat sink. Tablet 320 on the four corners. The position of the notch 322 is designed according to the position of the second semiconductor element 312 on the substrate 300. The size of the notch 322 may be equal to or slightly larger than the size of the first semiconductor element 312, so the second semiconductor element 312 can be avoided. Referring to FIG. 3B, it shows the difference in locality between the first semiconductor element 31 and the first j semiconductor element 312. In this embodiment, the height difference between the two is about 0.5 mm to 1 mm. In addition, there is still a layer of thermally conductive adhesive coating 324 between the heat sink "ο and the first ^ conductor element 310. Please refer to Figure 3C, which shows the package structure of Figure 3A along β — 1231979 V. Description of the invention (9) is a schematic cross-sectional view. The heat sink 320 is disposed on the first semiconductor element 31 (), and the top surface 325 of the heat sink 320 away from the substrate 300 on the surface 300 and the second semiconductor The back surface 327 of the element 312 can be approximately the same height. In this way, the thickness of the entire semiconductor device package structure can be reduced to achieve the purpose of lightness, thinness, shortness, and smallness on the package. See FIG. 3D, FIG. 3D Then it is shown on the package structure in FIG. 3A. A cross-sectional view along the B-β 'line after the heat sink is installed. Because the top surface 325 of the heat sink 320 and the back surface 327 of the second semiconductor element 312 are about ^, Therefore, a heat sink 328 can be provided after the heat sink 320 and the back surface 327 of the second semiconductor element 312 are coated with a thermal conductive adhesive coating 326. The heat sink 328 is attached to the heat sink 320 and the second semiconductor element 31. 2 on the back, "and its department can help Heat sink 320 and the second semiconductor element 312 heat. The heat dissipation device 328 may also extend to cover the back surface of the second semiconductor element 312. Embodiment 2 Please refer to FIG. 4A and FIG. 4B at the same time, wherein FIG. 0 shows a schematic plan view of a packaging structure with a semiconductor element arranged on a substrate according to another preferred embodiment of the present invention. Figure 4A is a schematic cross-sectional view of the packaging structure along the cc line. The substrate 400 has a surface 402 and a plurality of contacts (not shown) on the upper surface 402 of the substrate 400. The input / output medium of the internal circuit of the gang is used as a substrate in this embodiment. The upper surface 402 is provided with a first semiconductor element 41, and two plates 40. The mmv first semiconductor element 41 ° may be a flip-chip package chip, such as a controller or a processor. 〇r), 1231979 V. Description of the Invention (ίο)

It is located on the central area of the upper surface 402 of the substrate 400, and the first semiconductor element 41o is electrically connected to the substrate 400 through the bumps by the arrangement of a plurality of bumps 411. In addition, the four second semiconductor elements 412 may be a wafer-size structured wafer, such as a dynamic random access memory (DRAM), which is distributed on four corner regions of the substrate 400 on the upper surface 402. Generally, the thickness of the wafer structured wafer is larger than the flip-chip packaged wafer. In this embodiment, a heat sink 420 having an opening 422 is disposed on the first semiconductor element 410. Preferably, the opening 422 is disposed at four corners of the heat sink 420 to make the heat sink 422 has a field-like shape. The position of the opening 422 can be designed according to the position of the second semiconductor element 412 on the substrate 40. The size of the opening 422 can be equal to or slightly larger than the size of the first semiconductor element 412, so the second semiconductor element can be avoided. 4, 12. ― Please refer to FIG. 4B, which shows the difference in height between the first semiconductor element 41 and the second semiconductor element 412. In this embodiment, the height difference between the two is about millimeters to! Between millimeters. In addition, there is a layer of thermally conductive adhesive coating 424 between the heat sink 42 and the first semiconductor element 410. Refer to Figure 4C for details. Figure 4C is a schematic cross-sectional view of the package structure of Figure 4A along line D-D. The heat sink 420 is disposed on the first semiconductor element 0, and the top surface 42 of the heat sink 420 far from the upper surface 402 of the substrate 400 and the back surface 427 of the second semiconductor element 412 may be approximately the same height, In this way, the thickness of the package structure of the entire semiconductor device can be reduced, and the package is light, thin, short, and small. : = Refer to Figure 4D. Figure 4D is a schematic cross-sectional view taken along the line D-D 'after the heat sink is installed in the "Picture of the Seal" because the heat sink 1

Page 15 1231979 V. Description of the invention (11) The top surface 425 of 420 is approximately the same height as the back surface 425 of the second semiconductor element 412, so a heat conductive adhesive coating can be applied to the heat sink 420 and the back surface 427 of the second semiconductor element 412. After 426, a heat dissipating device 428 is provided. The heat dissipating device 428 is attached to the back of the heat sink 420 and the second semiconductor element 412 to help the heat sink 420 and the second semiconductor element 412 to dissipate heat. The heat dissipation device 428 may also extend to cover the back surface of the second semiconductor element 412. In summary, the packaging structure with a semiconductor element of the present invention has at least the following advantages: a 1 'The packaging structure with a semiconductor element of the present invention, in which the semiconductor element is arranged on the same surface of the substrate, and the heat sink having an opening can Avoid thicker semiconductor components, thus reducing the thickness of the packaging structure of the semiconductor components, and thus achieving the goals of lightness, thinness, shortness, and smallness. 1 · ^ Benming's packaging structure with semiconductor elements, all semiconductor elements Γ ί Thermal interface material layer directly attached to the heat sink, the heat dissipation path is reduced The heat dissipation performance of this chip can be improved, and the cooling rate of the chip can be accelerated 3 Π 之 Α has a semiconductor device package structure, which has a low opening, and the seal is very simple, so it can reduce the manufacturing cost. This reduces the manufacturing cost of the package structure. It has a heat sink with an opening, and the setting end of the opening depends on the half-crossed: anti-Shi setting. In the two preferred embodiments of the present invention, however, the second = preformed heat sink structure is only for illustration, and it is out of the bounds of the Ming: Limiting the present invention to anyone who is familiar with this skill, will not Within the scope, when various changes and retouching can be made,

Page 16 1231979 V. Description of the invention (12) Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patents. _ «

Page 17 1231979 Schematic description [Schematic description JJ makes the above and its features of the present invention ^ Wen special mention-the preferred embodiment, and with the accompanying drawings, it is easy to clarify as follows: Figure shows the side view of a conventional blank chip with a package structure; 卞 1 ^ # ^ ^ ^ ^ ^ # ^ ^ ^ ^ ^ # t ^ _ Side view of a solution that is not unique Schematic diagram; Seal H shows a top view of a preferred embodiment of the invention with a semiconductor device structure arranged on a substrate; Figure 3; Figure B is a diagram showing the packaging structure of Figure 3A along the line a_a, a cross-sectional view & The diagram shows the package structure of FIG. 3A along B_B, and the cross-sectional view of the line is a diagram of the cross section of the package structure of FIG. 3A after the heat dissipation device is placed on the line # β ~ Β '; FIG. A is a schematic top view of a semiconductor device / mounting structure disposed on a substrate according to another preferred embodiment of the present invention; FIG. B is a cross-sectional view of the packaging structure of FIG. 4A along line c-c, Schematic = 4C shows the package structure of Figure 4A along D-D. A schematic diagram; FIG. 4D, and the second line shows the package in Figure 4A and then the heat dissipating means is provided

Page 18 1231979 Schematic illustration of the cross-section along the D_D 'line. [Simple description of element representative symbols] 100, 30 0, 400: Substrate 102, 30 2, 402: Surface 106: Solder ball 108: Filling material 11 0, 31 0, 41 0 ·· First semiconductor element 111, 311, 411 : Bump 112, 312, 412: second semiconductor element 114, 126, 320, 420: heat sink 11 6 · blank wafer 11 8, 1 2 0 · thermal interface substance _ 122, 328, 428: heat sink 124 Protruding portion 128: Flange 322: Notches 324, 326, 424, 426: Thermally conductive adhesive coatings 325, 425. Top surface 327, 42 7. Back surface 422: Opening

Page 19

Claims (1)

1231979 VI. Scope of patent application '" ^ --- 1. A semiconductor device package structure with enhanced heat dissipation efficiency, at least: a substrate having an upper surface; a first semiconductor element disposed on the substrate The upper surface is electrically connected to the substrate; a second semiconductor element is disposed on the upper surface of the substrate and is electrically connected to the substrate; and the thickness of the second semiconductor element is greater than the first semiconductor element; and A heat sink is disposed on the first semiconductor element and has at least one opening, wherein the second semiconductor element is located in the opening.丨 2. The semiconductor device package structure with enhanced heat dissipation performance described in item 1 of the scope of patent application, further comprising a thermal interface material layer (Thermal Interface Material, TIM) disposed between the first semiconductor element and the heat sink . 3. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the scope of patent application, wherein the first semiconductor device is a flip-chip wafer. 4. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 or 3 of the scope of patent application, further comprising a plurality of bumps disposed between the first semiconductor element and the substrate, and the first A semiconductor device is electrically connected to the substrate through the bumps. Page 20 1231979 VI. Scope of patent application 5 · The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the patent application scope, wherein the second semiconductor device is a wafer-size package structure. 6. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the scope of patent application, further comprising a heat dissipation mechanism disposed on the heat sink. 7. The semiconductor device package structure with enhanced heat dissipation performance as described in item 6 of the scope of the patent application, wherein the heat dissipation mechanism extends to cover the back of the second semiconductor device. · 8. The semiconductor device package structure with enhanced heat dissipation performance as described in item 6 or 7 of the scope of patent application, further comprising a thermal interface material layer disposed between the heat dissipation mechanism and the heat sink. 9. The semiconductor device package structure with enhanced heat dissipation performance as described in item 8 of the scope of patent application, further comprising a thermal interface material layer disposed between the heat dissipation mechanism and the second semiconductor device. 10. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the scope of the patent application, wherein the second semiconductor device is housed in the opening and surrounds the heat sink. 1 1. With enhanced heat dissipation as described in item 2, 8 or 9 of the scope of patent application 1231979 6. Scope of Patent Application Effective semiconductor device packaging structure, wherein the thermal interface material layer is a thermally conductive adhesive layer. -1 2 · The semiconductor device package structure with enhanced heat dissipation performance as described in item 6 or 7 of the scope of patent application, wherein the heat dissipation mechanism has a plurality of heat dissipation fins. 1 3. The semiconductor device package structure with enhanced heat dissipation performance as described in item 10 of the scope of patent application, wherein the size of the opening is larger than the size of the second semiconductor device. 4 1 4. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the scope of patent application, wherein the top surface of the heat sink is approximately the same height as the back surface of the second semiconductor device. 1 5. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the scope of patent application, wherein the top surface of the heat sink is slightly higher than the back surface of the second semiconductor element. 16. The semiconductor device package structure with enhanced heat dissipation performance as described in item 1 of the scope of patent application, wherein the top surface of the heat sink is slightly lower than the back surface of the second semiconductor element. 1 7. —Semiconductor component packaging structure with enhanced heat dissipation Page 22 1231979 VI. The scope of the patent application includes a substrate having an upper surface; a first semiconductor element disposed on the upper surface of the substrate and electrically connected to the substrate; a second semiconductor element, It is disposed on the upper surface of the substrate and is electrically connected to the substrate, and the thickness of the second semiconductor element is larger than the first semiconductor element; and, a heat sink is disposed on the first semiconductor element, and the heat sink is There is at least one peripheral notch, and the peripheral notch corresponds to the second semiconductor element so that the heat sink can avoid the second semiconductor element. 1 8. The semiconductor element packaging structure with enhanced heat dissipation performance as described in item 17 of the scope of the patent application, wherein the second semiconductor element is disposed at a corner of the substrate, and the peripheral notch is correspondingly disposed at the heat dissipation The corner of the film. 19. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 or 18 of the scope of patent application, wherein the peripheral openings are provided at the four corners of the heat sink, so that the heat sink is The semiconductor device has a similar structure with a shape other than the “ten” shape. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the scope of patent application, further includes a thermal interface material layer disposed on the first semiconductor device. And the heat sink. Page 23 1231979 VI. Scope of Patent Application 2 1 · The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the scope of patent application, wherein the first semiconductor element is a flip chip. 2 2. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 or 21 of the scope of patent application, further comprising a plurality of bumps disposed between the first semiconductor device and the substrate, And the first semiconductor element is electrically connected to the substrate through the bumps. 2 3 · The semi-conducting φ body element package structure with enhanced heat dissipation performance as described in item 17 of the scope of patent application, wherein the second semiconductor element is a wafer-size package structure. 24. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the scope of patent application, further comprising a heat dissipation mechanism disposed on the heat sink. 25. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the scope of patent application, wherein the heat dissipation mechanism extends to cover the back of the second semiconductor element. 2 6. The semiconductor device package structure with enhanced heat dissipation performance as described in item 24 of the scope of patent application, further comprising a thermal interface material layer disposed between the heat dissipation mechanism and the heat sink. Page 24 1231979 VI. Scope of patent application Heat conduction and semi-dispersion can be used in the thermal distribution and dispersion layer. The items included in the package include the 6th package, the second version of the package, the semi-exclusive structure of the guide structure, and the second package. Please install the package and the 7 · 27 frame machine 2 8. If the scope of the patent application is No. 20, The semiconductor device package structure with enhanced heat dissipation performance according to item 26 or item 27, wherein the thermal interface material layer is a thermally conductive adhesive layer. 29. The semiconductor device package structure with enhanced heat dissipation effect φ as described in item 24 or 25 of the scope of patent application, wherein the heat dissipation mechanism has a plurality of heat dissipation fins. 30. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the scope of the patent application, wherein the size of the peripheral notch is not less than the size of the second semiconductor device. 3 1. The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the scope of patent application, wherein the top surface of the heat sink is approximately the same height as the back surface of the second semiconductor component. 3 2. As a patent application The semiconductor device package structure with enhanced heat dissipation performance described in the item 17 of the scope, wherein a top surface of the heat sink is slightly higher than a back surface of the second semiconductor device. Page 25 1231979 VI. Patent application scope 3 3 · The semiconductor device package structure with enhanced heat dissipation performance as described in item 17 of the patent application scope, wherein the top surface of the heat sink is slightly lower than that of the second semiconductor device. the back of. 3 4. —Semiconductor element package structure with enhanced heat dissipation performance, including at least: a substrate having a first surface; a flip-chip mounting component electrically connected to the first surface of the substrate; a plurality of wafer-size structures The mounting element is electrically connected to the first surface of the substrate; φ and a heat sink are disposed on the first semiconductor element, wherein the heat sink exposes the top surfaces of the wafer-size mounting elements. 35. The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of the patent application, wherein the flip-chip mounting component and the heat sink further have a thermal interface material layer. 36. The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of the patent application, wherein the flip-chip mounting device is a flip-chip wafer. _ 3 7 · The semiconductor device packaging structure with enhanced heat dissipation performance as described in item 34 of the scope of the patent application, wherein the heat sink has at least one opening, and the wafer-size structural components are located in the opening to Make the heat sink visible Page 26 1231979 VI. Scope of Patent Application The top surfaces of these wafer-size components are exposed. 38. The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of the patent application, wherein the heat sink has at least one peripheral gap j " and the chip-size structural components are located on the periphery Inside the notch, so that the heat sink is exposed on the top surface of the chip-size component. 3 9 · The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of the patent application, wherein the peripheral openings are arranged at the four corners of the heat sink so that the heat sink has similar characteristics. Ten " outlook. _ 丨 40. The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of patent application, which includes providing a heat dissipation mechanism on the heat sink. 4 1. The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of patent application, which includes providing a heat dissipation mechanism on the heat sink and the chip-size structured components. 4 2. The semiconductor device package structure with enhanced heat dissipation performance as described in item 40 of the scope of the patent application, wherein the heat dissipation mechanism and the chip-size component and the heat sink further have a thermal interface material layer. . 4 3.Semiconductor with enhanced heat dissipation performance as described in item 41 of the scope of patent application Page 27 1231979 VI. Scope of patent application For body component packaging structure, there is a thermal interface material layer between the heat dissipation mechanism and the chip-size component and the heat sink. 44. The semiconductor device package structure with enhanced heat dissipation performance as described in item 35, item 42, or item 43 of the patent application scope, wherein the thermal interface material layer is a thermally conductive adhesive layer. 4 5. The semiconductor device package structure with enhanced heat dissipation performance as described in item 40 or 41 of the scope of patent application, wherein the heat dissipation mechanism has a plurality of heat dissipation binding pieces. 46. The semiconductor device package structure with enhanced heat dissipation performance as described in item 34 of the scope of the patent application, wherein the top surface of the heat sink is slightly higher than the back surface of the chip-size components. 47. The semiconductor device package structure with enhanced heat dissipation performance described in item 34 of the scope of the patent application, wherein the top surface of the heat sink is slightly lower than the back surface of the chip-sized component. Page 28