TWI231091B - Crystal oscillator circuit with activation control - Google Patents

Abstract

A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.

Description

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[Technical field to which the invention belongs] The present invention relates to a complementary metal-oxide-semiconductor (CM0s) crystal oscillator ', and more particularly to a clock generator with start-up control. [Prior Art] Figure 1a is a conventional knowledge The crystal unit 100a is used to generate a clock pulse alum. In order to generate the clock signal, the input terminal and the output terminal] are coupled to an external oscillation source, such as a quartz crystal circuit, so that an oscillation signal can be amplified by the amplifier 102 and output to the shaping circuit.丨 〇4. The vibrating signal is basically a sine wave, and the shaping circuit 104 may be a shaping transient, used to convert the oscillating signal into a square wave. With this, the crystal unit becomes a clock generator for 10 h. This architecture is widely used due to its reliability and simplicity, but it has some disadvantages, such as uncertain startup time. As shown in Figure 丨 b, the traditional approach is to add a counter 07 to solve this problem. The counter 1 0 7 can count the number of times of the square wave change, and send out a ready signal when the number of changes reaches a certain value. This design requires additional costs and can cause counting errors due to noise bounces, which can cause the system to crash. b Figure lc shows another crystal unit 100b in the conventional technique. The input terminal 101, the amplifier 102 and the output terminal 103 are no different from those in the first figure. However, the shaping circuit 104 is replaced with a hysteresis circuit 105. This method is still popular for its reliability, ease of use, and low cost. However, if the hysteresis circuit 105 uses a small hysteresis device, the problem of counting errors still exists in the counter 107 (as shown in Figure 1d), and if a large hysteresis device is used, it is easier to jump because of the power supply. (Power bouncing)

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The (deasserted) step may include a switching circuit. Prevent the clock signal from being output. The clock generator is further configured to turn off the detection when the sah-ready signal is established. The present invention also provides a method for controlling the start of a clock signal. First, the generation-oscillation signal 'is converted into a clock signal. A detection circuit is then provided to detect the amplitude of the oscillating signal, and a -ready signal is set when the amplitude exceeds a -ratio of a full swing voltage. Finally, when the ready signal is set, the detection circuit is turned off and a clock signal is output. [Embodiment] & Detailed examples of the present invention are provided as follows. The main spirit of the present invention is to add a set of detection circuits to determine when the oscillating signal is ready for use. As shown in Fig. 2a, in a crystal unit 200a, the input terminal 101, the amplifier 102, the output terminal 103, and the shaping circuit 104 are no different from those in Fig. 1a. The difference is that a detection circuit 201 including a large hysteresis circuit 202 is added, which is coupled to the output terminal 103. The large hysteresis circuit 202 can be used to detect the amplitude of the sine wave output from the amplifier 02. The large hysteresis circuit 202 is responsible for handling the readiness detection function, and its large hysteresis characteristic eliminates the problem of counting errors. In contrast, what is included in the forming circuit 〇04 is a small hysteresis circuit, or a Smith trigger (Schmit1: trigger). The small hysteresis characteristic can be used to prevent the impact caused by power bounce. two. As shown in Figure 3, when the clock generator is powered on, the oscillating signal is displayed as a sine wave. With time, the amplitude gradually increases, and finally a full swing signal is finally formed. In an embodiment, compared with the amplitude of the full swing signal, when the peak of the oscillating signal is higher than 75% and the trough is lower

1231091 V. Description of the invention (4) At 25%, the clock generator is considered ready. Then, the large hysteresis circuit 202 sends a ready signal, so that subsequent related actions are successively performed. In Figure 2b, a switch 2 0 4 is added. Since the detection circuit 2 0 j is only used to detect the ready state, it can be turned off after the work is completed. For example, by using the ready signal, the switch 204 turns off the detection circuit 201. In Fig. 2c, taking another embodiment, the detection circuit 201 further adds a counter 206 for counting the number of amplitude changes output by the large hysteresis circuit 202. Therefore, the method of determining the signal readiness can be based on the amplitude of the amplitude or whether the number of times between the positive and negative values of the oscillation voltage has exceeded a certain value. Due to the large hysteresis characteristic of the large hysteresis circuit 202, the problem of counting errors is unlikely to occur, so the reliability of detection is ensured. In addition, the X-oscillation signal is converted into a square wave by the shaping circuit 104, rather than through the large hysteresis circuit, so an unbalanced working cycle will not be generated due to power bounce. When the ready signal is set by the counter 2 0 6, the switch 2 0 is closed at the same time to stop the detection circuit 2 1 (including the large hysteresis circuit 2 0 2 and the counter 2 0 6).彳 FIG. 2d illustrates another embodiment, in which a logic AND gate 210 is added to control the rotation of the crystal unit 200d. The logic AND gate 210 will not output a square wave until it receives the ready signal from the start reset counter 208. In other words, at this time, the pulse generator is under the control of the logic AND gate 210, and will not output any unwanted noise or unread pulse signals. Until the logic AND gate 210 is opened due to the ready signal, the clock signal can be used for output.

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1231091 Brief description of the drawings [Simplified illustration of the drawings] The embodiments of the present invention will be best understood with the following drawings, among which: Figures 1a to 1d are the various types of conventional clock generators. Architecture diagrams; Figures 2a and 2d are structural diagrams of various embodiments of the clock generator of the present invention; and Figure 3 is a signal variation curve regarding Figures 2a to 2d. [Description of main component symbols] 10 0a to 100d crystal unit 101 to, input terminal 102 to 'amplifier 103 to, output terminal 104 to, forming circuit 105 to. Hysteresis circuit 107 to' counter 201 to ', detection circuit 2 0 2 ~ Large hysteresis circuit 204 ~ Switch 2 0 6 ~ Counter 20 8 ~ Start reset counter 210 ~ Logic AND gate (AND gat 2 0 0 a, ~ 2 0 0 d,-crystal unit

0697-A40233TWF (N2); P2004-002-TW-B; YEATSLUQ; .ptd Page 11

Claims (1)

1231091 6. Scope of patent application-Clocks with start-up control can generate cry, No., including ... 叩 used to generate a clock signal amplifier, including a round-in endpoint connected to an external field, & an output endpoint connected to the Wai Si according to the external vibration source, and the number, · To be connected to an external vibration source and generate a vibration circuit in Zhenhai, which is used to couple to the wheel number to generate a clock signal; The oscillating signal: = At the end of the round, and when the vibration is complete-Proportion :; two full swing electric-(ful1 _ ". ㈣d's assert (assert)-ready signal. Proportion 2 is the first round The clock generator according to item 1, wherein the peak of the signal is higher than 75% and the trough is lower than 100% of the two-inch field, as described in the first patent application scope The circuit sets up the ready signal. Detector 4: The clock generator described in item 1 of the patent scope, wherein the #a first hysteresis circuit is used to detect whether the amplitude of the oscillating signal exceeds the ratio of the dagger, and To produce a result; and a ready controller, using According to the result, the ready signal is generated. ^ 5 · The clock generator as described in item 4 of the patent application scope, wherein the first hysteresis circuit is a Schmitt trigger, / 6 The clock generator according to item 4 of the patent scope, wherein the shaping circuit is a second hysteresis circuit, which has a lower value than the first hysteresis circuit. Page 12 0697 · 3 _); ρ ^^^ 7 1231091 2. Hysteresis threshold voltage 2. Clock generator as described in item 4 of the scope of patent application, wherein the ready controller includes a counter to calculate the number of changes in the result, when the number of changes exceeds a certain When set, the ready signal is established. 8. The clock generator as described in item 7 of the scope of patent application, wherein the ready controller further includes a power on res2t to reset the counter during the startup phase. 9 · The clock generator as described in item 4 of the scope of the patent application, further comprising a logic gate for outputting the clock signal when the ready signal is set up and releasing the ready signal ( deasserted) to prevent the clock signal from being output. I 〇 The clock generator as described in item 1 of the scope of patent application, further comprising a switch for turning off the detection circuit when the ready signal is set. II. A method for starting and controlling a clock signal, including the following steps: generating an oscillating signal; shaping the oscillating signal to generate a clock signal; providing a detection circuit for detecting the amplitude of the oscillating signal; when the oscillating signal When the amplitude exceeds a ratio of a full swing voltage, a ready signal is set up; and when the ready signal is set up, the detection circuit is turned off and the clock signal is output. 1 2. The startup control method as described in item 11 of the scope of patent application, wherein the proportion is 50%. 0697-A40233TWF (N2); P2004-002-TW-B; YEATSLUO; .ptd Page 13 l23l09i-13. The startup control method as described in item 11 of the scope of patent application, which is the peak of the oscillation signal When it is above 75% and the trough is below 155%, the ready signal is established. 1, 4 · The start-up control method described in item 11 of the scope of patent application, further comprising: calculating the number of amplitude changes of the oscillating signal, and setting up the ready signal when the number of changes-the number of people exceeds a certain value. 1 5 · The startup control method described in item 14 of the scope of patent application, further comprising resetting the number of changes during the startup phase. 0697-A40233TWF (N2); P2004-002-TW-B; YEATSLUO; .ptd page 14