TWI229447B - High density multi-state mask ROM structure and its forming method - Google Patents

Abstract

Firstly, an oxidation layer is formed on a semiconductor substrate, next a plural number of first coding blocks are formed by patterning, then a photoresist pattern is formed on the first coding blocks and a plural number of first openings on the semiconductor substrate among the first coding blocks are formed, an n-type ion implant is formed to form doped area, after peeling off photoresist pattern, a high temperature hot oxidation process is performed to grow type I, type II, and type III oxidation blocks with various thickness respectively on the doped area, the first coding blocks, and the rest of blocks, therefore embedded bit lines are formed, a conductor layer is formed and patterned to define word line, a photoresist pattern is formed where the opening is used to define the second coding block that is located under some type II and type III oxidation blocks, the photoresist pattern is used as mask to perform an ion implant to form the second coding block, and after peeling off the photoresist, a multiple threshold voltage region is formed by annealing.

Description

1229447 V. Description of the invention (1) Field of invention: t

I The present invention relates to a process for manufacturing a semiconductor device, and more particularly to a high-density multi-state mark of a single polycrystalline silicon gate. § Mask read only memory (mask ROM) Component structure and manufacturing process. Background of the Invention: In recent years, with the advancement of semiconductor integrated circuit manufacturing and design technology, many popular electronic products, such as notebook computers, mobile phones, digital cameras, second-generation PLAY-STATION, personal digital assistants, MP3 Players and other electronic products have the same characteristics: light, thin, short, r

I | Small. Generally speaking, the reason why these products can achieve the above-mentioned characteristics is that high-density non-volatile tags are only indispensable for read-only memory. To achieve high-density labeled read-only memory technology, you can refer to the paper by Bertagnoili et al. "Bertagnoili et al.,’ R0S:

An Extreme 1y High Density Mask ROM Technology Based On Vertical Transistor Cells ^ Symp. On VLSI Tech. Dig ·, p, 58, 1996 · ’’. In this reference, the idea of forming a vertical metal-oxide-semiconductor crystal in a trench is proposed. The bottom of the trench is allowed in the trench as a self-aligned bit line. As a result, the density of bit lines is doubled. This technology is therefore about twice the packing density of traditional flat read-only memory. ;

Page 4 1229447 V. Explanation of the invention (2)! However, if you want to double the storage capacity and not use it as an alternative, you can use the multiple methods. The new concept of love and ability, and w ji deng heart (that is, 33 丨 丨 * 1 丨 丨; including ^ ^ ^ ^ 惶 匕 moon dagger enough to store data 丨 丨 (Γ or i 1 two. Then, bound It requires more electricity than a multi-state memory that can store 4 kinds of memory energy (〇, i, | 2, .3). 5 ^ 叩 et al., Published in December 1996 U.S. Patent No. 5,58 5, 2, 97, obtained on the 17th, proposes a multi-state (more than three-state) read-only memory. The technology used is more than two times of boron Ion implantation, combining the use of multiple masking techniques and varying implant doses to adjust the starting voltage. However, high-dose greenhouse ion implantation will result in encoding. The characteristics of the breakdown voltage of the metal-oxide-semiconductor crystal interface deteriorated, and the problem of leakage current caused by two adjacent memory cells. This aspect is in Ira The "U.S. Patent No. 5,6 8 3, 9 2 5" obtained by ni et al. on November 4, 1997, reported the structure shown in the figure below to solve the above problems. In this method, in the read-only memory block 3, "the gate oxide layer 18 which is long and thick by thermal oxidation method is used, only the electrode oxide layer between the periphery 3 and 2 is thinner. 2 US Patent No. 5 , 5 5 6, 8 0 0, patented by Takiziawa et al. On 996 = 17, reported another method. Takiziawa et al .: The thickness of the gate insulation layer was changed to change the opening of the channel. Starting voltage. The channel block is divided into two parts. The gate oxidation of the first part and the other part

Page 5 1229447 V. Description of the invention (3) The thicknesses of the layers are different. Therefore, when the ion implantation is applied, there are different penetration depths, that is, the concentration of impurities is changed. In other words, the gate oxide layer should have a gate voltage, but in the channel block adjacent to each other, it has different drain current characteristics. |

I Another recently reported method of marking read-only memory with multiple memory states is proposed by Wu. Please refer to U.S. Patent No. 6,133,102, published on October 17, 2000. In this method, we refer to the complex crystals defined by two times | i-break gates to achieve a multiple density of bit linear density and combine two different thicknesses of i-oxide layer and two ion implantation to achieve high-density multiple memory state mark Only Φ I reads the memory. The purpose of the present invention is to propose a simpler method than the previous case to achieve the purpose of multi- / i memory state marking read-only memory. In this method, it is only necessary to use two times: I use a thermal oxide layer and two ion implantation and use a single polycrystalline silicon and patterning technology

I i operation, that is to form a multi-memory mark read-only memory cell. Purpose and summary of the invention:

The purpose of the present invention is to provide a method for forming a multiple-memory read-only memory, so that the effect of maximizing the memory capacity can be produced at the minimum chip area. I The present invention discloses a method for forming a multi-memory mark read-only memory (mask i ROM) on a semiconductor substrate. The method of the present invention includes at least 1229447 V. Description of the invention (4) The next step: first, it is formed by a thermal oxidation method An oxide layer is formed on the semiconductor substrate; then, patterning is performed to form a plurality of equidistantly separated first coding regions; subsequently, a photoresist pattern is formed on the first coding block and the A plurality of first openings are formed on the semiconductor substrate between the first coding blocks. jj ί I, using the photoresist pattern as a mask, applying the first ion implantation, implanting a first doped region doped with n-type impurities; after removing the photoresist pattern, apply a high temperature The thermal oxidation process grows first-type oxide regions | blocks, second-type oxide blocks, and third-type oxide blocks of varying thicknesses, and the first-type oxide block j | is formed on the first doped region, and the second A type oxide block is formed in the first coded φ region, and a third type oxide block is formed on the remaining blocks. In addition, it drives the n-type conductive impurities to diffuse inside the semiconductor substrate to form a buried type.

I I bit line block. '! j Next, a first conductor layer is formed on all surfaces, and then patterned to define a word line; after that, a photoresist pattern is formed, and the photoresist pattern opening is used to define a second coding region. The second coding area is located under some type II oxide blocks and some type III oxide blocks; then, a photoresist pattern is used as a mask, and a second ion implantation is applied to implant ρ Type impurities to form a second coding region. Finally, after stripping the photoresist pattern, annealing is performed to form a multi-state read-only memory with multiple restart start voltage regions. _; i 1 Detailed description of the invention:

Page 7 1229447 V. Description of the invention (5) For details of the method of the present invention, please refer to the illustrations. ^ | | I Please refer to FIG. 2. Firstly, a pad oxide layer 1 1 0 with a thickness of about 20-50 nm | i is grown on a semiconductor substrate 105 by a thermal oxidation process. The pad oxide layer 11 〇 is used as the first coding oxide block. Next, please refer to the cross section shown in Figure III 丨

In a schematic diagram, a photoresist is formed on the pad oxide layer 110, and the first coding region 110A is defined by a lithography technique Ij · |. The exposed pad oxide layer is then wet-etched, for example, a BOE (buf f r r ox i de e t ch i ng) solution is removed. i! Please refer to the cross-sectional diagram shown in Figure 3. After etching, the photoresist pattern can be removed first, or another photoresist pattern 13 0 can be applied without removing to define the word line. The photoresist pattern 13 0 includes a photoresist layer covering the first coding region 110A and a plurality of photoresist layers formed between the first coding regions 110A (to; " 丨 less every two adjacent first Suppose there is a new photoresistor between the 1A and 1A, | layer). Therefore, as shown, a plurality of openings 14 are formed to define the buried bit line area 14 0. Subsequently, the first ion implantation is applied, and the photoresist pattern 13 is used as a mask. The first conductive impurity is implanted into the semiconductor substrate 105 through the opening 14 to form: # heteroregion 1 45. In a preferred embodiment, the energy and dose used for ion implantation are about 10-12 keM 5χ i 〇4-4χ 1016 / cm2 ° In addition, the 'conductive impurities are selected from phosphorus and arsenic and One of the ethnic groups formed by the combination. After the implantation, the photoresist pattern 1 3 0 is removed. 1229447 Five 'Explanation of invention (6) I.-after one' As shown in Figure 5, a thermal oxidation process is applied at a temperature to grow the second atmosphere, nitrogen atmosphere, and high-type oxidation at 70-105 ° C. Block 150B and ~ potential-~ split oxidation block 150A, the first and second type gas block 15 (^ refers to the oxide layer located in the doped [? 1/1 ^ old ^ block 150C. Type 1 oxide growth Since the semiconductor substrate is formed there in time, the two Γ ′ are thicker at the position of the type I impurity in the same thermal oxidation process. No .: The chemical conversion layer will be non-conductive than the others; 30-100 nm. The type oxide block 15OA has a thickness of about i 4 b. Therefore, the doped region has conductive impurities. The second type oxide block 15_ refers to the long erbium oxide layer on a plate. This second type oxide bar δ is Ma + + conductor base block and newly-grown oxide layer, thick ghost ιo 5β includes a stone horse oxidation area F 1 W μ, f $ Jing Jin 5 ~ 60nm. And the third type of oxidation

& Block 1 50C is a θ β w L other than the upper-speed two-type oxidation block. θ β w L is a block of r 仏. n, that is, only a newly grown oxide layer block. The force is 3-20 nm. thickness. In addition, a buried buried bit will be formed in the doped region layer. In addition to the growth of the oxide layer 145, impurities in the thermal oxidation process are driven into the semiconductor substrate i 05 and the inner line region 145A. Please refer to the schematic diagram of the cross section shown in Figure 6. A first conductive layer 160 is formed to a thickness of about 50 to 500 nm by a chemical vapor deposition method. The material of the first conductor layer 160 is selected from a synchronously doped polycrystalline silicon layer (which may be doped with phosphorous or phosphorus, or a metal silicide of refractory element or refractorable metal.) Then, through lithography and etching technology Patterned to form a word line 160.

Page 9 1229447 V. Description of the invention (7) Please refer to the schematic diagram of the cross section shown in Fig. 7. A photoresist pattern 1 7 0 is followed by / coated on all surfaces, and then the second coding area is defined by lithography technology. 1 8 0. The opening of the photoresist pattern 170 (predetermined second coding region 1 8 0) is set | in some blocks, these blocks have either a second type oxidation block 1 5 〇 B or i has a third Block 150C of the type oxidation block, but do not set all the blocks of the second type oxidation block I 150B and the second type oxidation block 150C to the second coding block 180.

I!

After the second coding area 1 80 is defined, a second ion implantation is performed. I use a high energy planting of 40-300keV with a photoresist pattern 17 0 as the mask, and the impurity _ i passes through the conductor layer 160 and is implanted. The implantation dose is about 5x 1 0 12- 2x I 10 15 / cm2. In addition, the second planting system uses a member selected from the group consisting of boron and BF2 and its group.

One of the p-type conductive impurities of the group consisting of I i compound. -

After the ion implantation, the photoresist pattern 170 is removed first, and then an annealing process is performed to activate the implanted ions. Therefore, about four kinds of starting voltages will be built! I stand below the first type oxidation block 150A, the second type oxidation block 150 B, and the third type oxidation block 150 C. The magnitude of the initial voltage depends on the thickness of the oxide layer on it and whether it is implanted with P-type conductive impurities. According to this, there are four kinds of starting voltages vtO, vtl, vt2, and vt3 corresponding to the block j 1 I of the third type oxidation zone. There are coded plants. Figure 8 shows the high-density multiple memory pattern formed according to the method of the present invention

Page 10 1229447 V. Description of the invention (8) Outline layout. There are four memory patterns (four start voltages) along the A-A 'line. The first area is 180, which has a first coding oxidation block and an i-th and second coding plant; the second area 190, which has a second coding plant, and the third zone, 200, which has a The first coding oxidation block; the fourth region 210 has a third type i oxidation block.

I

[

I i | Figure 9 shows the results of verifying the starting voltage according to the coding conditions (that is, different oxide layer thicknesses and planting conditions). | 1

I Please note that the coded planting conditions in Figure 9 are based on the implantation of electrical impurities with BF2 as the conducting material, the energy of the planting is 100keV, and the planting system is to pass through the 2 5 nm oxide layer as a channel effect. Buffer layer. For example, the implantation of sample B is 1.00E + 14 / cIn BF2 + at 100 keV. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should include In the following applications

Within the scope of I patent.

1229447 on page 11 is a schematic illustration of the preferred embodiment of the present invention, which will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows the horizontal direction of the mark-only memory formed according to the conventional technology Schematic cross-section. FIG. 2 is a schematic cross-sectional view of an oxide layer of a growth pad on a silicon substrate according to the technology of the present invention. FIG. 3 is a schematic cross-sectional view of a patterned pad oxide layer to form a coded oxide block according to the technology of the present invention. FIG. 4 is a schematic cross-sectional view of forming a photoresist pattern to define a buried bit line region and applying the first ion implantation according to the technology of the present invention. FIG. 5 is a schematic cross-sectional view of applying a thermal oxidation process to grow oxide layers of different thicknesses according to the technology of the present invention. FIG. 6 is a schematic cross-sectional view of forming a first conductor layer according to the technology of the present invention and then patterning the first conductor layer. FIG. 7 is a schematic cross-sectional view of forming a photoresist pattern to define a second coding region and applying a second ion implantation according to the technology of the present invention. FIG. 8 shows a schematic layout of a mark-only memory of a high-density multiple memory state formed according to the technology of the present invention. Figure 9 shows a table of high-density multiple-memory mark read-only memories that simulates the starting voltage data based on different oxide layer thicknesses and implant conditions.

Page 12

Claims (1)

1229447 VI. Scope of patent application 1. A method for forming a multiple memory state mark read-only memory (mask ROM) on a semiconductor substrate, the method includes at least the following steps: | forming a pad oxide layer on the semiconductor substrate; Patterning the pad oxide layer to form a plurality of first coding regions @; forming a photoresist pattern on the first coding region and the substrate substrate U to form a plurality of first openings; The first ion implantation is used to implant a first conductive impurity into the semiconductor substrate through the I first opening to form a first doped region, and the photoresist I 丨 pattern is used as a mask; removing the photoresist Pattern; _ j applying a first high temperature thermal oxidation process to form an oxide layer on the semiconductor substrate, and driving the first conductive impurity into the semiconductor substrate to form a buried buried bit line region Forming a first conductor layer on the oxide layer; i-patterning the first conductor layer to define a word line; forming a photoresist pattern on all surfaces, the photoresist pattern having a second I opening As second coding And a second ion implantation to implant a second conductive impurity into the semiconductor substrate to form a second coding region, using the photoresist pattern as a mask, and forming multiple Restart the starting voltage predetermined range. % i · 2. The method according to item 1 of the scope of patent application, wherein the plurality of first coding blocks described above include a plurality of first openings between any two of the first coding regions I: between.丨 Page 13 1229447 VI. Application scope of patents | 3. For the method of the first scope of patent application, wherein the above-mentioned oxide layer includes I-type 1 oxidation block, a second-type oxidation block, and a third-type oxidation Zone | Block, and the thickness is about 30-100nm, 15-60nm, and 3-20nm, respectively. II 4 · According to the method of claim 1 in the scope of patent application, after performing the above-mentioned first high temperature thermal oxidation process, the above-mentioned first type oxidation block is formed in the first doped region and the second type oxidation The blocks are formed in the first coding region, and the third type: oxidized blocks are formed in the remaining blocks. | 5. The method according to item 1 of the scope of patent application, wherein the energy and dose for the first ion implantation described above are about 1 0-1 2 0 ke V and 5x 1 0 14-2x: 1016 / cm2, In addition, the first conductive impurity is one selected from the group consisting of phosphorus, arsenic, and a combination thereof. | 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned first high temperature I thermal oxidation process is in the range of 7 0-1 0 50 ° C. 7. The method according to item 1 of the scope of patent application, wherein the energy and dose used for the second ion implantation are about 4 0-3 0 0 keV and 5x 1 Ο 12-2x I 10 15 / cm2, in addition; The second conductive impurity is one selected from the group consisting of boron, BF 2+ and combinations thereof. ! I 8. The method according to item 3 of the scope of patent application, wherein the second coding area described above Page 14 1229447 ^ --—_——--- · I 6. Scope of patent application Block i contains at least some of the type II oxidation blocks or type III oxidation blocks mentioned above. 9. The method according to item 1 of the scope of patent application, further comprising, after the second ion implantation step, removing the photoresist pattern and then annealing to activate the second conductive impurity. 10. A method of forming a multiple memory state mark read-only memory (mask R OM) on a semiconductor substrate, the method includes at least the following steps:! Forming a pad oxide layer on the semiconductor substrate; I i patterning The pad oxide layer forms a plurality of equally spaced first coding regions Φ regions; a photoresist pattern is formed on the first coding block and on the semiconductor substrate between the first coding blocks. Forming a plurality of first openings; / applying a first ion implantation to implant a first conductive impurity into the semiconductor substrate through the first β | opening to form a first doped region with the photoresist pattern i is the mask; remove the photoresist pattern; apply the first high temperature thermal oxidation process to grow the first type oxidation block, the second type oxidation block and the third type oxidation block, the first type oxidation region Blocks are formed in the first doped region, the second-type oxide block is formed in the first coded region, the third-type oxide block is formed in the remaining blocks, and the first conductive impurity is driven Diffuse into the semiconductor substrate and drive A first conductive impurity into the semiconductor substrate to form a buried region of the bit line block; Page 15 1229447 6. Scope of patent application 丨 | Form a conductor layer and pattern it by lithography and etching to define 丨 word lines; | I form a photoresist pattern defining a predetermined block of the second coding area , Where the predetermined block of the I · I coding area is located under certain type II oxidation blocks and / or the i type III oxidation block; and I applies a second ion implantation to implant A second conductive impurity is introduced into the semiconductor substrate to form a second coding region, and the photoresist pattern is used as a mask. II, a predetermined region of a multi-start voltage region is formed. : 11. The method according to item 10 of the scope of patent application, wherein the first type oxygenated block, a second type oxidized block, and a third type oxidized block, and the thicknesses of each are approximately 30 -100nm, 15-60nm, and 3-20nin thickness. ~~ 12. If the method of claim 10 is applied, the energy and dose of the first ion implantation mentioned above are about 10-120keV and 5χ 10 14-2χ J 0 1β / cm 2 respectively. The first conductive impurity is one selected from the group consisting of phosphorus, arsenic, and combinations thereof. 1 3. The method according to item 10 of the scope of patent application, wherein the first high-temperature thermal oxidation process described above is in the range of 700-105 ° C. Call I 1 4. The method according to item 10 of the scope of patent application, wherein the energy and dose used for the second ion implantation are about 40-3 0 0 ke V and 5x 1 0 12- 2x 10 15 / cm2, and the second conductive impurity is selected from boron and BF2 + and Page 16 1229447 6. Scope of Patent Application 丨 | One of the groups formed by the combination. Bu I: | Il5. The method according to item 10 of the patent application scope further includes a second ion j: implantation step, first removing the photoresist pattern and then annealing to activate the second conductive impurity. . 1. 6. A multiple-memory mark read-only memory (mask ROM) structure, the i-mark read-only memory structure includes at least: | a semiconductor substrate, the semiconductor substrate contains at least three different thickness I degrees of oxidation There are a plurality of layers, the thickest of which is the first type oxide block, the 0th second type oxide block is the second thickest and the third type oxide layer is the thinnest. A second type oxide block or a third type oxide block | block, and the semiconductor system immediately under the first type oxide block is used as the mark; < i the bit line buried under the read memory, Some of the semiconductor substrates under the second and third type oxygen and I-type blocks have channels doped with P-type conductive impurities by ion implantation, and the remaining number of second-type oxide blocks and The III-type semiconductor substrate does not have a channel doped with P-type conductive impurities by ion implantation. Therefore, the mark read-only memory structure has at least four different starting voltage operation modes. 1 7. Mark the read-only memory structure according to item 16 of the scope of patent application, where I; | The first type oxide block, the second type oxide block and the third type oxide block described above, the thickness is about 30-100nm, 15-60nm, and 3-20nm. Page 17 1229447 VI. Application scope of patent 18. For example, the mark read-only memory structure of item 16 of the scope of patent application, wherein the above-mentioned buried bit line has a family selected from the group consisting of phosphorus and arsenic and combinations thereof. | Ion doping of one of the groups. I | 19. If the marked read-only memory structure of item 16 in the scope of the patent application, the above-mentioned four different starting voltage operation modes are based on the different types of oxidized blocks on the channel, and whether they have ionic distribution It is produced by doping p-type conductive i-type impurities in a planting manner.