TWI228681B - Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache - Google Patents

Abstract

A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query pass and one or more finish passes. When the cache detects a snoop query intervening between the query pass and a finish pass of the in-flight operation, the cache generates a more up-to-date status for the snoop query that takes into account the tag status to which the in-flight finish pass will update the implicated cache line. This is necessary because otherwise the snoop query might not see the affect of the in-flight finish pass status update. This allows the in-flight finish pass to complete instead of being cancelled and the snoop finish pass to correctly update the status after the in-flight finish pass, and to provide modified data from the cache line to the externally snooped transaction.

Description

1228681 V. Description of the invention (1) [Technology to which the invention belongs] [0002] The jaw field, especially with memory and external peeping [Prior art] [0003] Xu j That is, it includes the computational load of the coupling system. Memory. Further, it is often hierarchical. [0 0 0 4] The internal memory of the cache is usually much smaller than the system material transfer, which is much faster than reading the system memory from the system memory, so take the memory to read the place and process it next time. The device writes data to the cache immediately. Access to cache memory can reduce the entire resource [0005] Quick Street field] 'Ming is about the multi-pass pipeline (mu 11 i-pass) of the cache memory in the microprocessor The effect of operations on it. Modern computer systems are multiprocessor systems. Also, multiple processors on a shared bus are shared to share the system. In addition, multiple processors usually share a common system. Each processor includes cache memory, its access memory. Take the cache memory (cache memory or cache) as the processing part of the system memory, and the memory. The cache memory of the processor is used to transfer data between the server and the memory. When the processor fetches the material, the processor will also store the data into its cache. When the processor needs to read the data, it can be faster from the fast time ~ small ... also 丨 think of the limbs to retrieve the material. Similarly, the > data is written to the system memory address (its data is stored, the processor only needs to write to the cache memory, and it is not necessary. It is generally called write-back (sen "-) fast data, without having to access the memory This kind of energy can greatly improve the system performance. The hidden body will store data in the cache line. Generally 12268681 V. Description of the invention (2) The cache line size is 32 bytes. Fast The fetch line is the smallest unit of data that can be transferred between the cache memory and the system memory. That is, when the winter virtual phase reads from the memory-a cacheable data, the packet is fast; the line is all read Fetch, and store the entire cache line into cache memory. Similarly, when a new cache line is written to the cache memory, instead of a modified cache line, the processor Writes the entire replaced cache line to memory.

[0 0 0 6] Multiple processors each have their own cache memory to cache data from a total of dry memory. This situation will cause a cache memory consistency problem. That is, the memory that one processor sees through its cache memory is different from the memory that another processor sees through its cache memory. For example, suppose a location x in memory contains the value of 丨. Processor A reads from memory address X and caches the value of 1 into its cache memory. Then, the processor B reads from the memory address X, and caches the value of 1 to its cache memory. Then, the processor A writes the value of 0 to its cache memory, and updates the address X of the memory to the value of 0. Now if processor A reads address X, it will receive 0 from its cache memory; but if processor B reads address X, it will receive i from its cache memory. [00 〇 7] The above example shows the need to track the status of any cache line shared by more than one cache memory in the system. There is a common architecture for maintaining cache coherence, commonly called snooping. By peeking, each cache memory records a copy of the shared state for each cache line it holds. Each cache memory monitors or peeks at every job on the bus shared by other processors to

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(2) Determine whether it has a dependent line of the bus operation initiated by another processor. Cache memory Zhao performs different actions based on the type of job being watched and the pain of its dependent line, '. A commonly used cache memory is the mind 51 agreement. MEs 丨 stands for Modified (dlfled), Exclusive, Shared, Invalid, which are the four possible states or status values of a cache line in the cache memory. [0008] A general method for maintaining the consistency of cache memory with peeping is to ensure that the processor has unique access to the line before the processor writes data to the line. This method is generally called the write invalidation protocol; because at the time of writing, this method invalidates the * copy of any related cache f in other cache memories. Requires unique access to ensure that the place where the write is made, when the device writes data, there are no other readable or writable copies of the cache line written. M00 9] In order to invalidate other copies of the cache line in other cache memory, the invalidating processor will obtain access to the bus and provide the cache line to be invalidated on the bus. Address. Basing his cache 忆 The memory will peek at the bus ’and check if it currently caches the address \ If so, other cache memories will change the state of the cache line to beneficial. [0010] In addition, each cache memory will also be broken by peeking whether it has a modified cache that is being read by another processor. J: Right, the cache memory is modified by caching The line is written into memory or the modified cache line is passed to the requesting processor, or both to provide the modified cache line. The operation of reading the cache line may allow 4 caches & 1226681. V. Description of the invention (4) Enjoying 'or' it may require other cache memory to invalidate the cache line 0 [0 〇11] processing The processor's cache memory is usually hierarchical cache memory. For example, a processor may have a first-level (L1) cache and a second-level (L2) cache. The L1 cache is closer to the processor's computing elements than the L2 cache and can transfer data to the computing elements faster than the L2 cache. Furthermore, the cache memory can be further divided into separate instruction cache memory and data cache memory, which are used to cache instructions and data, respectively.

[〇 〇 1 2] In the processor's cache memory hierarchy, various cache memories will transfer each other's cache line. For example, when the cache address misses the L i cache, if the miss cache line exists in L2, L 丨 loads the miss cache line from the L2 cache memory of the processor. Furthermore, if the L1 cache needs to replace a valid cache line with a newer cache line, the L1 cache memory will move the replaced cache line to the L2 cache without changing Write the cache line to system memory. This practice is typically used to write back cached configurations.

[0 0 1 3] It may take several processor clock cycles to transfer the cache line between the two cache memories of the processor. There may be several reasons for this. One reason is that cache memory usually includes a local memory with multiple stages to process an operation in a -clock cycle, requiring multiple clock cycles. In addition, the cache memory Erxi: Pass-through cache memory, so in the first pass pipeline (commonly referred to as the inquiry pass) _ ’will get the state of the relevant cache line. Pick up

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ί = Pass the pipeline one or more times again, depending on the status obtained, 1. Take a memory, or read the amount of money that was not obtained during the query pass, V and g 'on the processor's integrated circuit The cache memory may be quite far apart from each other, so additional clock cycles are needed for the long roar path of the car, and / or signals generated by the transmission delay of many logic gates. [0012] For example, suppose the processor stores a new cache line in L1 and L1, and forces L1 to replace a modified cache line. l 1 moves the modified cache line to be fetched to the L2 cache on the processor. L1, its! T line ° sells the removed cache line, and stores a buffer between the two cache memories. L1 will inform L2 of this removal action, then read the removed cache with the removed cache line center = write this line into itself. [0015] As long as the cache memory does not peek on the bus to conflict with the address of the removed cache line during the removal (ie, its address is the same as the address of the removed cache line) , The previous approach is fine. However, if "conflicting operations are observed during the" removal operation in progress ", it will cause obvious problems in design" and must be resolved. For example, if the job being viewed is to be read and the cache line in the transfer contains modification data that has not yet been written to memory, which of the two cache memories should it be for the cache line? Data to spy on the bus? Which cache-fetch memory will have this removed cache line to update its shape? [0016] The conventional method for this problem is to cancel or kill the operation in the transfer. However, this approach has negative effects. For cancelled

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V. Description of the invention (6) = operation during transfer. This method will increase the cache memory and complexity. For example, in the front shot, the new cache line in the L1 cache memory tC overwrites the action of the removed cache line until L2 tells i f to proceed to the ground. The longer U waits, the cancellation and / or retry should be, the more complicated the whole process is. In addition, the increased latency may affect performance. In addition, between a cache memory, due to the need to fetch ^ handshaking), if the two cache memory blocks are spaced apart and shake hands,

If the distance is too long, the signals communicating with each other may be quite long, and there may be significant delay, which may cause a critical timing path. I

[0017] Therefore, what is needed is a kind of cache memory, which can handle the impact caused by the conflict between the operation of the external peep and the operation in the branch, and does not cancel the operation in the branch. [Summary of the Invention] [0018] This conflict is peeped. For the purpose described, a feature of the present invention is to provide a pass-through cache. The present invention proposes a cache memory that conflicts with operations in a transfer. The operation in the branch needs to be cancelled. Because it can detect an external fetch memory. The cache memory includes a query to receive a query between time and an operation. This operation transfers one cache line from one micro-cache to another. . The cache memory also includes control logic to detect a peeping query between the peeping address and the cache line. The fetching memory and an array of peeping addresses are used for

And here, for a kind of microprocessing, a peek and mark processor, a peeking series, coupled with a single site, internally processes multiple arrays in the device, and uses the quick query packet in the bundle to connect to the label & amp Rush

Page 12 1228681 V. Description of Invention (7) The control logic will complete the end pass by updating the tag array when a conflict is detected, without canceling the end pass.

[0019] On the other hand, a feature of the present invention is to provide a second-order (L2) cache memory in the microprocessor, which can process a peep operation internally, and responds to one of the microprocessor's external Received by the operation peeped on the bus, and its address conflicts with the transfer operation of a cache line between the L2 cache memory in the microprocessor and another cache memory, and the L2 The cache does not need to cancel the transfer operation. The L2 cache memory includes a peep conflict logic, which generates a peep flag state based on detecting an address conflict between the peep operation and the operation in the branch, and detecting an address conflict between the peep operation and the operation in the branch. The L2 cache memory also includes a peep action logic, which is coupled to the peep conflict logic to generate a peep action based on the status of the peep marker. The peeking operation updates the cache memory consistency state after updating one of the cache lines' cache memory consistency status to the transfer in-progress mark operation during the transfer operation. [0020] In another aspect, a feature of the present invention is to provide a method for enabling a first cache memory to internally process a peep operation, the peep operation having a second cache memory and a first cache. The relevant cache line in the memory-to-memory transfer, the first cache memory does not need to cancel the operation in the transfer. The method includes querying the first cache memory and marking the array to obtain the first state of the cache line by the transfer operation; querying the mark array to obtain the first line of the cache line by the peek operation. Two states; and after interrogating the second state, the tag array is updated with the second state of the cache line by the transition operation. This method also includes

1228681 V. Description of the invention (8) After the occurrence of the state of sadness and suddenness, the column is used to avoid the [0 02 1] conflict result cycle time sequence, and the cache operation of the cache is performed. The processing [0 022] and the attached picture and the address between the operations in the transfer peek through this method. This method also includes the update in the third state of the exemption, the fourth from the cache line Xiao Xigu The state update flag array does not cancel the operation in the transition. The full advantage of ΛΙ / is that ‘cache memory can peep == :: It can avoid the need to integrate the processor's integrated power Γ between the body: Ϊ: communication related issues. The conventional method needs to be moved; operation two, in order to cancel the address and an external peeping operation, the operation is different. In addition, the present invention can also reduce the complexity of other cache memories in the initial transfer memory. Other features and advantages of the present invention will become more apparent after cooperating with the following description. [Embodiment] [0 0 3 0] Referring now to FIG. I, it is a block diagram of a cache memory hierarchy of the microprocessor 100 according to the present invention. [0 0 3 1] The cache memory level of the microprocessor 100 includes a first-order instruction (LI I) cache memory 102, a first-order data (lid) cache memory 104, and Second level (L2) cache memory 106. LI I 102 and L1D 104 cache instructions and data respectively, while L2 cache memory 106 caches instructions and data to reduce the time required for microprocessor 100 to fetch instructions and data. L2 cache 1 06 is in the system's memory hierarchy, which is located between system memory and L1I 102 and L1D 104. L1I 102, L1D 104, and L2 cache

1228681 V. Description of the invention (9) Memory 1 06 is coupled together. The cache lines are transferred between L 1 I 1 02 and L2 cache memory 1 06, and the cache lines are transferred between L1D 104 and L2 cache memory 106. For example, L1 I 1 02 and LI D 1 04 will move the cache line to L2 cache memory 106 or load the cache line from L2 cache memory 106. [0032] The microprocessor 100 further includes a bus interface unit 108, which is coupled to the L1I 102, the L1D 104, and the L2 cache memory 106. The bus interface unit 108 taps the cache memory 102-106 and other functional blocks in the microprocessor 100 to a processor bus 112. The processor bus 11 2 couples the microprocessor 100 to other system components, such as other microprocessors, I / 0 devices, and memory components, such as system memory. The microprocessor 100 and other devices execute the bus operations on the processor bus 丨 2 to perform data transfer and maintain consistency between cache memories. [0033] The bus interface unit 108 will respond from the microprocessor [0 0 3 4] In addition, the 'bus interface unit 1' will monitor the processor bus

The request of the function block (such as cache memory 102-106) in 100 on page 15 will generate a job on the processor bus 丨 12. For example, if L2 cache memory 106 receives a request that misses L2 cache memory 106 from another block in microprocessor 100, L2 cache memory 106 will request confluence The interface unit 1 08 starts the operation on the processor bus 丨 丨 2 to read the relevant error cache line from the processor bus 1 ^ 2. Similarly, if the cache memory needs to write a cache line into the system memory, the L2 cache memory 106 will request the processor bus 112 to generate a buffer on the processor bus 112 to cache this cache. Line write processor bus 丨 i 2. 1228681 V. Description of invention (ίο) —---- Assign jobs on row 112 and reflect these jobs to cache memory 102-106. In particular, if the bus interface unit 108 finds one or more invalidated read or write operations on the processor to the bus 112, the bus interface unit 108 will perform a peep operation request (sn〇〇p 〇peatiQn request), reflecting that the job gave cache memory 102-106. The cache memory hierarchy of the microprocessor 100 of FIG. 1 is a representative microprocessor using the present invention; however, the present invention is not limited to the embodiment of FIG. More precisely, the present invention can be applied to any kind of cache memory hierarchy configuration, as long as two of the cache memories transfer each other's data, and during the transfer (that is, in-f light )), The cache can receive peep operations whose addresses conflict. Advantageously, if a peek operation generated by a job on the processor bus 11 2 conflicts with an operation in a transfer, the L2 cache memory of the present invention 106 can be internally It will be processed without canceling the operation in the branch as is customary. [0036] Reference is now made to FIG. 2, which is a block diagram illustrating the L2 cache memory 106 of FIG. 1 according to the present invention.

[0 0 3 7] The L 2 cache memory 106 includes a data array 208. The data array 208 includes an array of storage elements for storing cache lines. The data array 208 receives a memory address 2 12 as an index of the data array 208 to select a storage element in the array. The data array 2 08 outputs the cache line selected at the address 2 1 2 to the data output terminal 2 1 8. In particular, the data array 208 is stored in the cache line transferred between the L 2 cache memory 106 and the L1 cache memory 10 2-104.

IEMI Page 16 1228681 V. Description of the Invention (11) [0 0 3 8] L 2 Cache § Memory 106 also includes a tag array 206. The label array 206 includes a storage element array ′ for storing relevant status information of the cache lines stored in the data array 208 ′. This status information includes cache consistency status information. In one embodiment, the cache memory consistency information includes M E S I status information or status. The tag array 2 06 will also receive the address 2 12 as the index of the tag array 2 06 to select a storage element in the array. The marker array 2 0 6 outputs the selected state at the address 2 1 2 in the state wheel output 21 6.

[0 0 39] The L2 cache memory 106 further includes control logic 202, which is consumed by the data array 208 and the tag array 206. The control logic 202 is also coupled to the LI I 102, L1 D 104, and the bus interface unit log, receives an operation request therefrom, and generates a response. The control logic 202 is used to control the operation of the L2 cache memory 106. The following description will be described in more detail in conjunction with the other drawings. 0 [0 0 4 0] The L2 cache memory 10 is multiple times. Multi-pass cache. That is, most operations need to be completed through [2 cache memory 1 06 two or more times. When the L2 cache memory 106 is passed for the first time, the tag status 216 is read from the tag array 206, and in the case of reading classes and operations, it is also possible to read data 21 8 from the data array 208. First, the first person through the L 2 cache 纟 memory body 106 is also called query pass (query PaS_S \, because it will ask the tag array 206 about the status of the cache line 216., the first person and any place The required subsequent pass of the L2 cache memory is the finish pass, and because it updates the cache in the tag array 206, ..., 'two, it is also called an action pass or Update pass

1228681 V. Description of the invention (12) Column 208 may write data into the data array 208 under the circumstance that the type 1 type operation is stolen. The end of peeping nose movement is called peeping movement. Chuan 4 [=]: 2 cache memories like 1 " include-peep action queue Λ, 2 / to control logic 2 ° 2. The peep action queue 2 (34 stores the peep action performed by U = a self memory 106. The operation of the peep action queue 204 will be described in more detail below with reference to the remaining drawings. [0042] Now referring to FIG. 3, which is a more detailed diagram of the control logic 202 of FIG. 2 according to the present invention, such as a block diagram of the cache memory 106. The dagger 2 cache memory 106 of FIG. 3 includes the control logic 202 of FIG. 2 , Peep action queue 204, tag array 206, and data array 208. In the embodiment of FIG. 3, the L2 cache memory 106 pipeline includes four phases, labeled _phase 322, K-phase 324 L-phase 326 and M-phase 328. The tag array 206 and the data array 208 each include four stages j to μ 3 2 2-3 2 8. [0043] The control logic 202 includes an arbiter 3o. 2. The arbiter 302 receives a plurality of requester inputs requesting access to the L2 cache memory 106. One of the requesters is a peep inquiry 3 3 6. The bus interface unit of FIG. 1 will respond. The external processor bus in FIG. 1 is peeked from the job and generates a peek query 3 3 6 request. [0044] Another set of requester packages New operation 334. The new operation 334 request passes the query including the L2 cache memory 106 operation, but does not include the peep query 336 for peeping nose. In one embodiment, the new operation includes a load operation from L1D 104, Load operation from Lu 102, move-out operation from L1D 104, move-out operation from Lu 102, and storage operation from L1D 104. L1D load operation includes from [2 cache memory

Page 18 1228681 V. Description of the invention (13) Data transfer from 106 to L1D 104. The L1I load operation includes data transfer from L2 cache memory 106 to L1I 102. The L1D shift-out operation includes a cache line shift from the lid 104 to the L2 cache memory 106. The LI I shift-out operation includes a cache line shift from L1I 102 to L2 cache memory 106. L1D storage operations include data transfer from L1 D 1 04 to L2 cache memory 106. [0045] Another requester is peep action 338. When a peep inquiry reaches the bottom of the L2 cache § memory body 106 pipeline, the peep action generation logic 314 described below will respond to generate a peep action 338. [0046] Another set of requesters includes an end operation 332. The end operation 332 includes the end of operation of the L2 cache memory 106, but does not include the peep action 338 of peeping nose. In one embodiment, the end operation 332 includes the end of L1 loading, the end of L1 removal, the end of L1 storage, and the removal of L2. L1 load end includes the end of the L1D or L1I load operation. The end of L1 removal includes the end of L1D or L1I removal. The end of L1 storage includes the end of the L1D storage operation. L2 removal includes L2 cache memory 106 responding to a write type operation that writes to L2 cache $ memory body 106, and sacrifice cache configured to be replaced by L2 cache memory 106 Line to move to system memory. [0047] If a peep query with a conflicting address is entered into the 12 cache memory 106 pipeline after the query of an operation passes but before the last end of the operation passes, the operation is in transition. A peek operation may also be a transition operation. For example, a second peek query with a conflicting address is entered into the L2 cache memory 106 pipeline after the first peek query but before the first peek action. ~

Page 19 1228681 V. Description of the invention (14) [0 048] The arbiter 302 will select one of the requesters 3 3 2-3 3 8 according to a priority order to access the tag array 2 0 6 and the data array 2 〇8. That is, the arbiter 302 selects one of the requesters 332-338 and transmits its memory address 2 1 2 to the tag array 206 and the data array 208. In addition, if the claimants 332-338 that have won the arbitration have passed, they will transmit their updated state 342 or transitioning state 342 to the tag array 206. The update status 3 4 2 indicates the cache memory consistency status of the cache line specified by the address array 2 2 in the tag array 2 06 that is to be updated after a transfer operation. The transition state ’or update state is included in each end operation M 2 and

Depending on action 338. Finally, if the claimant 332-338 who won the arbitration is a clear type operation, he will provide his data to the data in data signal 34 4, line 208. f The operation type of the arbiter is specified in the operation type signal. The different type 346 specifies the u operations listed in Table 1 below: In-embodiment +, the priority order of the operation types used by the arbiter 302 is determined in advance, as shown in Table 1 below. 1 · Peep inquiry

2 · L 1 loading completed \ 3. L2 move out | —End of calculation during transfer passed 4 · L 1 move complete 丨 5 · L1 save complete 丨 6 · Peep action / 7 · L1D load \

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8. L1I load I 9 · LID move out 丨 —new operation i〇 · L1I move out I 11 · L 1 D Store / Table 1 Low-optimal = shown in Table 1 above, peep action 338 is the best to end the pass

The order is lower ^ Φ ′, that is, the peep action 338 has a higher order than the ^ operation 332 and the peep action 338 that end the operation 332, and has a lower priority than any new operation 334. To 2nd 5: Control, 202 also includes a calculation pipeline 304, which consumes ° The calculation official line 304 includes four stages of storage elements, and the calculation line selected by the t cutter 302 passes through the L2 cache memory 106. Phases of the pipeline f array 206 and data array 208 are stored at the corresponding stage. The parent stage of the 笞 line 3 0 4 stores a memory address 3 5 β, an operation type 364, and a transition state 362 or an update state 362. Memory address 35 (, 圮 memory address 212 down the pipeline. Operation type 364 is from the operation sea

Type 346 goes down the official line. The transitioning state 362 goes down the pipeline from the update state 342. [0051] The control logic 202 also includes a plurality of address comparators 306, which are lightly connected to the arithmetic pipeline 304. The address comparator 306 receives a memory address 3 5 6 from each stage of the arithmetic pipeline 3 04. In addition, the address comparator 3 06 will receive the operation currently being arbitrated by the arbiter 3 2 to access the L 2 cache memory 106.

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V. Invention Description (16) The memory address is 3 5 2. Finally, the address comparator 306 also receives a victim address 354. Sacrifice address 354 is the memory address of the associated cache line of an L1 shift-out operation (that is, an operation that configures a new cache line). The address comparator 3 06 compares the various addresses received to determine whether any address conflict has occurred between a peek query 336 address and any other address received by the address comparator 3 06, as follows Table 2 gives a more detailed explanation. The address comparator 306 uses an address conflict signal 348 to indicate that an address conflict has occurred. In one embodiment, the 'address collision occurs when the most significant bit of the peep address coincides with the address of the computation in the branch that needs to specify a cache line.

[0052] The control logic 202 also includes a peep conflict logic 308, which

Connected to the address comparator 306. Peep collision logic 308 receives an address conflict signal 3 4 8. In addition, the peep conflict logic 3 08 will receive the tag status 2 16 from the tag array 2 06 'from each stage of the computing pipeline 3 0 4 and receive the transition status value 362, and from the arbiter 302 to accept the arbitration to The operation of accessing the L2 cache memory 106 is in the state of transition 366. Furthermore, the peep conflict logic 308 will receive the operation type 364 from each stage of the operation pipeline 304, and from the operation type 368 that accepts the arbiter 302 to access the L2 cache memory 106. . Finally, the "peep conflict logic 308" will receive a sacrificing valid signal 3 72, which shows whether the sacrificing memory address 354 is valid, that is, whether the victim of a configuration action is valid. [0053] The control logic 202 also includes a peep flag state 312, which is coupled to the peep conflict logic 308. The peep conflict logic 308 generates a peep flag state 31 2 in response to various inputs received. The peep marker status 3 1 2 is used to generate peep actions and bus actions, as described below

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1228681 V. Description of the invention (17) The equation in Table 2 below describes how the peep conflict logic 3 08 generates the peep tag status 312, which is labeled as EsnpTagstatus —M [1: 0]. £ SnpTagSta1u $ _M [l: 0] = ESnp_M & LlLdFui.L · & L2MEqL_P? 2b 00: ESi9 > _M & LlLiFm.K & L2MEqK_P 7 2b 00: ESi5 > _M & Remq L2 : Κΐφ_Μ & LlStFin_L & L2MEqL_P? LlStFinWrStatas_L [l: 0]: ES ^ p_M & LlStFinJK. &Amp; L2MEqK_P? LlSffmWiSUta5_K [l: 0]: ESrv oneM & LqFF 0]: Κΐφ_Μ & LlCOiinLast_L & L2MEqL_P 7 LlC〇rmWiStatus_L [l: 0]: Εϊφ_Μ & LlC〇riaL ^ st_K & L2MEqK ^ P? LlCOFiaVftStajj_K [l: 0C] &Remp; ? • UCOFinWiStatii_P [l: 0]:

ESrq > VicCoilEA2iy_M? 2 * b00: ESti > _M & LlCOFinReq ^ P & UCOFinVicVId_P & L2COEqM_P? 2 ^ 00: ESnp_M & ESn > Fin_L & ESM00 +? PMqL ^ Fin.K & L2MEqK_P? 2 * b00: ESnp_M & ESn > Fiifteq__P & ES i ^ > FinEqM_P? 2¾ 00

HilSUiujJI [l: 0]; Table 2 [0054] Signals ending with _J, _K, _L, or _ 乂 correspond to J-phase 322, K-phase 324, L- of L2 cache memory 106 pipeline Stage 32 $ 6 or M stage 3 28. Signals ending with _P are not specific. The status values in Table 2 correspond to the following MESI status values: 2 'bll = modified; 2' 1) 10 unique; 2 'b01 = shared; 2' b00 = invalid. The signals in Table 2 are defined as follows. [00 5 5] Esnp_M is one of the operation type signals 364, and if true, it means that there is an external peep query type operation at M-stage 328 1228681

[0056] L2MEqL_P is one of the address conflict signals 348, and if true, it represents the memory address 356 of the operation or action in the M-phase 328, and the memory address of the operation in the L-phase 326 356 is the same. L2MEqK — P is one of the address conflict signals 348, and if true, it indicates that the memory address 356 of the operation or action in the M-phase 328 is the same as the memory address 356 of the operation in the ^ phase 324. LiLdF in-L is one of the operation type signals 36 4 and if true, it means that a u-loaded end type operation is located in the L-phase 326. LILdF in —K is one of the operation type signals 364, and if true, it means that there is a u-load end type operation located in 1 (-stage 324. 1 ^ 11 (1 『丨 111 ^ 9 —? Is arbitration One of the operation type signals 368, and if true, it means that a u-load end type operation is receiving arbiter 302 arbitration to access ^ cache & body 106 ° LlLdFinEqM — P is the address One of the conflict signals 348, and if true, it means that an arbitration L1 loads the memory address 352 of the end operation, and the memory address 3 56 of the operation in M- = segment 328 is the same. UStFin — L is the operation type One of the signals 3 6 4 and if it is true, it means that there is an operation of ending type Li in L-phase 326. L1StFin-κ is one of the transport signals 364, and if it is true, it means that there is one The operation of u storage type is located in K-stage 324. L1StFinReq_p is one of the arbitration operation type signal 368, and if true, it means that an operation of u storage type is receiving arbiter 302 arbitration to store Take ^ cache = body 106 QLlSt-FinEqM-P is one of address conflict signals 348 , And: is true, it means that an arbitration L1 stores the memory address M2 right after the operation is completed

1228681 Invention description (19) The memory address 356 of the operation in M-stage 328 is the same. LlStFinWrStatus—L [1: 0] is one of the status signals 362 in the transition, and displays the cache memory consistency status value of the tag array 2 0 6 to be updated in the L-phase 326 completion operation of the L1 storage. LlStFinWrStatus—K [l: 0] is one of the transition status signals 362, and displays the cache memory consistency status value of the tag array 206 to be updated when the L1 storage end operation in K-phase 324 is updated. LIStFinWrStatus_P [1: 0] is one of the status signal 366 = in the arbitration transfer, and it shows that the L1 storage that has been accepted by the arbiter 302 is finished. The cache of the tag array 2 0 6 needs to update the consistency status value. . LICOFi n Last-L is one of the different types of signals 364, and if true, it means that the last pass of an L1 removal end type operation is located in the [-stage 326]. LICOFinLast — K is one of the operation type signals 364, and if true, it means that the final pass of an L1 removal end type operation is located in K-phase 324. LICOFinReq_P is one of the arbitration operation type signals 368, and if it is true, it means that there is an arbitration of the arbiter 302 of the removal type end operation type. LICOFinEqM — P is one of the address conflict signals 348, and if it is true, it means an arbitration [丨 removes the memory address 352 of the end operation, which is the same as the memory address 356 of the operation in the M-phase 328 ~ the same . LlCOFinVicVldd —P is the sacrifice valid signal 3 72. LICOFi nWr Status — L [1: 〇] is one of the status signals 362 in the transition, and it shows the cache memory consistency status value of the § Array 2 0 6 to be updated in the L-phase 326. . LlCOFinWrStatus — K [1 ·· 〇] is 1228681 in the transition status signal 362

One, and it shows the cache memory consistency status value of the tag array 2 0 6 to be updated when the L1 removal end operation in the K-phase 324 is completed. LlCOFinWrStatus — P [1: 〇] is one of the status signals in the arbitration transfer, and it shows that the L1 shifted out of the arbiter 302 arbitration is finished and the cache memory consistency status value of the tag array 206 is updated. 1 ^ 2 (: (^ 〇 »« —? Is one of the address conflict signals 34 8 and if true, it means that L1 is moved out of the configuration memory address 354, which is the same as that in M-stage 328 Jiyi's ship address 356 is the same. ESnpFin —L is one of the operation type signals 364, and if true, it means that a peep end (or peep action) type operation is located in L-phase 326. ESnpF in —K is One of the operation type signals 364, and if true, it indicates that a peep end (or peep action) type operation is located in K-stage 3 24. ESnpF inReq_p is one of the arbitration operation type signals 368, and if it is True, it means that a peep action type operation is receiving arbiter 302 arbitration to access [2 cache memory 106 ° ESnpFinEqM —P is one of the address conflict signals 348, and if true, it means a The memory address 352 at the end of the arbitration peep operation is the same as the memory address 356 of the operation in the ^^^ stage 328. [00 57] HitStatus — M [1: 0] is the flag shape of the flag array 20 6 although it outputs 216 As can be seen from the equation in Table 2, If there is no address conflict between the operations, the default value of peeking flag status 3 丨 2 (represented by EsnpTagStatuS-M [l: 0] in Table 2) is marked off, and it is marked as HitStatus—M [1 ·· 0 ]To represent. ~

[005 8] EsnpVicCol lEarly-M is a signal generated inside the peep conflict logic 308, which is used to generate EsnpTagStatus_M 1228681 V. Description of the invention (21) [1: 0] ° ESnpVicC0llEarly-M If true, it means asking It is located in M-stage 328, and when the peep question first looks at Lent or L-step, it and a L1 move out of Sacrifice-step Hikaruyama 1 to fly the effective sacrifice address 354 to produce a red dog, and the L1 The removed victim will be overwritten by the outgoing operation that it ended arbitrating through the positive acceptor 302. When the peep query bit stage 324, the peep conflict logic 308 sends the item (ESnp κ &,

LlC〇FinReq_P & L1C0FinVicVld —p & L2c〇EqK —ρ) is stored in a register to generate £ 5111 ^ 4 (: 〇11 £ 31 ~ 4 ^ !, the latter is located at L-stage 326 In the middle, the temporary value and the item usn ^ &

LlCOFinReq_P & LlCOFinVicVld_P & L2c〇EqL p) edit the operation of "or", and then store the result in a register and when the query reaches the M-stage 328, output this second temporary operation One of the type signals 364, and if true, it means that the peep query type operation is located in the K-phase 324. ESnP_L is one of the operation type signals 364, and if true, it means that an external peep inquiry type operation is located in the L-phase 326. L2COEqK_P is one of the address conflict signals 348, and if it is true, it means that! ^ 2 shifts out the allocation sacrifice memory address 354, which is the same as the memory address 356 of the operation in K-phase 324. 1 ^ 2 (: 0 £ 91 ^ —? Is one of the address conflict signals 34 8 and if true, it means that L 2 is moved out of the configuration to sacrifice memory address 3 5 4 and disk L-stage 3 2 ^ Φ eve The calculated memory address 356 is the same.… [0 0 5 9] in Nuchuan It can be observed from Table 2 that the status of the peek query 21 6 at the bottom of the L 2 cache memory 1 06 pipeline, and in the pipeline Or accepting arbitration to pass the end of the operation of the access pipeline to the transitioning states 362 and 366,

Page 27 1228681

V. Description of the Invention (22) are all factors that affect the peep mark state 312. Advantageously, the present invention uses the intermediate peek mark state 312 to generate a peep action to update the cache memory consistency of the relevant cache line of the conflicting address and generate a bus action in response to the processing of FIG. The external peeking operation on the device bus 112 is described below, thereby avoiding the cancellation of operations during transfer, as in the conventional method. [0060] The control logic 202 further includes a peep motion generation logic 314,

It is coupled to the peek mark state 312. The peep action generation logic 314 generates a peep action based on the peep flag state 3 1 2. The peeping action generated by the peeping action generating logic 314 is stored in the peeping action queue 204 of FIG. 2 to be transmitted to the arbiter 302 via the peeping action signal 338. The peep action consists of two parts, as shown in Figure 4. [0 〇 6 1] Referring now to FIG. 4, it is a block diagram of the peep action queue 2 0 4 of FIG. 2 according to the present invention. The peep action queue 2 in FIG. 4 is filled with example values for easy explanation. The peep action queue 204 includes a storage element queue. Each storage element includes a valid bit 402, a memory address 404, a peek update status bit 406, and a provided data bit 408.

[0 0 6 2] The effective bit 4 2 indicates that the item in the peep action queue 2 04 includes an effective peep action. Once a valid item in the peep action queue 204 is output to the arbiter 302 and wins arbitration, the item will be marked as invalid until a new valid peep action is stored in the item. Address 4 0 4 specifies the memory address of the cache line associated with the peek operation. Address 4 0 4 is provided by M-stage 328 through address 356 of FIG. 3. The peep action updates the status of the cache line specified by address 404 in the tag array 206 to

Page 28

1228681 V. Description of the invention (23) Peek update status 4 0 6 Stored cache memory consistency status. In one embodiment, the peek update status 406 includes one of four MESI status values. The provided data bit 408 specifies whether the peep action in this item will provide data from the data array 208, such as the modification cache line required for external peek operations on the processor bus 112. The peek update status 406 and the provided data bit 408 are generated as described in Table 3 below. [0063] Referring again to FIG. 3, the equation in Table 3 below describes how the peep action generation logic 314 generates the peep action stored in the peep action 204.

ESnpFiuLd = (ESrp_M & ESupTagStatuifl]) 丨 (EiBp_M & ES if > TagStatis [p []); ESnpPxoviieDAU = ESnp.M & ES χφΤ ^ Uti $ [1] & ES ryTagS Utas〇Q] As = 110;

EsnpUpdateState P] * ESnp.M & S lOK & ((ES apTacS Ulos [1] & -ESn > Ta «SWaj [OD | // ΕΛ» (-ESnpT4gSUias [l] & ESapT4eSt »tas () D : D); // S ft Table 3 [00 64] If ESnpFinLd is true, it will instruct the peep action queue 204 to load the end of the peep pass generated by the peep action generation logic 314, or the peep action. It can be seen that the peep action queue 204 will load the peep action when the peep flag state 312 is modified, exclusive, or shared, rather than when the peep flag § self state 31 2 is invalid. [0065] From the table 3 It can be seen that only when the relevant cache line is modified

1228681 Description of Invention (24) The data will only be provided when peeping. [0 0 6 6] According to Table 3, if the relevant cache line is already in the exclusive or shared state, the L2 cache memory 106 will allow the cache line to be shared. In another embodiment, the equation for the peek update status 4 of FIG. 4 is: ESnpUdpdateStatus = 2'bOO. That is, the L2 cache memory 106 will invalidate the cache line related to a peep conflict, and will not allow the cache line to be shared. [00 67] ShOK is a signal from the graphics processor bus 112, which indicates that the external peek operation allows the microprocessor 丨 〇 〇

The line remains in a shared state, and is used for peeping operations such as instruction fetching rather than invalidation. [0068] The control logic 102 further includes a bus action generating logic 31 6 ′, which is coupled to the peek mark state 3 2 and the bus interface unit 108 of FIG. 1. The bus action generating logic 316 will generate a bus action 3 7 4 according to the peek mark state 312 for transmission to the bus interface unit 1 q 8. The bus action 3 7 4 instructs the bus interface unit 108 to respond to an external peep operation on the processor bus U2 which will cause it to generate a peep operation (the peep flag state 312 is thus generated).

[0069] The control logic 202 also includes an end pass generation logic gig, which is consumed by the tag array 206 and the arithmetic pipeline 304. The end pass generation logic 318 generates an end pass or end action of a new operation 334 (i.e., a non-peek operation). In one embodiment, the end pass generation logic 318 generates [load end, L1 removal end, L1 storage end, and L2 removal pass or operation. The end operation 3 3 2 includes an update status for updating the marker array 2 06,

1228681

It is used to retrieve the marker array 206 and the rough land π. 1κ 次 Mr from # 枓 Array 2 08 one of the memory address, the nose type and the shell material (right this knot to the east, and also to the east, you have to write the action), and in the When the end of the difference was selected by the arbitration 1 § 3 02, all the items mentioned above were provided by Kuwei 342, 212, 346, and 344, respectively. The control logic 202 also includes an end action, Tsai Lie Chuan, which is connected to the end pass generation logic 318. The end action is deleted: the end action is received by the generating logic 318, and the end action ^ bundle is stored and transmitted to the arbiter 3202 via the end signal 332.

[007 1] Referring now to FIG. 5, it is shown in accordance with the present invention that for the punching dog between the peep operation and the operation in the transition generated by the peeped operation, the L2 cache memory 1 in FIG. Operation flow chart for internal processing. The process starts at block 502. # [0072] In block 502, the arbiter 302 of FIG. 3 selects the new operation 3 34 of FIG. 3 so that it can access the L2 cache memory 106 and enters the J-stage 322 of the pipeline of FIG. 3. That is, the memory address 212 of the new operation 334 will be sent to the tag array 206, the data array 208, and the operation pipeline 3 04 of FIG. 3, and the operation type 346 of the new operation 334 will be transmitted to the operation pipeline 3. 〇4. Flow continues to block 504. [0073] In block 504, the arbiter 302 receives the peep query operation 3 3 6 of FIG. 3 from the bus interface unit 10 8 of FIG. 1, and the peek query operation 3 3 6 accepts arbitration to access the L2 cache. Memory 1 06. The bus interface unit 108 responds to the external operation peeped on the processor bus 11 2 of FIG. 1, and generates a peep inquiry 3 3 6. The flow continues to block 506. [0074] In block 506, the new operation 334 reaches the bottom of the pipeline (also

1228681 V. Description of the invention (26) That is, the M-stage 328 is reached, and the mark state 216 is obtained from the mark array 206. Since the conflicting peep inquiry entered the L2 cache memory 106 pipeline before the end of the new operation 334, the new operation 334 is a branch-in operation at this time. End-of-pass generation logic 3 1 8 generates an end-of-transition operation based on the obtained flag state 216 and operation type 364, which includes updating the state of the flag array 206 in transition. The process continues to block 5 0 8 〇

[0075] In block 508, the end action queue 382 transmits the end of the branch operation generated in block 506 to the arbiter 302 through 332, and the branch operation arbitrates through the arbiter 302. Flow continues to block 512. [0076] In block 512, the peek query reaches M-stage 328. The peep conflict logic 308 detects an address conflict between a peep operation and an operation in a branch. Flow continues to block 514. [0077] In block 514, the peep conflict logic 3008 generates the peep marker state 31 based on the peek query received from the marker array 2 06 and the marker state 2 1 6 and the relevant transition in-operation state 3 6 2 calculated in the transition. 2, as described in Table 2 above. Flow continues to block 51 6.

[0079] In block 516, the peep conflict logic 308 generates a peep action 3 3 8 based on the peep target state 31 2 ′ obtained in Table 3 to store in the peep action queue 204. The peep action 338 includes a peek update status to update the tag array 206. The flow proceeds to block 5 1 8. [0079] In block 518, the peep action 338 generated in block 516 is arbitrated by the arbiter 302 to access the L2 cache memory 106. flow

Page 32 1228681 V. Description of Invention (27) The process proceeds to block 522. [0 08 0] In block 522, the end of the branch operation is updated by updating the flag array 2 06 with the branch state in the state signal 3 4 2. In addition, if the in-transition operation is a write-type operation, data is written into the data array 208 via the data signal 3 44. Flow continues to block 524. [0081] In block 524, the peek action 338 updates the tag array 206 with the peek update status generated in block 516. In addition, if the providing data field 408 of the peep action 338 indicates that the peep operation is to provide data to an external peek operation on the processor bus 112, the peep action 338 obtains data from the data array 208 via the data signal 218 to provide to the bus Row interface unit 108. The flow proceeds to block 5 2 6. [0082] In block 526, the bus action generation logic 316 generates a bus action 374 based on the peek mark state 3 1 2. In one embodiment, block 526 occurs substantially simultaneously with block 516. Flow continues to block 528. [0083] In block 528, the bus interface unit 108 uses the bus action 3 7 4 generated during the block 526 to repeat the external peeking operation on the processor bus 112, which may include providing the block Information obtained during 524. The process ends at block 5 2 8. [0084] In order to understand the present invention, various timing diagrams will be described below. In order to understand the present invention more completely, the operation timing diagram of the conventional L2 cache memory is discussed below. [0 0 8 5] Referring now to FIG. 6, it is a related art timing diagram showing that the conventional L2 cache memory cancels the operation in the transfer that conflicts with a peep operation.

1228681 V. Description of the invention, the implementation of column f assumes that the conventional L2 cache memory has four stages of pipelines, which are similar to the stages of L2 cache memory 106 in Fig. 3. This example also assumes that L2 cache memory is a multi-pass cache memory. The timing diagram includes nine rows corresponding to nine consecutive clock cycles and four pipeline stages (called j, K, L, and 趵) corresponding to the conventional u cache memory. Each item in the diagram System, showing specific pipeline stages during a specific clock cycle

[0086] In the example of FIG. 6, the conventional u cache memory is received—a storage operation with a memory address A, which is caused by another conventional microprocessor: the memory (such as the L1 cache memory) Get started. When the storage operation still advances, it is followed by a peep operation = with the same memory address A, so there will be a conflict between the storage operation and the peek operation. In this example, the peep operation is invalidated peep operation, that is, the external peek operation of the processor bus ^ is invalidated operation t, and the person invalidated invalidated operation. R ^ [0087] in the clock cycle! During this period, the query of the storage operation passed (indicated by StQ eight) into the pipeline stage; During the clock cycle 2, the peep 2 query is passed (indicated by SnpQ A). After the query is stored, it enters: During the clock cycle 3, the two operations go down the pipeline to the next stage. 0 [0 0 8 8 ] In the 4th part of the clock cycle, and the cache memory will provide a fixed cache line. If it does not pass the end of the peep, it will continue,

At the same time, the storage query reaches the bottom of the pipeline. A unique flag state conflicts with the query pointed to by address A. The cache line at address A in the storage operation is updated with the modification.

1228681

Because of the cache memory, the cache state is used, and the data is written into the cache memory. However, a conflict between the save query and the peek query was detected. The memory cancels the save operation. [0089] During clock cycle 5, peep inquiries to the server, and the cache memory will provide a right_ $ green bottom 斉 dead 択 exclusive status to the cache line specified by address A. Because the storage operation has been defeated, and the Dingxinyi Dagger has been canceled, it is unique to leave the correct state of the cache line. That is, if the left and right μ w 4 β ~ A this ^ ^ ^ Ak 'Right storage storage has never been started, the shape of the cache line, j, is any of its original state. In the clock, the peep action of the peep calculation enters the pipeline through (represented by SnpA A)

J stage. Between clock cycle 7 and "month", the peep action will go through the remaining stages of "1" to update the status of the cache line as invalid, as specified by the external operation of the cache memory peep.

[0090] As mentioned above, the conventional [2 cache memory must cancel the storage operation. Otherwise, the valid data will be written into the cache memory at the end of the storage operation, and the status will be updated to modify, and then due to the peep action, a unique status showing that the cache line has not been modified (passed at the end of storage) Update the status to the status before the modification), so this peep action will invalidate the cache line. As a result, valid stored data is lost. Therefore, the conventional L2 cache memory must cancel the storage operation so that the peep inquiry can receive the correct state. Canceling a save operation (that is, a move-in operation) has a negative effect, as described here. [0 0 9 1] Referring now to FIG. 7, it is a timing diagram illustrating the operation of the [2 cache memory 1 0 6 of FIG. 1 according to the process of FIG. 5 according to the present invention. It can be seen from FIG. 7 that the internal portion of the L2 cache memory 106 of the present invention can favorably process

1228681 V. Description of the invention (30) Impact of sudden peeping nose operation 'without canceling the operation in the transfer, thereby reducing the negative effect brought by canceling the operation in the transfer.

[0 0 9 2] In the timing diagram of FIG. 7, the L2 cache memory 106 of FIG. 3 passes the new operation signal 334, and receives the lid storage operation initiated by L1D 104 of FIG. 'The storage operation query with memory address A. When the storage operation is in transition, a peek operation having the same memory address A from the bus interface unit 10 8 via the peep inquiry signal 3 36 is followed shortly thereafter. Peep queries can cause conflicts between this stored operation and the peek operation. In this example, the peep operation is an invalid peep operation, that is, an external peep operation on the processor bus 112 is an invalid operation 'such as a write invalidation or a read invalidation operation. In FIG. 7, the stored inquiry pass is called StQ A, the peep inquiry pass is called SnpQ A, and the peep action pass is called SnpA, as in the case of FIG. 6. In addition, the storage operation of the storage operation of the address a is passed or the storage operation is passed. [0093] During clock 1, according to block 502 in FIG. 5, the arbiter 302 selects the stored query to pass, and the stored query will proceed to j-stage 3 22 in FIG. During clock cycle 2, according to block 504, the stored query proceeds to K-phase 324 'and the peek query is accepted to access [2 cache memory

1 0 6 ° During clock 3, the storage inquiry and the peep inquiry proceed to L-phase 326 and K-phase 324, respectively. [0094] During clock 4, the storage query reaches the% stage 328, and a unique flag state 216 value is received from the tag = array 206. Upon completion of the generation, the logic 318 will receive the unique flag state 216 and — L1D store the operation type 364 value from the operation pipeline 304, and according to the flag obtained in block 506.

1228681

V. Description of the invention (31): State 216 and operation type 364 ′ result in storage end pass = or state in transition. "In the example, the state of the transition in progress: Piece [[]]: Second phase and second phase [0 0 9 6] Also, during clock 5, according to block 512, Logic 3. 8 will detect The conflict between the storage operation and the peep operation = the rusher, the peeper will reach the M-phase m and obtain a unique flag state 2 1 6 value from the flag array 206. However, at the following clock 6 to 6 During the period of 8, the unique state of the cache line is incorrect or will be incorrect once the storage action is updated to the modified state. Therefore, the peep conflict logic 308 of the present invention can advantageously generate a peep Query received incorrect unique mark status 2 1 6 value is also new peep mark status 3 丨 2. That is, according to block 5 1 4 'Peep Conflict Logic 3 008 based on the obtained peek query mark status 216 and modify The (Modified) storage action updates the status value to generate the peek mark status 3 1 2, which is the transition status, as described in Table 2. In this example, according to Table 2, the peek conflict logic 308 will generate a modified peek mark status. A value of 312 is because the peek query is located in M-stage 328, such as The calculation type signal 364 is displayed; the storage end is located in the L-phase 326, as shown in the operation type signal 364; the address 356 in the M-phase 328 and the L-phase 326 will conflict, as shown in the address conflict signal 348; And in the transfer at L-phase 326, the storage update status is modified. [0097] According to block 516, in response to the generation of the peep mark status 312, the 'peep action generation logic 314 will obtain the peep mark status according to Table 3.

Page 1228 28681

3 1 2 ′ and a peep motion occurs. In this example, according to Table 3, the peep action generation logic 314 generates a true EsnpFinLd signal, so that a peep action is loaded into the peep action queue 204. And because the peep flag state 312 is modified (2 'bll), the peep action generating logic 314 will generate a true-valued information field 408. And, in this example, the external bus operation is an invalidation type operation (that is, it cannot be shared), so the peek action generation logic 314 will generate an invalid (2, b00) peep update status value of 4.0. . [0098] During clock 6, according to block 518, the peek action accepts arbitration by the arbiter 302 into the j_ stage 322. During clocks 6 to 8, according to block 522, the storage action will go through K-phase 324, L-phase 326, and M-phase 328, and the marker array 206 will be updated with the modified transition state value, and will be stored The data was written into the data array 208. [0100] During clocks 7 to 9, according to block 524, the peep action passes through K-phase 324, L-phase 326, and M-phase 328, and the marker array 206 is updated with invalid peep update status values. In addition, during clock 9, if the data provided by the peeping action field 408 indicates that the task peeking on the processor bus 12 should provide data, then the peeping action will pass from the data array 2 08 through the data signal. 218, and get the cache line data. In one embodiment, one or more subsequent actions may be generated to obtain the data requested by the operation peeked by the processor bus 11 2. ° [ooloo] During the subsequent clock cycle, according to block 526, the bus action generation logic 316 generates a bus action according to the peek mark state 312 and transmits the bus action to the bus interface unit 1 08, And according to step 528, the bus interface unit 丨 08 will act on the bus

1228681

= ΛΛ / ΛChaye. Favorable *, in response to the bus action of the Vision / Department during the bus encounter period of the processor, it can be non-_ in terms of timing in subsequent clocks, like L2 cache memory 106 and 1 ^ cache memory The signal between 102 and 104 is like. Therefore, peep conflicts will only affect the internal control logic of the L2 cache memory 106 or non-tin-critical_critical logic, thereby improving the operating frequency of the microprocessor 100. Relevant communication for canceling operations in the cache memory 1 02-1 06 is needed to reduce complexity.

[0 0 1 0 1] Although the present invention and its objects, features, and advantages have been described in detail, other embodiments may be included within the scope of the present invention. For example, although the present invention has been described with reference to a write invalidation peep protocol, the present invention is applicable to other protocols, such as a write update protocol. In addition, although the present invention has been described with reference to the cache consistency state blunt protocol, the present invention is still applicable to other cache consistency protocols. Finally, although the L2 cache memory system of the present invention uses L2 to describe the system context between L1 cache memory and system memory, L2 cache memory can also be located in microprocessing

Any cache memory level of the processor, as long as this level, the operation in the transfer may conflict with the peep operation. ^ In summary, the above is only a preferred embodiment of the present invention, and the scope of implementation of the present invention cannot be limited by it. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention should still fall within the scope of the patent for the present invention. I ask your reviewing committee to make a clear note and pray for your approval.

1228681 Schematic illustration of a schematic diagram showing a cache memory of a microprocessor [0023] FIG. 1 is a block diagram according to the present invention. [0 024] FIG. 2 is a block diagram illustrating the L2 cache memory of FIG. 1 according to the present invention. [0 0 2 5] FIG. 3 is a block diagram of the L 2 cache memory of FIG. 1 according to the present invention in more detail. [0 026] FIG. 4 is a block diagram of the peek action queue of FIG. 2 according to the present invention. It is clearly shown that for the conflict between operations in the externally viewed work, the L 2 fast operation flow chart in FIG. The operation timing diagram shows the operation example of the operation cancellation in the conventional L2 cache. Fig. 1 shows the L2 cache memory of Fig. 1 according to [0027]. Fig. 5 is based on the peep operation and transfer of memory generated by the industry. [0028] Fig. 6 is a related technology memory and [0 02 9] A glance at the conflict of operations Figure 7 is based on the present

According to Figure! 5 sequence timing diagram of the operation. Description of drawing number = 100: microprocessor 102 first order instruction (L1 I) cache memory 104 first order data (L1 D) cache memory 106 second order (L2) cache memory 108 bus interface Unit 112 Processor Bus 202 Control Logic Page 40 1228681 Brief Description of Drawings 204 Peep Action Queue 206 Tag Array 208 Data Array 212 Memory Address 216 Status Output 218 Data Output 302 Arbiter 304 Arithmetic Pipeline 306 Address Comparator 308 Peep conflict logic 312 Peep flag status 314 Peep action generation logic 316 Bus action generation logic 318 End pass generation logic 322 J-Phase 324 K-phase 326 L-phase 328 M-phase 332 End operation 334 New operation 336 Peek inquiry 338 Peep action 342 Update status or transition status 344 Data signal

Page 411228681 Simple explanation of the drawing 346: Operation type signal 348: Address conflict signal 3 5 2: Memory address 3 5 4 ·· Sacrificed address 3 5 6: Memory address 362: In-transit status or update status 364 , 368: Operation type 3 6 6: In transition state 372: Sacrifice valid signal 374: Bus action 382: End action queue 4 0 2 ·· Valid bit 4 0 4: Memory address 40 6: Peep update status bit $ 40 8 • Data Bits 第 42 页

Claims (1)

1228681 • A kind of multi-pass cache memory used in a microprocessor 1. The body includes a tag array for receiving a peeping query between -〃 one pass and one end pass, the operation ... The other one inquires about the cached memory disc in the microprocessor, and the other one uses 乂 to transfer between the two. The peep inquiry includes a peep address; and one of the control logics of the mouth, Coupled to the tag array, for detecting a conflict between the address and an address of the cache line; "» Where the control logic detects the conflict, it updates the tag array by Make the end pass complete without canceling the end pass 0 2 · If the cache memory of the first patent application scope includes: a data array coupled to the mark array for storing a plurality of caches Fetch line, where the tag array stores the cache memory consistency state of the cache lines stored in the data array correspondingly. 3. If the cache memory of item 2 of the patent application scope, wherein the control logic detects the conflict, it will selectively write the cache line to or read from the data array. The cache line enables the end pass to be completed without canceling the end pass. 4 · If the cache memory of item 2 of the patent application scope, wherein the query pass includes a first pass of the operation, wherein the query pass will be sent from the mark when the cache line address is sent to the mark array. The array obtains the first cache memory consistency state. 5 · If the cache memory of item 4 of the patent application ’is used, Page 43 1228681 VI. Patent application query 勹 Red: One of the first pass of the peek operation, where the peek query will get the second cache memory from the mark array when the peep address is sent to the mark array Body consistency status. ^ If the cache memory of item 5 of the patent application is filed, the peep " is obtained after the query obtains the first cache memory consistency state from the tag array, and then obtains the first cache memory from the tag array. Two cache memory consistency states. 7. The cache memory of item 6 of the patent application scope, wherein the end pass includes one of the operations located after the query is passed, and is used to selectively read from the data array according to one type of the operation The cache line, or write the cache line to the data array. 8. If the cache memory of item 7 of the patent application scope, wherein the type of the operation includes one of a list, the list includes: a) Move the cache line from the other cache memory to The cache memory; b) storing data of one or more bytes of the cache line from the other cache memory to the cache memory; and c) removing the cache line from the cache memory Fetch memory to load another cache memory BMk body. 9 · If the cache memory of item 5 of the patent application scope, the ending of the action by updating the tag array includes updating the cache after obtaining the consistency state of the second cache memory by the peek query The memory consistency state is used to update the tag array. 10. If the cache memory of item 9 of the patent application scope, wherein the control Page 44 1228681 6. The scope of patent application logic is based on the status of the mark. 11. If the claim logic is also based on sexual status, 12. If the claim logic is based on the visual action in the array. 13 · If the claim array receives the peep inquiry from the coupler 1. 4. If the application of the bus interface unit is issued, 15 · If the application logic is based on the control logic, the bus interface is provided. 16. Such as an arbiter One of the calculations17. If the arbiter requests the update of the cache memory consistency status, it will generate the patent scope No. 1 〇 The peeking inquiry will take the peep mark status please the patent range 11 Peep mark status, and the end Access to this quick question by updating the patent application. Please look at the patent fan, peek a question, ask the patent fan, peek at the mark, and the bus driver, the patent fan, is coupled to, to allow the patent fan to calculate the cache status of the cache memory around the 14th item. An external operation is generated in which a health-care speculative system includes the external operation of the control unit, the control of the control unit, the operation of the communication unit, and the operation of the unit in the unit. The cache memory around item 1 further includes the tag array, which is used to select a plurality of requests for access to the tag array. The cache memory around item 16, in which the middle is selected to have the highest i first Page 45 1228681 6. Scope of patent application. 18. The cache memory of item 17 in the scope of patent application, wherein the arbiter is selected among the request calculations to transfer a cache between the cache memory and the other cache memory. The end of the line drawing operation is passed as the second highest priority after these peep inquiries. 19. The cache memory of item 18 in the scope of the patent application, wherein the arbiter selects the peep action as the next highest priority among the request operations after the passage of these conclusions. 2.20. The cache memory of item 19 in the scope of patent application, wherein the arbiter is selected among the request operations to transfer between the cache memory and the other cache memory. The query of the operation of a cache line passes as the second highest priority after the peep actions. 21 * If the cache memory of the first item of the patent application scope, it further includes: = a plurality of address comparators included in the control logic to detect the peep address and the address of the cache line That conflict. Office 22. If the cache memory of item 21 of the patent application scope is applied, the flushing occurs when the most significant bits of the peep address coincide with the address of the cache line. · A second-order (L2) cache memory used in a microprocessor can internally process a peep operation, which is supposed to be received by a peek operation on an external bus, and In the meantime, the L2 cache in the microprocessor conflicts with one of the operations in the transfer of another cache line, and the L2 fast α does not need to cancel the operation in the transfer. Fetch memory includes 1228681 ▲ A peep conflict logic, based on a flag state in one of the operations in the transition, and a bit conflict between the peep operation and the operation in the transition is detected, resulting in a peep flag state; and a peep action logic Is coupled to the peep conflict logic to generate a peep action based on the peep marker state, and the peep action is used to update the cache memory consistency state of one of the cache lines to After the 状态 $ state in the transition, the cache memory consistency m is updated. 24. If the L2 cache memory of item 23 of the patent application scope, where The peep action also selectively provides data of one or more bytes of the cache line to the peek operation. 25. For example, the L2 cache memory of item 23 of the patent application scope further comprises: a tag array coupled to the peep conflict logic to store the cache memory consistency state of a plurality of cache lines. 26. = L2 cache memory in the scope of patent application No. 25, wherein after the peek operation queries the tag array to obtain the cache memory consistency state of the cache line, the operation in the transfer will The cache memory consistency state of the cache line in the tag array is updated to the tag state in the transfer. Cao 27. If the L2 cache memory of the 26th scope of the patent application, the peep conflict logic also generates the peep flag based on the cache memory consistency state of the cache line inquired by the peep operation. status. 28. For example, the L2 cache entry of item 23 of the scope of patent application, where Page 47 1228681 VI. Scope of Patent Application The cache memory coherent state substantially conforms to the MESI cache memory consistency state agreement. 29. The L2 cache memory according to item 23 of the patent application scope, further comprising: A bus action generation logic 'is coupled to the peep conflict logic to generate a bus action based on the status of the peek mark. 30. If the L2 cache memory of item 29 of the patent application scope further includes: A bus interface unit is coupled to the bus action generating logic to receive the bus action, and based on the bus action, the external bus should be peeked back last time. 31 · A method for enabling a first cache memory to internally process a peep operation 'The peep nose has a correlation in a second cache memory spot that is being transferred between the first cache memory The cache line, the first body does not need to cancel the transfer operation, the method includes: remembering to ask the one of the first cache memory to "⑧ array" to obtain the cache by the transfer operation One of the first states of the line; ^ has used the peek operation to query the mark array to obtain a second state; fetch the cache line After inquiring about the second state, the tag array is updated with the third state of the transfer in which one of the μ lines is taken; the difference is based on the second and third states as quickly as possible, and the shift-in operation is detected One of the addresses conflicts, and a fourth state is generated. Although the calculation and transfer are updated in the third state, the peek 2 and 1228681 are used to update the fourth state of the patent application. The array is used to avoid canceling the branch operation. 3 2. The method according to item 31 of the scope of patent application, further comprising: substantially updating the data array of the first cache memory with the cache line at the same time as updating the tag array with the third state. 33. The method of claim 32, further comprising: after updating the shell material array, providing data from the cache line to the peek operation. 3: According to the method of the paradigm, it further includes: generating a bus t for the look-up phase, t, and u, and detecting the address conflict, and one of the bus operations.