TWI227927B - Method of fabricating a self-aligned contact opening and structure of a self-aligned contact - Google Patents
Method of fabricating a self-aligned contact opening and structure of a self-aligned contact Download PDFInfo
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
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- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 description 15
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000004575 stone Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 241000238631 Hexapoda Species 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
1227927 _案號 92125463_年月日__ 五、發明說明(1) 發明所屬之技術領域 本發明是有關於一種半導體元件及其製造方法,且特 別是有關於一種自行對準接觸窗及自行對準接觸窗開口的 製造方法。 先前技術 目前極大型積體電路(U L S I )製程解析度已經發展到0 . 1 8微米以下,即深度對寬度或直徑的比例愈來愈大,金屬 和半導體的接觸窗也愈來愈小,因此要如何克服愈來愈小 的線寬,防止接觸窗發生對準失誤(Misalignment),已成 為半導體業界的研發重點。 為了克服愈來愈小的線寬以及防止接觸窗發生對準失 誤,通常許多半導體元件會採用自行對準接觸窗 (self-aligned contact,SAC)的設計。特別是,若欲使 基底中之摻雜區與形成在基底上方之導線結構電性連接, 則可以採用自行對準接觸窗的設計來達成。 第1 A圖至第1 D圖所示,其繪示是習知一種自行對準接 觸窗開口的製造流程剖面示意圖。 請參照第1 A圖,提供基底1 0 0,基底1 0 0上已形成有數 個具有頂蓋層1 0 8之閘極結構1 1 0,且每一閘極結構1 1 0還 包括有閘介電層1 0 2、多晶矽層1 0 4以及矽化金屬層1 0 6 , 其中多晶矽層1 0 4以及矽化金屬層1 0 6係為閘極導電層。之 後,在閘極結構1 1 0之側壁形成氮化矽間隙壁1 1 2。 接著,請繼續參照第1 A圖,於相鄰之二閘極結構1 1 0 之間的基底1 0 0上形成阻障層1 1 3。之後,再於基底1 0 0上1227927 _Case No. 92125463_ Year Month Date__ V. Description of the Invention (1) Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a self-aligning contact window and self-aligning contact window. Manufacturing method of quasi-contact window opening. In the prior art, the resolution of the ultra large integrated circuit (ULSI) process has been developed to less than 0.8 microns, that is, the ratio of depth to width or diameter is getting larger and the contact windows of metals and semiconductors are getting smaller. How to overcome the increasingly smaller line widths and prevent misalignment of contact windows has become the focus of research and development in the semiconductor industry. In order to overcome the ever-smaller line width and prevent misalignment of the contact window, many semiconductor devices usually adopt a self-aligned contact (SAC) design. In particular, if the doped region in the substrate is to be electrically connected to the wire structure formed above the substrate, a self-aligned contact window design can be used to achieve it. Figures 1A to 1D show schematic cross-sectional views of the manufacturing process of a conventional self-aligned contact window opening. Referring to FIG. 1A, a substrate 100 is provided. A plurality of gate structures 1 10 having a cap layer 108 have been formed on the substrate 100, and each gate structure 1 1 0 further includes a gate. The dielectric layer 102, the polycrystalline silicon layer 104, and the silicided metal layer 106 are the polysilicon layer 104 and the silicided metal layer 106 are gate conductive layers. Thereafter, a silicon nitride spacer 1 12 is formed on the sidewall of the gate structure 110. Next, please continue to refer to FIG. 1A to form a barrier layer 1 13 on the substrate 100 between two adjacent gate structures 1 110. After that, on the substrate 1 0 0
第8頁 1227927 _案號 92125463_年月日__ 五、發明說明(2) 沈積氧化矽介電層1 1 4,以覆蓋閘極結構1 1 0與阻障層 113° 然後,請參照第1 B圖,於介電層1 1 4上形成圖案化之 多晶石夕硬罩幕層1 1 6後,以硬罩幕層1 1 6為敍刻罩幕,I虫刻 介電層1 1 4。值得注意的是,當介電層1 1 4 a逐漸被移除而 裸露出頂蓋層1 0 8的頂部時,由於氧化矽介電層(1 1 4與 1 1 4 a )對於氮化石夕頂蓋層1 0 8以及氮化矽間隙壁1 1 2之触刻 選擇比不夠高(約1 0〜2 0 ),因此當此蝕刻製程繼續進行 時,會使得部分頂蓋層1 0 8與間隙壁1 1 2被移除(如第1 C圖 所示)。 請參照第1 D圖,繼續進行此蝕刻介電層1 1 4的步驟, 以形成自行對準接觸窗開口 1 2 0。之後,移除位於自行對 準接觸窗開口 1 2 0中的阻障層1 1 3。值得注意的是,當蝕刻 製程繼續進行時,頂蓋層1 0 8與間隙壁1 1 2被移除的問題會 愈來愈嚴重,甚至還可能使得位於頂蓋層1 0 8下方之閘極 導電層(多晶矽層104與矽化金屬層106)被裸露出來。如此 當後續於自行對準接觸窗開口 1 2 0中填入導電材料,以形 成自行對準接觸時(未繪示),將會造成自行對準接觸窗與 裸露之閘極導電層(多晶矽層1 0 4與矽化金屬層1 0 6 )短路。 雖然上述的問題可以藉由形成較厚之頂蓋層1 0 8來解 決,但是在現今製程線寬愈來愈窄的情況下,如此會使得 接觸窗開口的高寬比(Aspect Ration)提高,而造成更多 製程上的限制。 發明内容Page 8 1227927 _Case No. 92125463_ Year Month Date__ V. Description of the Invention (2) Deposit a silicon oxide dielectric layer 1 1 4 to cover the gate structure 1 1 0 and the barrier layer 113 °. Figure 1 B. After forming a patterned polycrystalline stone hard mask layer 1 1 6 on the dielectric layer 1 1 4, the hard mask layer 1 1 6 is used as the mask, and the dielectric layer 1 is etched by the insect. 1 4. It is worth noting that when the dielectric layer 1 1 4 a is gradually removed and the top of the top cap layer 108 is exposed, the silicon oxide dielectric layer (1 1 4 and 1 1 4 a) is not suitable for nitride nitride. The contact ratio of the top cap layer 108 and the silicon nitride spacer 1 12 is not high enough (approximately 10 to 20), so when this etching process is continued, part of the top cap layer 108 and The partition wall 1 1 2 is removed (as shown in Fig. 1 C). Referring to FIG. 1D, the steps of etching the dielectric layer 114 are continued to form self-aligned contact window openings 120. Thereafter, the barrier layer 1 1 3 located in the self-aligning contact window opening 1 2 0 is removed. It is worth noting that when the etching process continues, the problem of removing the cap layer 108 and the spacer wall 1 12 will become more and more serious, and it may even make the gate electrode below the cap layer 108 The conductive layers (the polycrystalline silicon layer 104 and the silicided metal layer 106) are exposed. Thus, when a conductive material is subsequently filled in the self-aligning contact window opening 120 to form a self-aligning contact (not shown), the self-aligning contact window and the exposed gate conductive layer (polycrystalline silicon layer) will be caused. 104 is short-circuited with the silicided metal layer 106). Although the above problems can be solved by forming a thicker cap layer 108, in the case of the current process line width becoming narrower and narrower, this will increase the aspect ratio of the opening of the contact window. This results in more process constraints. Summary of the Invention
第9頁 1227927 _案號 92125463_年月日_魅_ 五、發明說明(3) 有鑑於此,本發明的目的就是在提供一種自行對準接 觸窗及自行對準接觸窗開口的製造方法,以解決習知在相 鄰二個閘極結構之間進行自行對準接觸窗開口製程時,由 於頂蓋層的部分頂部會被裸露出來,而可能造成下方之閘 極導電層在蝕刻製程中被裸露出來,進而造成短路的問 題。Page 9 1227927 _Case No. 92125463_year month_ charm_ V. Description of the invention (3) In view of this, the object of the present invention is to provide a self-aligning contact window and a method for manufacturing a self-aligning contact window opening. In order to solve the problem that during the self-aligning contact window opening process between two adjacent gate structures, part of the top of the cap layer may be exposed, which may cause the lower gate conductive layer to be exposed during the etching process. Exposed, causing short-circuit problems.
本發明提出一種自行對準接觸窗開口的製造方法,此 方法係先提供一基底,此基底上已形成有數個閘極結構, 其中每一個閘極結構包括閘介電層、閘極導電層與頂蓋 層。之後’於這些閘極結構之側壁形成第一間隙壁。然 後,於基底上方形成介電層,以覆蓋這些閘極結構與基 底。接著,蝕刻部分的介電層,直到相鄰的其中二閘極結 構之間的頂蓋層之部分頂部裸露出來為止,而且於被蝕刻 之介電層中係形成一開口 。繼之,於開口的側壁形成第二 間隙壁,其中第二間隙壁的材質例如是與介電層的材質不 同。之後,移除開口中所裸露之介電層,以形成自行對準 接觸窗開口。The invention proposes a method for manufacturing a self-aligned contact window opening. This method first provides a substrate on which several gate structures have been formed. Each of the gate structures includes a gate dielectric layer, a gate conductive layer and Top cover. After that, a first gap wall is formed on a sidewall of these gate structures. Then, a dielectric layer is formed over the substrate to cover these gate structures and the substrate. Next, a part of the dielectric layer is etched until the top of a part of the capping layer between two adjacent gate structures is exposed, and an opening is formed in the etched dielectric layer. Next, a second gap wall is formed on the side wall of the opening, and the material of the second gap wall is, for example, different from that of the dielectric layer. Thereafter, the exposed dielectric layer is removed from the opening to form a self-aligned contact window opening.
本·發明提出一種自行對準接觸窗,此自行對準接觸窗 包括數個閘極結構、介電層、第一間隙壁、第二間隙壁與 導電層。其中,數個閘極結構係配置在基底上,其中每一 個閘極結構具有閘介電層、閘極導電層以及頂蓋層。此 外,介電層係覆蓋這些閘極結構,且介電層中具有自行對 準接觸窗開口而暴露出相鄰的其中二閘極結構之間的區 域。另外,第一間隙壁係配置在自行對準接觸窗開口中之The present invention proposes a self-aligning contact window. The self-aligning contact window includes a plurality of gate structures, a dielectric layer, a first spacer wall, a second spacer wall, and a conductive layer. Among them, several gate structures are arranged on the substrate, and each of the gate structures has a gate dielectric layer, a gate conductive layer, and a cap layer. In addition, the dielectric layer covers these gate structures, and the dielectric layer has a self-aligned contact window opening to expose the area between two adjacent gate structures. In addition, the first gap wall is disposed in a self-aligned contact window opening.
第10頁 1227927 _案號 92125463_年月日__ 五、發明說明(4) 這些閘極結構的側壁。此外,第二間隙壁係配置在自行對 準接觸窗開口中之介電層的側壁,其中第二間隙壁的材質 例如是與介電層的材質不同。另外,導電層係填滿此自行 對準接觸窗開口。 在本發明中,由於將蝕刻介電層以形成自行對準接觸 窗開口的製程分為二步驟來進行,而且在此二步驟之間, 係形成第二間隙壁來覆蓋住裸露之頂蓋層頂部。於是,在 進行介電層之第二個蝕刻步驟(移除開口中所裸露之介電 層)時,閘極結構之頂蓋層較不易被移除。因此,可以避 免習知因頂蓋層被移除而使得閘極導電層可能被裸露出來 的問題,而且還能避免後續所形成之自行對準接觸窗與閘 極導電層產生短路。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細 說明如下: 實施方式 以下係以内連線的製造方法來說明本發明之自行對準 接觸窗開口製程,唯本發明並不限定於此。 第2 A圖至第2 F圖所示,其繪示為依照本發明一較佳實 施例之内連線的製造流程剖面示意圖。 請參照第2 A圖,本發明之内連線的製造方法係先提供 基底2 0 0,且基底2 0 0上已形成有數個閘極結構2 1 0。其 中,每一個閘極結構2 1 0係包括有閘介電層2 0 2、閘極導電 層2 0 6與頂蓋層2 0 8。而且,在一較佳實施例中,閘極導電Page 10 1227927 _ Case No. 92125463 _ Month and Day __ V. Description of the invention (4) The side walls of these gate structures. In addition, the second spacer is disposed on a side wall of the dielectric layer in the self-aligned contact window opening, and the material of the second spacer is, for example, different from that of the dielectric layer. In addition, the conductive layer fills this self-aligning contact window opening. In the present invention, since the process of etching the dielectric layer to form the self-aligned contact window opening is divided into two steps, and between these two steps, a second gap wall is formed to cover the bare cap layer. top. Therefore, during the second etching step of the dielectric layer (removing the exposed dielectric layer in the opening), the cap layer of the gate structure is less easily removed. Therefore, it is possible to avoid the problem that the gate conductive layer may be exposed due to the removal of the cap layer, and it is also possible to avoid the short circuit caused by the self-aligned contact window and the gate conductive layer formed later. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Embodiments The following is a method for manufacturing an interconnect. The self-aligning contact window opening process of the present invention is described, but the present invention is not limited thereto. Figures 2A to 2F are schematic cross-sectional views showing the manufacturing process of an interconnector according to a preferred embodiment of the present invention. Referring to FIG. 2A, the manufacturing method of the interconnect in the present invention firstly provides a substrate 2 0, and a plurality of gate structures 2 1 0 have been formed on the substrate 2 0. Among them, each gate structure 210 includes a gate dielectric layer 202, a gate conductive layer 206, and a cap layer 208. Moreover, in a preferred embodiment, the gate is conductive
1227927 _案號 92125463_年月日__ 五、發明說明(5) 層2 0 6例如是由多晶矽層2 0 4與矽化金屬層2 0 5所構成。其 中,閘介電層2 0 2的材質例如是氧化矽,頂蓋層2 0 8的材質 例如是氮化石夕,而石夕化金屬層2 0 5之材質例如是石夕化鶴或 石夕化鈦。 之後,請繼續參照第2 A圖,於這些閘極結構2 1 0之側 壁形成間隙壁2 1 2。其中,間隙壁2 1 2之形成方法係先在基 底2 0 0上形成共形的間隙壁材料層(未繪示),此間隙壁材 料層的材質例如是氮化矽。然後,進行非等向蝕刻而形成 之。1227927 _Case No. 92125463_ Year Month__ V. Description of the Invention (5) The layer 2 0 6 is composed of a polycrystalline silicon layer 2 0 4 and a silicided metal layer 2 0 5. Among them, the material of the gate dielectric layer 202 is, for example, silicon oxide, the material of the cap layer 208 is, for example, nitride nitride, and the material of the stone-plated metal layer 205 is, for example, stone-plated crane or stone-plated Of titanium. After that, please continue to refer to FIG. 2A to form a gap wall 2 1 2 on the side wall of these gate structures 2 1 0. The method for forming the partition wall 2 12 is to first form a conformal partition wall material layer (not shown) on the substrate 2000. The material of the partition wall material layer is, for example, silicon nitride. It is then formed by anisotropic etching.
另外,在一較佳實施例中,在形成間隙壁2 1 2之後, 更包括於裸露之基底200表面上形成阻障層213,以保護基 底2 0 0。其中,阻障層2 1 3的材質例如是氧化矽或是氮化 石夕。In addition, in a preferred embodiment, after forming the spacers 2 12, the method further includes forming a barrier layer 213 on the surface of the bare substrate 200 to protect the substrate 200. The material of the barrier layer 2 1 3 is, for example, silicon oxide or nitride nitride.
接著,請繼續參照第2 A圖,於基底2 0 0上方形成介電 層2 1 4,以覆蓋這些閘極結構2 1 0與阻障層2 1 3。其中,介 電層2 1 4的材質例如是氧化矽。在另一較佳實施例中,介 電層2 1 4的材質例如是由摻雜矽玻璃層(硼磷矽玻璃)2 1 5與 無摻雜矽玻璃層(氧化矽)2 1 7所構成,而介電層2 1 4的形成 方法例如是先利用化學氣相沈積法形成摻雜矽玻璃層 215,以覆蓋閘極結構210與阻障層213。然後,進行平坦 化製程,以移除部分的摻雜矽玻璃層2 1 5,而使得閘極結 構2 1 0的頂部暴露出來,其中平坦化製程例如是進行化學 機械研磨法。之後,利用化學氣相沈積法於摻雜矽玻璃層 2 1 5上形成絕緣效果較佳之無摻雜矽玻璃層2 1 7。其中,形Next, please continue to refer to FIG. 2A to form a dielectric layer 2 1 4 on the substrate 200 to cover the gate structures 2 1 0 and the barrier layer 2 1 3. The material of the dielectric layer 2 1 4 is, for example, silicon oxide. In another preferred embodiment, the material of the dielectric layer 2 1 4 is, for example, composed of a doped silica glass layer (borophosphosilicate glass) 2 1 5 and an undoped silica glass layer (silicon oxide) 2 1 7 The dielectric layer 2 1 4 is formed by, for example, first forming a doped silica glass layer 215 using a chemical vapor deposition method to cover the gate structure 210 and the barrier layer 213. Then, a planarization process is performed to remove a part of the doped silica glass layer 2 15 and the top of the gate structure 2 10 is exposed. The planarization process is, for example, a chemical mechanical polishing method. After that, an undoped silica glass layer 2 1 7 with better insulation effect is formed on the doped silica glass layer 2 1 5 by a chemical vapor deposition method. Of which
第12頁 1227927 _案號 92125463_年月日__ 五、發明說明(6) 成無摻雜矽玻璃層2 1 7所使用之反應氣體例如是四乙基矽 酸醋(tetra — ethyl — ortho — silicate ,簡稱TEOS),而所形 成之厚度例如是2 5 0 0埃左右。 然後,請繼續參照第2 A圖,於介電層2 1 4上形成圖案 化之硬罩幕層2 1 6。其中,硬罩幕層2 1 6的材質例如是多晶 矽、氮化矽等與介電層2 1 4具有不同蝕刻選擇比之材質,1227927 on page 12 _ case number 92125463 _ year month day__ V. Description of the invention (6) The reaction gas used to form the undoped silica glass layer 2 1 7 is, for example, tetra ethyl vinegar (tetra — ethyl — ortho — Silicate (TEOS for short), and the thickness formed is, for example, about 2500 Angstroms. Then, please continue to refer to FIG. 2A to form a patterned hard mask layer 2 1 6 on the dielectric layer 2 1 4. The material of the hard cover curtain layer 2 1 6 is, for example, a material having a different etching selection ratio than that of the dielectric layer 2 1 4.
且其厚度例如是8 5 0埃左右。而其形成方法係先於介電層 2 1 4上形成硬罩幕材料層(未繪示),然後進行微影蝕刻製 程而形成之。當然,在一較佳實施例中,可以於介電層 2 1 4上形成圖案化之光阻層(未繪示),且以此光阻層作為 後續蝕刻製程之蝕刻罩幕。 繼之,請參照第2 B圖,以硬罩幕層2 1 6作為蝕刻罩 幕,蝕刻部分的介電層2 1 4,直到相鄰的其中二閘極結構 2 1 0之間的頂蓋層2 0 8之部分頂部裸露出來為止,而且於被 蝕刻之介電層2 1 4 a中係形成有開口 2 2 0。The thickness is, for example, about 850 angstroms. The formation method is formed by first forming a hard mask material layer (not shown) on the dielectric layer 2 1 4 and then performing a lithography etching process. Of course, in a preferred embodiment, a patterned photoresist layer (not shown) may be formed on the dielectric layer 2 1 4, and the photoresist layer is used as an etching mask for a subsequent etching process. Next, please refer to FIG. 2B. The hard mask layer 2 1 6 is used as the etching mask, and the dielectric layer 2 1 4 is etched to the top cover between the adjacent two gate structures 2 1 0. A part of the layer 208 is exposed at the top, and an opening 2 2 0 is formed in the etched dielectric layer 2 1 4 a.
隨後,請參照第2 C圖,於介電層2 1 4 a上與開口 2 2 0中 形成共形的間隙壁材料層2 2 2,以覆蓋裸露之介電層2 1 4 a 表面、頂蓋層2 0 8頂部與硬罩幕層2 1 6表面。其中,間隙壁 材料層2 2 2的材質例如是與介電層2 1 4 a的材質不同,但可 與間隙壁2 1 2的材質相同,其例如是氮化矽。當然,間隙 壁材料層2 2 2的材質亦可與介電層2 1 4a的材質相同,其例 如是氧化矽。此外,所形成之間隙壁材料層2 2 2的厚度例 如是介於2 0 0至3 0 0埃之間。 之後,請參照第2 D圖,回蝕刻間隙壁材料層2 2 2 ,以Subsequently, referring to FIG. 2C, a conformal spacer material layer 2 2 2 is formed on the dielectric layer 2 1 4 a and the opening 2 2 0 to cover the surface and top of the exposed dielectric layer 2 1 4 a. The top of the cover layer 2 0 8 and the hard cover curtain layer 2 1 6 surface. The material of the spacer material layer 2 2 2 is, for example, different from the material of the dielectric layer 2 1 4 a, but may be the same as the material of the spacer 2 1 2, for example, silicon nitride. Of course, the material of the spacer material layer 2 2 2 may also be the same as that of the dielectric layer 2 1 4a, such as silicon oxide. In addition, the thickness of the formed spacer material layer 2 2 2 is, for example, between 200 and 300 angstroms. After that, referring to FIG. 2D, the spacer material layer 2 2 2 is etched back to
第13頁 1227927 年_月 修正 曰 案號 92125463 五、發明說明(7) 保留下位於開口 2 2 0側壁之間隙壁材料層2 2 2,而形成間隙 壁2 2 4 ’且間隙壁2 2 4係覆蓋住裸露之頂蓋層2 〇 8的頂部。 接著,請參照第2 E圖,移除開口 2 2 0中所裸露之介電 層2 1 4 a ’以於相鄰的其中二閘極結構2 1 〇之間形成自行對 準接觸窗開口 2 2 6。其中,移除介電層2 1 4 a的方法例如是 進行蝕刻製程。之後,移除硬罩幕層2 1 6。 值得一提的是,由於在移除開口220中所裸露之介電 ^ 2 1 4 a的步驟前,於裸露之頂蓋層2 〇 8頂部覆蓋間隙壁 4,因此當在移除介電層2丨“時,可以降低頂蓋層2 8被 除j機率。換言之,位於頂蓋層2 〇 8下方之閘極導電層 頂蓋層2 0 8較不易被移除,故不會裸露出來,因此可以 知閘極導電層與後續所形成之自行對準接觸窗短路 具。1題。在—較佳實施例中,若間隙壁2 2 4與介電層2丨4 a ς有高蝕刻選擇比,則頂蓋層2 〇 8被移除的機率更士大幅 2低,而在一較佳實施例中,間隙壁2 2 4的材質例如是 石夕 且介電層2 1 4 a的材質例如是氧化石夕。 如9 ^外,在另一較佳實施例中,若介電層214的材質例 由推雜碎玻璃層215(硼磷矽玻璃)與無摻雜矽玻璃層 先1乳化石夕)所構成,則第2B圖至第2E圖之製裎步驟係為 二ί無摻雜矽玻璃層2 1 7進行蝕刻,以裸露出相鄰的其中 :間極結構2 1 0之間的頂蓋層2 0 8之部分頂部。之後/於開 著2 2 0中之無摻雜矽玻璃層2 1 7 a的側壁形成間隙壁2 2 4。接 層U再移除相鄰的其中二閘極結構2 1 0之間的摻雜矽玻璃Page 13 1227927 _ Month Amendment Case No. 92125463 V. Description of the Invention (7) Keep the spacer material layer 2 2 2 on the side wall of the opening 2 2 0 to form the spacer 2 2 4 ′ and the spacer 2 2 4 It covers the top of the exposed cover layer 208. Next, referring to FIG. 2E, the exposed dielectric layer 2 1 4 a ′ in the opening 2 2 0 is removed to form a self-aligning contact window opening 2 between two adjacent gate structures 2 1 〇. 2 6. The method for removing the dielectric layer 2 1 4 a is, for example, an etching process. After that, the hard cover curtain layer 2 1 6 is removed. It is worth mentioning that, before the step of removing the exposed dielectric ^ 2 1 4 a in the opening 220, the spacer 4 is covered on the top of the exposed cap layer 2 08, so when the dielectric layer is removed 2 丨 ", it can reduce the probability of the top cover layer 2 8 being removed. In other words, the gate conductive layer top cover layer 208 located under the top cover layer 208 is less likely to be removed, so it will not be exposed. Therefore, it can be known that the gate conductive layer and the self-aligned contact window shorting device formed later. 1. In the preferred embodiment, if the spacer 2 2 4 and the dielectric layer 2 丨 4 a have a high etching option Compared with that, the probability that the cap layer 2 08 is removed is even greater than 2, and in a preferred embodiment, the material of the partition wall 2 2 4 is, for example, Shi Xi and the material of the dielectric layer 2 1 4 a For example, it is oxidized stone. As shown in FIG. 9, in another preferred embodiment, if the material of the dielectric layer 214 includes a doped glass layer 215 (borophosphosilicate glass) and an undoped silicon glass layer (Fossil evening), then the steps of making the 2D to 2E steps are two non-doped silica glass layers 2 1 7 to etch to expose the adjacent: Part of the top cover layer 2 0 8 between the structures 2 0. Then / the side wall of the undoped silica glass layer 2 1 7 a in the opening 2 2 0 forms a spacer 2 2 4. Remove doped silica glass between two gate structures 2 1 0
1227927 _案號 92125463_年月日__ 五、發明說明(8) 上述之描述係為本發明之自行對準接觸窗開口的製造 流程。當然,之後更可繼續下述之製程,以完成内連線製 程,其詳細說明如下。 請參照第2 F圖,在移除阻障層2 1 3後,於自行對準接 觸窗開口 2 2 6中填入導電材料,以形成自行對準接觸窗 2 2 8。其中,導電材料例如是金屬鎢或是多晶矽等導電材 料,而填入導電材料的方法例如是先於介電層2 1 4 b (或無 摻雜矽玻璃層2 1 7 a )上形成導電材料,且此導電材料至少 填滿自行對準接觸窗開口 2 2 6 ,然後以回蝕刻法或是化學 機械研磨法去除開口 2 2 6以外之導電材料。1227927 _ Case No. 92125463_ Year Month__ V. Description of the invention (8) The above description is the manufacturing process of the self-aligned contact window opening of the present invention. Of course, the following processes can be continued in the future to complete the interconnection process. The detailed description is as follows. Referring to FIG. 2F, after removing the barrier layer 2 1 3, a conductive material is filled in the self-aligning contact window opening 2 2 6 to form a self-aligning contact window 2 2 8. Among them, the conductive material is, for example, metal tungsten or polycrystalline silicon, and the method of filling the conductive material is, for example, forming a conductive material on the dielectric layer 2 1 4 b (or the undoped silicon glass layer 2 1 7 a). And the conductive material at least fills the self-aligned contact window opening 2 2 6, and then removes conductive materials other than the opening 2 2 6 by an etch-back method or a chemical mechanical polishing method.
此外,再一較佳實施例中,於自行對準接觸窗開口 2 2 6中填入導電材料的步驟之前,係將間隙壁2 2 4先行移 除。In addition, in another preferred embodiment, the spacer 2 2 4 is removed before the step of self-aligning the contact window opening 2 2 6 with a conductive material.
然後,請繼續參照第2 F圖,在介電層2 1 4 b (或無摻雜 矽玻璃層2 1 7 a )上形成導線結構2 3 0,且此導線結構2 3 0係 與自行對準接觸窗2 2 8電性連接。其中,導線結構2 3 0的形 成方法例如是進行金屬鑲嵌製程。此金屬鑲嵌製程例如是 先於介電層214b(或無摻雜矽玻璃層217a)上形成另一層介 電層(未繪示),其中,此介電層具有溝渠(未繪示),以暴 露出自行對準接觸窗2 2 8。然後,於溝渠中填入導線材料 層(未繪示)。其中,導線材料層的材質例如是鎢或銅等導 線材料。接著,以化學機械研磨法去除溝渠以外之導線材 料層。 此外,在另一較佳實施例中,導線結構2 3 0的形成方Then, please continue to refer to FIG. 2F to form a wire structure 2 3 0 on the dielectric layer 2 1 4 b (or undoped silica glass layer 2 1 7 a), and the wire structure 2 3 0 is self-aligned. The quasi-contact window 2 2 8 is electrically connected. The method for forming the lead structure 230 is, for example, a damascene process. The metal damascene process is, for example, forming another dielectric layer (not shown) on the dielectric layer 214b (or the undoped silica glass layer 217a). The dielectric layer has trenches (not shown), The self-aligning contact window 2 2 8 is exposed. Then, fill the trench with a layer of wire material (not shown). The material of the wire material layer is, for example, a wire material such as tungsten or copper. Next, a layer of wire material other than the trench is removed by chemical mechanical polishing. In addition, in another preferred embodiment, the formation method of the wire structure 2 3 0
第15頁 1227927Page 15 1227927
修正____ ΐ 21Ξ iv於介電,214 b (或無摻雜石夕玻璃層2 1 7 a)上形成 φ、、' 曰(未繪不)’以覆蓋自行對準接觸窗2 2 8。其 二-ϊ Κ材料層例如是鎢或鋁等導線材料。#著,進行 破衫蝕刻製程,以定義出導線結構2 3 0。Correct ____ ΐ 21Ξ iv on the dielectric, 214 b (or non-doped Shixi glass layer 2 1 7 a) to form φ ,, 'said (not shown)' to cover the self-aligned contact window 2 2 8. The second -ϊK material layer is a wire material such as tungsten or aluminum. # 着 , Carry out the etch process to define the wire structure 2 3 0.
=下係針對於第2F圖所得之内連線結構來說明本發明 =^ =對準接觸窗的結構。請參照第2F圖,此内連線結構 ^括本發明之自行對準接觸窗的結構與導線結構23〇。其 =,自仃對準接觸窗的結構包括數個閘極結構2丨〇、介電 層214b(或無摻雜矽玻璃層2l7a)、間隙壁(212與2 2 4 )與導 ,層2 2 8。而且,這些閘極結構21〇包括閘介電層2〇2、多 曰曰矽層2 0 4、矽化金屬層2 0 5以及頂蓋層2 〇 8,且多晶矽層 2 0 4與矽化金屬層2 0 5係為問極導電層2 〇 6。 其中’數個閘極結構21〇係配置胃在基底2〇〇上。此外, μ電層2 1 4 b (或無摻雜矽玻螭層2 1 7 a )係覆蓋這些閘極結構 210,且介電層214b(或無摻雜矽玻璃層217a)中具有自行 對準接觸窗開口 2 2 6而暴露出相鄰的其中二閘極結構2丨〇之 間的區域。另外,間隙壁2 1 2係配置在自行對準接觸窗開 口 2 2 6中之這些閘極結構2 1 〇的側壁,其中間隙壁2 1 2的材 質例如是氮化石夕。= The following is a description of the present invention based on the interconnect structure obtained in FIG. 2F = ^ = The structure of the alignment contact window. Please refer to FIG. 2F. This interconnection structure includes the structure of the self-aligned contact window and the wire structure 23 of the present invention. The structure of the self-aligned contact window includes a plurality of gate structures 21, a dielectric layer 214b (or an undoped silica glass layer 2117a), a spacer wall (212 and 2 2 4), and a conductive layer 2 2 8. In addition, these gate structures 21 include a gate dielectric layer 202, a silicon layer 204, a silicide metal layer 205, and a cap layer 208, and a polycrystalline silicon layer 204 and a silicide metal layer. 2 0 5 is an interfacial conductive layer 2 06. Among them, a plurality of gate structures 21 are arranged on the stomach 200. In addition, the μ electrical layer 2 1 4 b (or the undoped silicon glass layer 2 1 7 a) covers these gate structures 210, and the dielectric layer 214 b (or the undoped silicon glass layer 217 a) has a self-alignment. The quasi-contact window opening 2 2 6 exposes an adjacent area between the two gate structures 2 1 0. In addition, the partition wall 2 1 2 is a side wall of the gate structures 2 1 0 arranged in the self-aligned contact window opening 2 2 6. The material of the partition wall 2 1 2 is, for example, nitride stone.
此外,間隙壁2 2 4係配置在自行對準接觸窗開口 2 2 6中 之介電層214b(或無摻雜矽玻璃層217a)的側壁,且覆蓋住 裸絡之頂盖層2 0 8的頂部。其中,間隙壁2 2 4的材質例如是 與介電層214b(或無摻雜石夕玻璃層217a)的材質不同,但可 與間隙壁2 1 2的材質相同’其例如是氮化石夕。當然,間隙In addition, the spacer 2 2 4 is a side wall of the dielectric layer 214 b (or undoped silica glass layer 217 a) disposed in the self-aligned contact window opening 2 2 6 and covers the bare top cover layer 2 0 8 the top of. The material of the spacer 2 2 4 is, for example, different from the material of the dielectric layer 214b (or the undoped stone layer 217a), but may be the same as the material of the spacer 2 1 2 '. For example, it is nitrided stone. Clearance
第16頁 1227927 __案號 92125463_年月日__ 五、發明說明(10) 壁224的材質亦可與介電層214b(或無摻雜矽玻璃層217a) 的材質相同,其例如是氧化矽。 另夕卜,導電層2 2 8係填滿自行對準接觸窗開口 2 2 6 ,且 作為自行對準接觸窗之用。其中,導電層2 2 8的材質例如 是金屬鎢或是多晶矽等導電材料。 此外,對一内連線結構來說,更包括導線結構2 3 0配 置在介電層2 1 4 b (或無摻雜矽玻璃層2 1 7 a )上,且導線結構 2 3 0係與導電層2 2 8電性連接。其中,導線結構2 3 0的材質 例如是鎢、鋁或是銅等導線材料。 在本發明中,由於將钱刻介電層2 1 4,以形成自行對 準接觸窗開口 2 2 6的製程分為二步驟來進行,而且在此二 步驟之間,係形成間隙壁2 2 4來覆蓋住裸露之頂蓋層2 0 8頂 部。於是,在進行介電層2 1 4之第二個蝕刻步驟(移除開口 2 2 0中所裸露之介電層2 1 4 a )時,閘極結構2 1 0之頂蓋層2 0 8 較不易被移除。因此,可以避免因頂蓋層2 0 8被移除而使 得閘極導電層可能被裸露出來的問題,而且還能避免後續 所形成之自行對準接觸窗2 2 8與閘極導電層產生短路。 另外,在本發明中由於裸露的頂蓋層208頂部覆蓋有 間隙壁2 2 4,因此即使閘極結構之頂蓋層的厚度較薄,仍 不會產生習知閘極導電層被裸露的問題。因此,本發明可 以使用較薄的頂蓋層,來降低接觸窗開口的高寬比,如此 將可以減少高高寬比對於製程所產生的限制。 此外,上述之製造方法除了應用於一般元件之内連線 製程外,更可應用於記憶體元件中,以使基底中之摻雜區Page 16 1227927 __Case No. 92125463_Year_Month__ V. Description of the invention (10) The material of the wall 224 may also be the same as that of the dielectric layer 214b (or undoped silica glass layer 217a), which is Silicon oxide. In addition, the conductive layer 2 2 8 fills the self-aligning contact window opening 2 2 6 and serves as a self-aligning contact window. The material of the conductive layer 2 2 8 is, for example, a conductive material such as metal tungsten or polycrystalline silicon. In addition, for an interconnect structure, the wire structure 2 3 0 is further disposed on the dielectric layer 2 1 4 b (or the undoped silica glass layer 2 1 7 a), and the wire structure 2 3 0 is related to The conductive layers 2 2 8 are electrically connected. The material of the lead structure 230 is, for example, a lead material such as tungsten, aluminum, or copper. In the present invention, since the process of engraving the dielectric layer 2 1 4 to form the self-aligned contact window opening 2 2 6 is divided into two steps, and a gap wall 2 2 is formed between the two steps. 4 to cover the top of the bare top cover 208. Therefore, when the second etching step of the dielectric layer 2 1 4 is performed (removing the exposed dielectric layer 2 1 4 a in the opening 2 20), the cap layer 2 0 8 of the gate structure 2 10 Less easily removed. Therefore, the problem that the conductive conductive layer of the gate may be exposed due to the removal of the cap layer 2 08 can be avoided, and the subsequent self-aligned contact window 2 2 8 and the conductive short layer of the gate can be avoided. . In addition, in the present invention, since the top of the bare cap layer 208 is covered with a gap wall 2 2 4, even if the thickness of the cap layer of the gate structure is thin, the conventional problem that the conductive layer of the gate is exposed will not occur. . Therefore, the present invention can use a thinner capping layer to reduce the aspect ratio of the contact window opening, which can reduce the limitation of the aspect ratio on the manufacturing process. In addition, the above-mentioned manufacturing method can be applied not only to the interconnection process of general devices, but also to memory devices to make doped regions in the substrate.
第17頁 1227927 _案號 92125463_年月日__ 五、發明說明(11) 藉由自行對準接觸窗與上方之位元線之電性連接。若上述 之製程係應用於記憶體元件中,則上述之導電結構2 3 0則 是位元線,而上述之自行對準接觸窗(或導電層)2 2 8則是 位元線接觸窗。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。Page 17 1227927 _ Case No. 92125463_ Year Month Date__ V. Description of the invention (11) The electrical connection between the contact window and the upper bit line is made by self-aligning the contact window. If the above process is applied to a memory device, the above-mentioned conductive structure 230 is a bit line, and the above-mentioned self-aligned contact window (or conductive layer) 2 28 is a bit line contact window. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
第18頁 1227927 _案號 92125463_年月日__ 圖式簡單說明 第1 A圖至第1 D圖是習知的一種自行對準接觸窗開口之 製造流程剖面示意圖。 第2 A圖至第2 F圖是依照本發明之一較佳實施例之内連 線的製造流程剖面示意圖。 【圖式標記說明】Page 18 1227927 _Case No. 92125463_Year Month Day__ Brief Description of Drawings Figures 1A to 1D are cross-sectional schematic diagrams of the manufacturing process of a conventional self-aligned contact window opening. Figures 2A to 2F are schematic cross-sectional views showing the manufacturing process of an interconnect according to a preferred embodiment of the present invention. [Schematic mark description]
1 0 0、2 0 0 ··基底 1 0 2 、2 0 2 :閘介電層 1 0 4 、2 0 4 :多晶矽層 1 0 6 、2 0 5 :石夕化金屬層 1 0 8、2 0 8 :頂蓋層 1 1 0、2 1 0 :閘極結構 1 1 2 、2 1 2 、2 2 4 :間隙壁 1 1 3、2 1 3 :阻障層 114 、114a 、214 、214a 、214b :介電層 1 1 6、2 1 6 :硬罩幕層 1 2 0、2 2 6 :自行對準揍、觸窗開口 2 0 6 :閘極導電層 2 1 5 :摻雜矽玻璃層 2 1 7、2 1 7 a :無摻雜矽玻璃層1 0 0, 2 0 0 · Base 1 0 2, 2 0 2: gate dielectric layer 1 0 4, 2 0 4: polycrystalline silicon layer 1 0 6, 2 0 5: petrified metal layer 1 0 8, 2 0 8: Cap layer 1 1 0, 2 1 0: Gate structure 1 1 2, 2 1 2, 2 2 4: Spacer wall 1 1 3, 2 1 3: Barrier layer 114, 114a, 214, 214a, 214b: Dielectric layer 1 1 6, 2 1 6: Hard cover curtain layer 1 2 0, 2 2 6: Self-alignment 揍, touch window opening 2 0 6: Gate conductive layer 2 1 5: Doped silica glass layer 2 1 7, 2 1 7 a: undoped silica glass layer
220 開 a 222 間 隙壁材料層 228 白 行對準接觸窗(導電層) 230 導 線結構220 open a 222 gap wall material layer 228 white line contact window (conductive layer) 230 wire structure
第19頁Page 19
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| TW92125463A TWI227927B (en) | 2003-09-16 | 2003-09-16 | Method of fabricating a self-aligned contact opening and structure of a self-aligned contact |
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| Application Number | Priority Date | Filing Date | Title |
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| TW92125463A TWI227927B (en) | 2003-09-16 | 2003-09-16 | Method of fabricating a self-aligned contact opening and structure of a self-aligned contact |
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| TW200512862A TW200512862A (en) | 2005-04-01 |
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