TWI226675B - Method of forming dual damascene - Google Patents

Abstract

A method of forming dual damascene uses photoresist to fill in contact holes then it can reduce the aspect ratio of contact hole and insulating layer and prevent over-etched phenomenon when we etch the trenches of metal line. This invention comprise: providing a substrate; forming multi-gates on said substrate; forming a first insulating layer; forming a second insulating layer; etching said second insulating layer and first insulating layer then forming multi-contact holes; coating said second insulating layer and said multi contact holes with a first photoresist layer; exposing and developing said first photoresist layer then expose said second insulating layer, but still have some photoresist in said multi contact holes; covering an anti-reflective layer; forming multi-trenches of metal line; removing photoresist of said multi contact holes; depositing a metal layer on said multi-trenches of metal line and said multi contact holes.

Description

1226675 Modification [Technical field to which the invention belongs] The method is based on the formation of a contact hole area of a metal double damascene in a semiconductor process and: 绫 :: ϋ The photoresist is filled into the contact hole to reduce the trench connected to the metal wire. Top: A method of degree difference to prevent over-etching of the edge of the contact hole. [Prior art]: The process of conducting metal wires is most commonly performed in the insulating layer 12 == hole "to expose the underlying conductor layer or the electrode / source region n. Layer or _ / source region When exposed, 're-use money or deposition to fill the metal 16 into the contact hole and the insulating layer. Then, a photoresist is used to pattern the metal layer, and finally the shape of the metal wire is etched. It is etched out, as shown in the first figure. As the integration degree of integrated circuits increases, the line width of semiconductors becomes smaller and smaller, from the original 1 / zm, 0 · 5 // m, 0 · 3 / zm, 〇 25 // m, to today's 0 2 // m, 0 13 / zm, 0 09 // m. The line width is getting smaller and smaller, but each layer is higher and higher, As the depth of the contact hole becomes deeper and deeper, the conventional metal wire process becomes unsuitable because metal cannot fill the bottom of the contact hole. At this time, a new metal dual damascene process is proposed. 0 Metal The dual Damascene structure is shown in the second figure.

1226675 ______ Case No. 92106394__Check — "_ g ________ V. Description of the Invention (2) First, a conductor layer or a drain / source region 21 is formed on a semiconductor substrate 20, and then a first insulating layer 22 is deposited and flat. After the first insulating layer 22 is formed, a second insulating layer 23 is deposited. The first insulating layer 22 and the second insulating layer 23 are then patterned and etched, and contact holes 24 are formed at this time. After the contact hole 24 is formed, the second insulating layer is patterned again and the second insulating layer is etched. At this time, the trench 25 of the metal wire appears, and then the metal crane (^) or metal copper (Cu) 2 6 is filled. In the contact hole 24 and the trench 25 of the metal wire, a metal polishing method (CMP: chemical-mechanical polishing) is used to finish polishing the metal on the second insulating layer. The above mentioned is the basic process of double inlay of metal. The third A ~ D drawing shows the dual-mosaic structure diagram of the flash gate and its metal. The structure of the flash memory (F 1 ash) on the transistor gate 3 1 is a floating gate 301 (Floating Gate) and a control gate 302 (Control Gate). Because they are stacked on top of each other, plus the upper insulating layer 32, the total height (X shown in the figure) can reach 8 0 0 Angstroms (A) to 1 100 Angstroms (A). As the line width becomes smaller and smaller, the light source for yellow light exposure is from 0-ΐin, I-1 ine, to the deep UV light source today. However, using a deep ultraviolet (deep UV) light source usually forms an anti-reflective layer 33 (ARC: Anti-Ref 1 Reflective Coating) before applying the photoresist. The purpose is to make the exposed profile (Prof i le) better. As mentioned above, the flash memory gate 31 plus the upper insulating layer 32 can reach a height of 80,000 angstroms (from 110,000 angstroms (a)). After the antireflection layer 33 is formed, its The thickness of the reflective layer at the corners of the insulating layer edge of the contact hole 34 is 341, which is only half or more of the thickness of the other positions.

1226675

Case No. 92106394 V. Description of the invention (3) It is thin. This situation will cause over-etching (Edge under-cut) at the corners of the insulating layer edge of the contact hole when the metal double-inlaid etching is performed on the groove of the metal wire. See figure c. The trench of the original metal wire was etched to a thickness of 2000 to 2500 Angstroms. However, due to this phenomenon, an extra 500 Angstroms will be etched at the corner of the insulating layer edge of the contact hole, which is equivalent to The corner of the insulating layer edge of the hole is etched from 2500 to 3500 Angstroms. This situation can be caused by the excessive ㈣ phenomenon at the corner of the insulating layer edge to cause a short-term phenomenon in the subsequent metal wiring. In order to avoid this phenomenon, the grooves of the metal wires can only be etched with a thickness of i 5000-2000 angstroms, so as to avoid the over-etching phenomenon at the corners of the layer caused by the "etching at the gate". Subsequent short circuit of metal wiring. The groove of the original metal wire became shallower because of the need to avoid the short circuit of the metal wire, but this caused another problem, that is, the groove of the metal wire due to the groove of the gold wire. It becomes shallower, and there is a danger of metal disconnection during the chemical mechanical polishing of rhenium. See the third D figure, the metal wire 35 is on the insulating layer 32, and the thickness in the trench should be 2000 ~ 2500. Angstrom, but in order to avoid excessive etching at the corners of the insulating layer, which results in etching to the gate and short-circuiting in the subsequent metal wiring, the thickness is reduced to 5,000 to 2000 Angstroms. When mechanical polishing is performed, in order to ensure that the adjacent metal lines 35 of the entire wafer will not be connected due to polishing; therefore, there will be an over-polishing (〇verp 0 1 ishing) step. But this over-polishing The steps are The metal wire 35 formed on the insulating layer 32 was worn away, causing the problem of metal disconnection. In addition, the original thickness of the metal and wire 35 became smaller, causing the problem of metal disconnection ° 3 Outer 'metal wire 3 5 original thickness has become smaller, relative

Page 8 1226675 Case No. 92106394 Amendment V. Description of the Invention (4) The cross-sectional area has also become smaller, so the resistance of the metal wire 35 will be increased, causing electrical problems. [Summary of the Invention In view of the phenomenon that causes a problem when a groove is at the height of a contact hole, a method of the present invention is to form a gold or a metal wire by embedding the remaining time on a layer region. In the conventional method for forming a metal damascene, the problem of short-circuiting occurs when the metal wiring is over-etched at the corners of the insulating layer edges of the metal double-damascene etched metal wire. If you want to avoid the shallow trench etching of the above lines, it will cause problems such as metal disconnection = larger values. The present invention provides a double metal method 'to avoid the above situation. , The purpose is to provide a formation method of metal double inlay. Filling in the contact hole to reduce the contact hole area and insulation: the degree difference is to prevent the metal wire trench above the contact hole from being over-engraved at the edges. ^ ' A further object of the present invention is to use the method f to fill in the photoresistor with the shape of the inlay; the height difference on the edge layer area, in order to prevent :: 属: = 和 成方 i 发 ::: : A ㈣, is to provide-a kind of metal double mosaic form first fill into the contact hole to reduce the contact hole area and " —

Page 9 1226675 --- ~ S ^ 92106394_ V. Description of the invention (5) To prevent metal disconnection or resistance value of metal wires The problem of height difference on the area of the insulation layer becomes large. According to the method of forming a plurality of gates, the contact should be made at the moment; a hole should be covered; a part of the contact hole should be comprehensive; the canal inside the contact hole is composed of the remaining contact holes and a plurality of metals as described above. The second and first light exposure of the substrate reveals that the first light covers a portion of the lead groove in the first engraved portion. The present invention: provides a substrate; a bottom upper edge layer of the resist layer shadows the resist layer to reflect light. Dividing the channel with: the shape and the reflection layer on the first exposed layer, the first, the first, and the second photoresist layer are developed on the first; the number of the shape layer and the photoresist layer Each connection provides a second insulating layer edge layer to form an edge layer, and the second insulating layer is exposed to form a plurality of second insulations afterwards; and a contact hole is deposited. A metal-insulating layer is left in the first plural plural second insulating layers and the metal-conducting layer; a metal layer is contacted with the contact edge layer in the insulating layer, and a plurality of wiring grooves are used to remove the multi-layer in the Flat = ί =: layer, wherein the second insulation layer is formed according to the above concept before the second insulation layer is formed, wherein the remaining layer is formed on the second insulation layer in steps of forming a plurality of contact holes; patterning the one insulation layer and the first insulation Floor. The step of engraving the second insulating layer and the first insulating step includes: forming a second photoresist layer on the second photoresist layer; and etching a portion of the first insulation layer according to the above concept, wherein the metal wire trench is in the contact hole.

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5. Description of the invention (6) and connected with the contact hole. According to the above concept, wherein the gate plus the second absolute value is greater than 80,000 angstroms. Height of θ According to the above-mentioned concept, after the step of performing comprehensive exposure and development, and the resist layer to expose the second insulating layer, the remaining f ~ light is more than half of the depth of the contact hole. According to the above concept, the material of the anti-reflection layer is a right-side material. According to the above concept, the metal layer is a metal tungsten or a hafnium steel. According to the above-mentioned concept, the step of depositing the metal layer on the plurality of line trenches and the plurality of contact holes includes: covering the second metal insulating layer, the plurality of metal wire trenches, and the plurality of connection holes ^ = The and removing the plurality of metal wire trenches and the plurality of contact holes are 5′-generized by a chemical mechanical polishing method. According to the above-mentioned purpose, the present invention provides a method for forming a metal double hafnium, including: forming a first conductor layer on a substrate having a plurality of crystals; and forming a first insulating layer on the substrate. Forming a second insulating layer on the first insulating layer; forming a plurality of contact holes on the first conductor layer; depositing a first photoresist layer on the second insulating layer and the plurality of contact holes, · Full exposure develops the first photoresist layer to expose the second insulation 1226675 _ case number 92106394_ year month day__ 5. Description of the invention (7) layer, some of the first photoresist layer is still exposed after exposure and development Remaining in the plurality of contact holes; covering an anti-reflection layer on the second insulating layer and a portion of the first photoresist layer in the plurality of contact holes; forming a plurality of metal wire trenches by etching the anti-reflection layer Layer and part of the second insulating layer; removing part of the first photoresist layer in the plurality of contact holes; and depositing a second conductor layer on the plurality of metal wire trenches and the plurality of contact holes. According to the above-mentioned concept, before forming the second insulating layer, the method further includes planarizing the first insulating layer.

According to the above concept, the step of forming the plurality of contact holes in the first conductor layer includes: forming a second photoresist layer on the second insulating layer; patterning the second photoresist layer; and etching part of the first photoresist layer. Two insulating layers and the first insulating layer. According to the above concept, the second metal line trench is above the contact hole and is connected to the contact hole.

According to the above concept, the height of the first insulating layer plus the second insulating layer is greater than 800 angstroms. According to the above-mentioned concept, after the step of performing comprehensive exposure and developing the first photoresist layer to expose the second insulating layer, the height of the retained portion of the first photoresist layer exceeds more than half of the depth of the contact hole.

Page 12 1226675 ^ ~ ——92106394_ Year, month and month ___, description of the invention (8) According to the above concept, the material of the anti-reflection layer is an organic material. According to the above concept, the metal layer is metal tungsten or metal copper. The above conception, wherein the step of depositing the metal layer on the plurality of metal conductors and the plurality of contact holes includes: covering the metal layer on the marginal layer of Eryiyi, the plurality of metal wire trenches and The plurality of contact holes; genus, two or more metal wire trenches and gold other than the plurality of contact holes are subjected to chemical mechanical polishing. [Embodiments] Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed disclosure, the present invention can be widely implemented in other embodiments, and the scope of the month is not limited, which is subject to the scope of subsequent patents. The contact hole ^ invention discloses a method of using a photoresist to fill the contact hole to reduce the height difference between the metal contact region and the insulating layer region to prevent the lead wire trench above the contact hole from being excessive at its edges. The remaining phenomena, such as the value weaving to avoid subsequent metal wiring short circuit or metal disconnection and metal wire resistance moxibustion and so on. Sand is a method for forming a metal-only mosaic as shown in the fourth A to F drawings. Firstly, a plurality of gates 4 丨 are formed on the circle 40, and the height of the gates is about 5000-200 angstroms. Next, a first insulating layer 42 is deposited on the silicon wafer 40, and the insulating q σ is a silicon dioxide layer or a silicon nitride layer or a silicon dioxide layer and a silicon nitride layer 1226675 -Ά -..... 92106394_ Twisting V. Description of the Invention (9)-'一' 一 ^-These are alternately stacked on top of each other. The insulating layer is then planarized. The planarization method may be a method of flowing at high temperature (f10w), a method of etch back, or a chemical mechanical polishing method. The emphasis of this flattening is whether the flatness is achieved or not. Therefore, according to different processes, the end point of a flattening can be to stop at the top of the gate 41 (as in the embodiment of the present case) or a part of the intermediate pole 41 still remains The thickness stops at the first insulating layer 42. When the planarization process of the insulating layer 42 is completed, a second insulating layer 43 having a thickness of about 3,000 to 40,000 angstroms is deposited. The second insulating layer may be a silicon dioxide layer or a nitride nitride layer. The deposition method may be a low pressure chemical deposition method or a plasma enhanced chemical deposition method (PECVD). Then, the second insulating layer is covered with light ^ and the photoresist is patterned, and the contact hole 44 is etched out by an anisotropic etching method. At this time, the height of the contact hole 44 is about 80000 to 11000. . Then remove the photoresist that was originally covered. 'Add another layer of photoresist 45 on the silicon wafer 40, and adjust the depth of focus (DOF: Depth Of Focus) so that the photoresist on the second insulating layer 43 is fully exposed.' However, the photoresist in the contact hole 44 is not fully exposed. It is preferable that the photoresist energy in the contact hole 44 is more than half of the depth of the contact hole. After the focus depth is determined, comprehensive exposure and development are performed. Then, an anti-reflection layer 46 having a thickness of about 500 to 100 angstroms is formed on a silicon wafer, and the anti-reflection layer 46 is composed of some organic materials. After the antireflection layer 46 is formed, the upper photoresist 47 is used to pattern the metal wires. After the non-isotropic anti-reflection layer and the second insulating layer 4 3 of about 2000 to 2500 angstroms are not covered by the photoresist, the photoresist 47 is removed. At this time, the metal wire channel 48 is form. At this time, since the anti-reflection layer 46 is an organic material, it will be removed in this photoresist removal step. Next, a metal layer 49 is formed on the wafer. The metal may be metal tungsten or metal copper. Finally, the chemical-mechanical polishing method is used to remove the metal other than the metal wire channel 48. 1226675 ^ --- M ^ _921〇6394 V. Description of the invention (10) The process of forming a double metal inlay. ^ Fifth, the method for forming the metal dual damascene shown in Figures A to F. Firstly, a first metal wire 5 is formed on a silicon wafer 50 having a transistor shape, and then a first insulating layer 52 is formed on the silicon wafer 50. This insulating layer may be silicon dioxide or nitride. Layer or silicon dioxide layer and silicon nitride layer are alternately stacked on top of each other to form and then planarize the insulating layer. The method of planarization may be a method of adding high temperature to make it flow (fl0w), or etch back ), Or by chemical mechanical polishing method, the final thickness of the first insulating layer 5 2 is about 50,000 to 70,000 angstroms. When the planarization process of the insulating layer 52 is completed, a second insulating layer 53 having a thickness of about 300 to 4000 angstroms is deposited. The second insulating layer may be a silicon oxide layer or a silicon nitride layer. The deposition method may be a low pressure chemical deposition method (LPCVD) or a plasma enhanced chemical deposition method (pECVD). Then, the second insulating layer is covered with a photoresist and the photoresist is patterned, and the contact hole 54 is etched out by anisotropic etching. At this time, the height of the contact hole 54 is about 8000 to 1 1 0. 0 0 Angstroms. After removing the photoresist that was originally covered, add another layer of photoresist 55 on the silicon wafer and adjust the depth of focus (DOF: Depth Of Focus) so that the photoresist energy on the first insulating layer 5 3 is fully exposed, but the contact The photoresist in the hole $ 4 is not fully exposed. It is best to leave the photoresist energy in the contact hole 54 more than half of the depth of the contact hole. After the focus depth is determined, comprehensive exposure and development are performed. An anti-reflection layer 56 having a thickness of about 500 to 1,000 angstroms is then formed on the silicon wafer 50. The anti-reflection layer 56 is composed of some organic materials. After the anti-reflection layer 56 is formed, the photoresist 5 7 is patterned on the metal wires. After the anisotropic etching of the anti-reflection layer 56 which is not covered by the photoresist and the second insulating layer 5 of about 2 0 0 ~ 2 5 0 0 Å, the photoresist will be removed. At this time, the metal wire channel 5 8 is

Page 15 1226675 _ Case No. 92106394 V. Description of the invention (11) ^ —— Day amendment

form. At this time, the anti-reflection layer 56 is removed due to the steps. The next type may be metallic tungsten or metallic copper. The metal other than the wire trench 5 8 is an organic material, so a metal layer 59 will be photo-resisted on this wafer, and finally the metal dual damascene process will be removed by chemical mechanical polishing to remove the gold metal.

Even though the invention has been described by citing several preferred embodiments, the invention is not limited to the illustrated embodiments. Although specific embodiments are listed and described before t, it is obvious that other equivalent changes or modifications without departing from the spirit disclosed by the present invention should be included in the scope of patent application of the present invention. In addition, all other similar and approximate changes or modifications completed without departing from the spirit disclosed by the present invention should also be considered within the scope of the patent application of the present invention. At the same time, the broadest definition = s. The scope of the present invention To include all modifications and similar structures. release

Page 16 1226675 Case No. 92106394 Means a simple explanation of the revised diagram: The first diagram shows a sectional view of a conventional metal wire; the second diagram shows a sectional view of a conventional metal double-inlaid structure; the third Figure A shows a top view of a conventional contact hole and a metal wire; Figure B shows a cross-sectional view of the third A in the direction XX '; Figure C shows a third B in FIG. The shape of the wire trench after etching is shown in a third D drawing, which is a cross-sectional view of the third A-YY ′ direction; the fourth A to F drawings are cross-sectional views of the process of the double-mosaic metal inlay of the present invention; and the fifth Figures A ~ F show cross-sectional views of another metal dual-inlaying process of the present invention.

Description of symbols: • 11 conductor layer 12 insulating layer 13 contact hole 16 metal 20 semiconductor substrate 21 drain / source region 22 first _ first insulation 23 second insulating layer 24 contact hole 25 metal wire channel 26 metal 31 gate Page 17 1226675 _Case No. 92106394_ Year, month, and day correction diagram, simple explanation 3 0 1: floating gate 3 0 2: control gate 3 2: insulating layer 3 3: anti-reflection layer 3 4: contact hole 3 4 1: At the corners of the edge of the contact hole 40, 50: silicon wafer 4 1: gate 5: first metal wire

4 2, 5 2: first insulating layer 4 3, 5 3: second insulating layer 4 4, 5 4: contact hole 4 5, 5 5: photoresistive layer 46, 56: anti-reflection layer 4 7, 5 7: Photoresist 48, 58: Metal wire trenches 49, 59: Metal

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Claims (1)

1226675 Case No. 92106394 Amendment VI. Patent application scope A method for forming a metal dual damascene, comprising: providing a substrate; forming a first insulation layer, forming a second insulation layer, and etching the second insulation layer at the edge layer And the gates and the substrate; on an insulating layer; the first insulating layer to form a plurality of contacts; covering a first photoresist layer on the second insulating layer and the plurality of contact holes; comprehensive exposure and development The first photoresist layer is exposed to the second insulating layer, and a part of the first photoresist layer is still retained in the plurality of contact holes after exposure and development; and an antireflection layer is covered on the second insulating layer and the上 on a photoresist layer inside a plurality of contact holes; belonging to a wire channel, removing a plurality of gold edge layers by etching a part of the anti-reflection layer and the first layer; and depositing a plurality of metal layers The plurality of first photoresist layers in the plurality of contact holes; and a plurality of metal wire trenches and the plurality of contact holes2. A method of forming a metal dual damascene as described in item 1 of the scope of patent application, Before the second insulating layer is formed, the first insulating layer is first planarized, and the end point of the planarization may be selected according to different processes to stop when the top ends of the plurality of gates are exposed, or remain on the plurality of gates. Stop when the first insulating layer has a partial thickness. 3 · The formation method of the metal double inlay as described in item 1 of the scope of patent application Page 19, 1226675 _ Case No. 92106394_ Year Month Date__ VI. Patent application method, wherein the step of etching the second insulating layer and the first insulating layer to form a plurality of contact holes includes: forming a second photoresist Layer on the second insulating layer; patterning the second photoresist layer; and etching part of the second insulating layer and the first insulating layer. 4. The method of forming a metal dual damascene as described in item 1 of the scope of patent application, wherein the metal wire trench is above the contact hole and is connected to the contact hole. 5. The method of forming a metal double insert as described in item 1 of the scope of the patent application, wherein the height of the gate electrode plus the second insulating layer is greater than 800 angstroms. 6. The method of forming a metal dual damascene as described in item 1 of the scope of the patent application, wherein after the step of comprehensively exposing the first photoresist layer to expose the second insulating layer, a part of the first The height of a photoresist layer is more than half of the depth of the contact hole. 7. The method of forming a metal dual damascene as described in item 1 of the scope of the patent application, wherein the material of the anti-reflection layer is an organic material. 8. The method of forming a metal dual damascene as described in item 1 of the scope of patent application, wherein the metal layer is tungsten. Page 201226675 ## ^ 92106394 Amendment < Method for forming a metal double damascene as described in item 1 of the scope of patent application where the metal layer is copperwork. 0 as in item 1 of the scope of patent application In the method of forming a metal dual damascene, the step of depositing the metal layer on the plurality of metal wire trenches and the plurality of contact holes includes: covering the metal layer on the second insulating layer, the plurality of metal wire trenches, and The plurality of contact holes; and / or removing metal other than the plurality of metal wire trenches and the plurality of contact holes by a chemical mechanical polishing method. 1 1 · A method for forming a metal double insert, comprising: · forming a first conductor layer on a substrate having a plurality of pseudotransistors; forming a first insulating layer on the substrate; forming a second insulating layer on On the first insulating layer; forming a plurality of contact holes on the first conductor layer; depositing a first photoresist layer on the second insulating layer and the plurality of contact holes; comprehensively exposing and developing the first photoresist layer In order to expose the second insulating layer, part of the first photoresist layer is still retained in the plurality of contact holes after exposure and development; and an anti-reflection layer is covered in the second insulating layer and the plurality of contact holes. Part of the first photoresist layer; 1226675 _ case number 92106394_ year month__ Sixth, the scope of the patent application is divided into the insulating layer; removing part of the first photoresist layer in the plurality of contact holes; and depositing a first Two conductor layers are in the plurality of metal wire trenches and the plurality of contact holes. 1 2. The method of forming a metal dual damascene as described in item 11 of the scope of patent application, wherein the second insulating layer further comprises planarizing the first insulating layer before forming. 1 3 · The method for forming a metal dual damascene as described in item 11 of the scope of patent application, wherein the step of forming the plurality of contact holes in the first conductor layer includes: forming a second photoresist layer on the second insulation Layer; patterning the second photoresist layer; and etching a portion of the second insulating layer and the first insulating layer. 1 4. The method for forming a metal dual damascene as described in item 11 of the scope of patent application, wherein the second metal line trench is above the contact hole and is connected to the contact hole. 1 5. The method of forming a metal dual damascene as described in item 11 of the scope of the patent application, wherein the height of the first insulating layer plus the second insulating layer is greater than 800 angstroms. Page 22 1226675 _Case No. 92106394_ Year Month Amendment_ VI. Patent Application Range 16 · The method of forming a metal double damascene as described in item 11 of the patent application range, wherein the first exposure is developed by comprehensive exposure After the step of exposing the second insulating layer to the photoresist layer, the height of the portion of the first photoresist layer that is retained exceeds more than half of the depth of the contact hole. 17 • The method of forming a metal dual damascene as described in item 11 of the scope of patent application, wherein the material of the anti-reflection layer is an organic material. 18 · The method for forming a metal dual damascene as described in item 11 of the scope of patent application, wherein the metal layer is tungsten. 19 · The method for forming a metal dual damascene as described in item 11 of the scope of patent application, wherein the metal layer is copper. 2 0. The method for forming a metal dual damascene as described in item 11 of the scope of the patent application, wherein the step of depositing the metal layer on the plurality of metal wire trenches and the plurality of contact holes includes: Covering the metal layer on the second insulating layer, the plurality of metal wire trenches and the plurality of contact holes; and removing the metal other than the plurality of metal wire trenches and the plurality of contact holes by a chemical mechanical polishing method. Page 23