TWI225673B - Flip-chip type semiconductor device and method for fabricating the same - Google Patents

Abstract

A flip-chip type semiconductor device and a method for fabricating the same are provided. A chip and a substrate each formed with a thinned insulating layer thereon are provided, wherein the thinned insulating layers are formed to expose the electrical pads of the chip and the substrate. Then, the chip and substrate are processed in a surface activation process and a connection process, so as to make the chip and substrate electrically connected each other via their corresponding electrical pads.

Description

1225673, Description of the invention (1) — [Technical field to which the invention belongs] The invention of the invention relates to a semiconductor device and a complex semiconductor device and its manufacturing method, and I method, especially a coating [prior art] Flip chip) Feng conductor encloses 4 conductors. Packaging technology H? Niu V body package technology is an advanced half-J attack technology. The difference between the soldier and the conventional non-fog is the semiconductor chip packaged in: The most important way of downloading technology is to place it on the substrate, and connect it to the substrate through a plurality of inverted electrical electrodes that are face down. Due to the flip chip 2: It is not necessary to connect the semiconductor wafer to the substrate in the structure with a larger space, and it is not necessary to connect to the semiconductor substrate. Therefore, the overall package structure can be made thinner and shorter. In the knowing technique, 'want to connect the semiconductor wafer # by flip-chip method, the metal bumps must be provided on the pads of the semiconductor wafer, and pre-solder pads must be provided on the substrate to expose the pre-solder. , The patterned solder resist layer of the dry pad, and the pre-solder bumps disposed on the pre-solder pads, through a reflow process, the metal bumps of the semiconductor wafer are connected and electrically connected to the substrate. Solder bumps. μ Refer to FIG. 1 ′ and want to bond the metal bump 12 to the semiconductor wafer 10, and firstly, a solder bump bottom must be formed on the solder pad 11 of the semiconductor wafer 10.

Under bump metallurgy (UBM) structure layer 13, the UBM structure layer 13 includes an adhesion layer (Adhesion 1 ayer) 1 3 a formed on the pad 11, such as an aluminum metal layer; a barrier to prevent diffusion Barrier layer 13b, such as nickel-hungry alloy; and a wet layer (W e 11 ing 1 ayer) 1 3 c, such as copper metal, for adhering the metal bump 12

17603 Quan 懋 .ptd Page 5 Ϊ225673 Layer V. Description of Invention (2). The feature is that the UBM structure layer 13 is used to provide metal bumps, expansion barriers, and early adhesion (diffusion barrier) and proper adhesion. The cloth bumps 12 and the semiconductor wafers 1 and 10 are soldered 1 1 In the meantime, the solder can be applied to each UBM structure layer, and then the reflow process (Ref low) is used to form the required metal bumps into the fresh materials. According to this, the process of forming the " Hai metal bumps on the pads of the wafer is quite time-consuming and technically complex. Please also refer to FIG. 2, which illustrates a conventional substrate for chip-on-chip sealing 2, which has a plurality of pre-soldering pads 2 1 on its surface insulation layer 2 2. It is typically formed from a metallic material (eg, copper) 7. After that, a solder resist layer 23 is formed on the surface of the substrate 2. For example, μ is used to protect the circuit layer formed on the surface of the substrate and provide insulation characteristics. Among them, the solder resist layer 23 is formed in The plurality of openings 露出 expose the pre-soldering pads 21 on the surface of the substrate. Finally, a pre-solder bump 24 is formed on the pre-soldering pad 21 for subsequent formation of a flip-chip solder connection with a metal bump of a semiconductor wafer. At present, the industry mainly uses stencil printing technology (Stencil Minting techno logy) to deposit solder material on the substrate pads and form pre-solder bumps. However, in actual operation, due to the current reduction in IC area and high density and multi-pin characteristics, Ball Grid Array (BGA), flip-chip (F 1 ip ch ip), and chip size packages (CSP, Ch ip size package) and multi-chip module (MCM, Multi-chip module) 4 packages have gradually become the mainstream in the packaging market, and are often matched with high-performance chips such as microprocessors, chip sets and graphics chips to achieve higher speeds Computing functions, but these structures are bound to reduce the width of the substrate circuit and the pad size

17603 Quan 懋 .ptd Page 6 1225673 V. Description of the invention (3) inch, and when the gap between the substrate pads continues to shrink, the presence of insulation sound on the substrate 'will cover the fresh area of the part' and cause it to be exposed The size of the pads of the insulation sound has been further reduced, resulting in the subsequent formation of the problem of pre-soldering bumps. At the same time, the space occupied by the insulation layer and the height of its formation have affected the template in the stencil printing technology. The size of the openings will inevitably be reduced ^ Not only will the manufacturing cost of the template increase due to the difficult opening of the template, but it will also make it difficult for the solder material to pass through due to the fine hole spacing of the template, which will cause a bottleneck in process technology. In addition, the generation precision of solder material ^ ^ = In addition to the correct template size in the stencil printing technology, the number of stencil printing and cleaning issues must be recognized. Because solder material has stickiness (

Viscosity), and the more printing times, the more residual ^ template = the more tin material in the wall, resulting in the next printing process, the number and shape of the solder materials used by the brush are inconsistent with the design specifications, Therefore, 捅 A + —in Wu Kecunli, use-to determine the number of prints after the second two: term = mold: .... During operation, the shape, size, and reliability of the surface tin material 枓 will be reduced. ; ::: Problems that cause inconvenience in the process of pre -... blocking, the refining should be carried out high ... to form mutual electric charges that even cause adjacent pre-solder bumps :::: Can it produce? Stream, the reliability of the process. The problem of electrical bridge search is serious. Refer to Figure 3 for an explanation. As shown in the figure, a number of full MEMS / known flip-chip semiconductor packages 32 and a number of fresh: =: = 1 are pre-soldering pads formed on the wafer 33 on the substrate 36 and fresh solder on the substrate 36. The pre-soldering bumps 34 shown in the above 7 are the conditions for forming the reflow temperature for melting. Sufficient to melt the pre-solder bumps 34 ^ Resolder the pre-solder bumps 34 to the corresponding

17603 懋 .ptd $ 7 1225673 V. Description of Invention (4) The metal bump 3 1 can form a solder joint 3 7. However, when reflowing at high temperature, the hot-melted solder material may cause overflow, and even cause adjacent solder bridges to electrically bridge each other, which seriously affects the reliability of the process. In addition, in order to suppress the wafer 3 3 and the substrate 3 The difference in thermal expansion between 6 and reduces the stress of the solder joint, further must be filled with primer material 38 in the gap between the wafer and the substrate, resulting in increased complexity of the manufacturing process. [Summary]: In view of the shortcomings of the conventional techniques described above, the main object of the present invention is to provide a flip-chip semiconductor device and a method for manufacturing the same, which simplify the structure and method of electrically connecting semiconductor wafers to substrates. Another object of the present invention is to provide a flip-chip semiconductor device and a manufacturing method thereof, which simplify the electrical connection material, cost, and manufacturing steps between a semiconductor wafer and a substrate. Still another object of the present invention is to provide a flip-chip semiconductor device and a method for manufacturing the same, so as to avoid problems caused by conventionally forming metal bumps on a semiconductor wafer. Yet another object of the present invention is to provide a flip-chip semiconductor device and a method for manufacturing the same, which avoid the problems caused by the conventional formation of pre-solder bumps on a substrate. In order to achieve the disclosure and other purposes, the flip-chip semiconductor device manufacturing method of the present invention includes: providing a semiconductor wafer with an insulating layer on the surface and a substrate with a thin insulating layer, and the insulating layer of the wafer and the substrate is exposed outside Electrical connection ends of the wafer and the substrate; and performing activation processes and bonding of the wafer and the substrate surface, so that the corresponding electrical connection ends of the wafer and the substrate are in phase

] 7603 懋 .ptd Page 8 1225673 V. Description of the invention (5) Electrical connection. Forming a semiconductor wafer having an insulating layer on the surface includes providing a wafer having a plurality of semiconductor wafers; forming an insulating layer on one side of the wafer surface having a plurality of electrical connection terminals, and the insulating layer is exposed The electrical connection ends of the wafer are cut out; and the wafer is cut to form a plurality of semiconductor wafers having the electrical connection ends and an insulating layer. In addition, forming a substrate having a thinned insulating layer on the surface includes: providing a substrate having a plurality of electrical connection ends; forming an insulation layer on a surface of the substrate having a plurality of electrical connection ends; and performing the insulation layer on The thinning process exposes the electrical connection ends of the substrate. In addition, in order to further improve the bonding force between the semiconductor wafer and the substrate, before the semiconductor wafer and the substrate are subjected to the activation process, the surface on which the wafer and the substrate are to be bonded can be planarized, and in an appropriate environment ( (Such as vacuum environment, inert gas environment or chemical solution) to clean the wafer and substrate to remove the oxide layer on the surface of the wafer and substrate and improve the quality of the subsequent surface activation process. The flip-chip semiconductor device manufactured according to the above-mentioned manufacturing method includes: a substrate having a plurality of electrical connection terminals on one surface thereof; and at least one semiconductor wafer having a plurality of electrical connection terminals on one surface thereof, so that The substrate is bonded in a crystal manner and is electrically conductively connected to a corresponding electrical connection end of the substrate. The bonding surface of the substrate and the wafer is effectively bonded together through a surface activation process. An insulation layer is formed on one surface of the substrate and the wafer, and each of the insulation layers is tightly bonded to the peripheral edges of the electrical connection ends of the substrate and the wafer, and the upper surface of the electrical connection ends is exposed for subsequent substrate and wafer Corresponding electricity

17603 Quan 懋 .ptd Page 9 1225673 V. Description of the invention (6) Connection of the sexual connection terminal Therefore, it is not in the semiconductor crystal insulating layer, and the insulating layer, P 1 asma, RIE or ionic gold In order to effectively prevent problems such as sudden and complicated formation on the electrical connection end of the film, the plating and the [implementation method] are used to make the present invention and identification, The invention of this invention can be used in various embodiments, instead of referring to the schematic diagram of the manufacturing method as shown in Figure 4A and 0. The wafer of the invention and the wafer for subsequent reactions are separated from the plasma process level and the chip is connected. The pre-soldering of the end shape, and even bridging the existing flip-chip semiconductor device and its manufacturing method, can be divided into a substrate on which the wafer is carried and a thinned and electrically connected connection surface of the substrate surface is exposed in advance, so that the substrate and the wafer are In a vacuum environment, the electronic and etching (Reactive ionic etching, (I on metal plasma, IMP)) process is used to make the atomic and molecular structures of the substrate and the wafer to be bonded directly. The connection of the real space at normal temperature, so that the electrical connection end of the chip to the corresponding electrical connection end on the substrate, the borrowed semiconductor package must first be metal bumps on the substrate, and on the substrate. Electrically connecting tin bumps, resulting in increased process costs and avoiding problems such as soldering materials in the conventional technology. The purpose, characteristics and functions of the clear, 钤% further detailed disclosure and map The formula is explained in detail, and the solution is as follows. When the bran is used, the form of the taxi is implemented. The following is A ... This is the best practice of the present invention to limit the scope of the present invention. First described. 4A to 4G diagrams are the cost of the present invention. ≪ As shown in the Japanese and Japanese semiconductor devices later, first, a wafer / 40 is provided, and the wafer 40 package is provided.

1225673 V. Description of the invention (7) " Contains a plurality of wafers 400, and electrical connection terminals, such as solder pads, formed on the surface of the wafers 40/400 are used as the wafers 4 〇 / chip 4 〇 Internal circuit output / round-in terminal. As shown in FIG. 4B, an insulating layer (Pass i vat i on 1 ay er) 42 is formed on the side of the wafer 40 where a plurality of electrical connections ^ 41 are formed. The insulating layer 42 may be a dielectric layer (Dieiec1: ric iayer). In a general process, a polyimide layer, a silicon dioxide layer, and a silicon nitride layer are used. de 1 ay er)%, and the insulating layer 42 is tightly bonded to the peripheral edge of the electrical connection terminal 41 of the wafer 40, and the upper surface of the electrical connection terminal 4 丨 is exposed. Then, 'the surface of the wafer 40 having the electrical connection end 41 and the insulating layer 4 2 can be planarized', and the crystal can be applied to the crystal in an appropriate environment (such as a vacuum environment, a passive gas environment, or a chemical solution). The surface of the circle 40 (including the insulating layer and the surface of the electrical connection end) is cleaned to remove the oxide layer on the surface and improve the quality of the subsequent wafer surface activation process. As shown in FIG. 4C, the wafer 40 is diced to form a plurality of wafers 400, and then the wafers 400 are subjected to a surface activation process. The surface activation process can be performed by plasma, reactive ion etching (RIE), or ion metal plasma (Imp) processes, so that the wafer 4 0 0 The surface to be bonded shows nanometer-level atomic and molecular structures, so that it can be subsequently bonded directly to the substrate under vacuum at room temperature. As shown in FIG. 4D, another substrate 50 is provided. The substrate has an electrical connection terminal 5 1 ′, such as a front pin, and an insulating layer 52 is formed on the surface of the substrate 50.

17603 全懋 .ptd Page 11 1225673 V. Description of the invention (8) The edge insulating layer 5 2 may be, for example, epoxy resin (E ρ 〇X yresi η), polyimide, Cyanate Ester , Glass fiber (Glass fiber), bismaleic acid imine / triazine (BT, Bisaleimide Triazine) or mixed epoxy resin and glass fiber (j? R 5) and other materials. Although the two-layer board is used as an illustration in the drawing, the form of the substrate 50 can be, for example, one of single-layer, double-layer, and multi-layer circuit boards. As shown in FIG. 4E, a thinning process is performed on the insulating layer 5 2 of the substrate 50 to remove a part of the insulating layer 5 2 by a technique such as grinding to expose the electrical connection terminal 51. Then, the surface of the substrate 50 (including the electrical connection end and the surface of the insulating layer) can be subjected to a planarization process such as polishing, and can be used in a suitable environment (such as a vacuum environment, a blunt gas environment, or a chemical solution). A cleaning process is performed to remove the oxide layer on the surface and improve the quality of the subsequent substrate surface activation process. As shown in Figure 4F, in a vacuum environment, the substrate 50 is subjected to a surface activation process 'wherein' the surface activation process can be performed by plasma (Reactive ionic etching, RIE) or Ion metal plasma (IMP) process, etc., so that the surface of the substrate 50 to be bonded against the nano-level atomic and molecular structure '俾 can be directly under normal temperature vacuum with the finished surface activation The wafer 4 0 0 is bonded to make the electrical connection terminals 5 1 of each of the substrates 50 to be bonded electrically connected to the electrical connection terminals 4 丨 of the wafer 4 0 to form a flip-chip type. Semiconductor device (as shown in Figure 4G). Of course, the above surface activation process can also be used to provide a plurality of semiconductor wafers bonded to the substrate, so as to form a multi-chip module structure.

17603 Quan 懋 .ptd Page 12 1225673 V. Description of the invention (9), see Figure 4G. Therefore, the flip-chip half-V device manufactured according to the above manufacturing method includes a substrate 50, the surface of which It has a plurality of electrical connection terminals 51 and at least one semiconductor wafer 400. The surface has a plurality of electrical connection terminals 41, which are bonded by a flip-chip method and are electrically conductively connected to the substrate 50. The connection terminal 51 is a flexible connection end, wherein the joint surface of the substrate 50 and the wafer 400 is effectively joined together through a surface activation process. Wherein, a plurality of electrical connection terminals 51 are formed on at least one surface of the substrate 50, and a thinned insulating layer 52 is formed on the surface of the substrate so that the thinned insulating layer 52 and electrical properties are formed. The peripheral edge of the connection terminal 51 is tightly bonded, and the upper surface of the electrical connection terminal 51 is completely exposed; and on the surface of the semiconductor wafer 400 that is to be correspondingly bonded to one of the substrate 50, a plurality of electricity is also formed. The electrical connection terminal 4 丨 has an insulating layer 4 2 on the surface of the wafer 400 and the electrical connection terminal 41 of the wafer 4 is tightly bonded, and the electrical connection terminal 4 丨 is completely exposed. On the upper surface, after subsequent surface activation processes of the substrate 50 and the wafer 400, a can be directly carried out a to electrically connect the wafer 400 and the substrate 50 through exposed electrical connection ends. Therefore, 'the flip-chip semiconductor device of the present invention and the manufacturing method thereof can be formed with an insulating layer in advance on the semiconductor wafer and the substrate for carrying the wafer' respectively, so that the electrical connection ends on the surface of the wafer and the substrate can be exposed. The substrate and wafer can provide the substrate and wafer in a vacuum environment, such as pen water (Plasma), reaction Xiao Xunzi surname engraving (RIE) or ion metal plasma piasma. , Imp) process and other methods to perform the surface activation process, so that the surface of the substrate and the wafer to be bonded to the surface of the nano-level atomic and molecular structure, directly in the

17603 Quan 懋 .ptd Page 13 1225673 V. Description of the invention At room temperature, vacuum connection ends, by adding the crystal electrical connection and reflow soldering the above, the invention can be broadly defined as the entity or all the same, the scope of the patent Intermediate connection with the wafer to the pre-solder formed on the known flip-chip end, and even avoid the bridging phenomenon, a better range, please apply for the following changes in the patent scope. When the end shape is complicated, the only essential meaning is the following method, or it is 0. The substrate is merged with electricity to avoid problems such as Xi Shisheng's connection to correspond. Plating and application of this technology are the same. The semiconductor metal bumps of the substrate are joined, so as to avoid problems such as the conventional examples. In the present invention, all patents will be used to make the chip electrically corresponding to the necessary electrical connection in the packaging package. The resulting process cost technology is only used for soldering materials. It is not intended to limit the quality of the technical content. What others have completed is defined by the technology & Is currently covered in this application

1225673 Simple description of the drawings [Simplified illustration of the drawings]: Figure 1 is a schematic cross-sectional view of a conventional metal bump formed on a solder pad of a semiconductor wafer; Figure 2 is a conventional formation of pre-zinc tin on a solder pad of a substrate FIG. 3 is a schematic cross-sectional view of a conventional flip-chip semiconductor package; and FIGS. 4A to 4G are schematic views of a flip-chip semiconductor device manufacturing method of the present invention. 10 Semiconductor wafer 11 Solder pad 12 Metal bump 13 Metallized structure layer 13a Adhesive layer 13b Barrier layer 13c Wet layer 2 Semiconductor package substrate 21 Pre-solder pad 22 Insulation layer 23 Solder resist layer 24 Pre-solder bump 31 Metal bumps 32 Solder pads 33 Semiconductor wafers 34 Pre-solder bumps 35 Pre-solder pads 36 Substrates 37 Solder joints 38 Primer materials 40 Wafers 400 Semiconductor wafers 41 Electrical connection ends 42 Insulating layers 50 Substrates 51 Electrical connection ends 52 Insulation

17603 懋 .ptd Page 15

Claims (1)

1225673 VI. Application for patent scope 1. A method for manufacturing a flip-chip semiconductor device, comprising: providing a semiconductor wafer with an insulating layer on the surface, and the insulating layer exposing the electrical connection ends of the wafer; providing a surface with a thinned surface A substrate with an insulating layer, and the thinned insulating layer exposes the electrical connection ends of the substrate; and the activation process and bonding of the wafer and the substrate surface are performed to make the corresponding electrical connection ends of the wafer and the substrate electrically Lead. 2. The method of manufacturing a flip-chip semiconductor device according to item 1 of the patent application, wherein the method of manufacturing a semiconductor wafer with an insulating layer on the surface includes: providing a wafer having a plurality of semiconductor wafers; An insulating layer is formed on one side of the electrical connection end, and the electrical connection end of the wafer is exposed on the insulation layer; and a plurality of reshapes are formed to cut the advancing wafer to the pair of wafers. The guideline of the semi-circumferential thin and thin layer has a special edge, and please refer to the table and apply the end, such as the 3 base day QE "in the coverage of the legal system. 1 Forming • The end of the upper surface of the base surface is connected with a continuous electrical electricity number. There is a base with a plate for the substrate that should be lifted. And this should be based on the advance of the face of I 3 table or plate 2, base --- • and the first piece of surrounding crystal. It should be good to connect to the specialist, and even ask the neutral to apply electricity, such as the 4-method system to install the semi-conductive crystal cover. 17603 懋 .ptd Page 16 1225673 6. Scope of patent application The electrical connection ends of the wafer and substrate and the surface of the insulation layer are flattened. 5. For the method of manufacturing a flip-chip semiconductor device according to item 4 of the patent application, after the planarization process, the wafer and substrate surfaces can be cleaned to remove the oxide layer on the surface and enhance subsequent activation. Process quality. 6. For example, the method of manufacturing a flip-chip semiconductor device according to item 1 of the scope of the patent application, wherein the activation process and the bonding system of the surface of the wafer and the substrate can be performed in a vacuum state. 7. For example, the method of manufacturing a flip-chip semiconductor device according to item 1 of the patent application, wherein the activation process can be performed by plasma (Plasma), reactive ion etching (RIE), and ion metal plasma (Ion metal). plasma (IMP) manufacturing process, so that the surface to be bonded between the substrate and the wafer exhibits nanometer-level atomic and molecular structures. 8. For the method of manufacturing a flip-chip semiconductor device according to item 1 or 3 of the scope of patent application, wherein the substrate insulating layer is tightly bonded to the peripheral edge of the electrical connection end of the substrate, and the substrate is electrically exposed after the thinning process. Surface above the end. 9. The method of manufacturing a flip-chip semiconductor device according to item 1 or 2 of the patent application, wherein an insulating layer is formed on the surface of the wafer, and the insulating layer is tightly bonded to the peripheral edge of the electrical connection end of the wafer, and the electrical properties of the wafer are exposed. Above the connection end. 10. If the method of manufacturing a flip-chip semiconductor device according to item 1 or 3 of the scope of patent application, 17603 Quan 懋 .ptd Page 17 1225673 6. Scope of patent application Among them, the substrate can be one of single-layer, double-layer and multi-layer circuit boards. 11. The method for manufacturing a flip-chip semiconductor device according to item 1 of the application, wherein the bonding between the substrate and the wafer can be performed under a vacuum at room temperature. 1 2. A flip-chip semiconductor device comprising: a substrate having a plurality of electrical connection terminals on a surface thereof; and at least one semiconductor wafer having a plurality of electrical connection terminals on a surface thereof for bonding by a flip-chip method And is electrically connected to the corresponding electrical connection end of the substrate, wherein the bonding surface of the substrate and the wafer is effectively bonded together through a surface activation process. 13. The flip-chip semiconductor device according to item 12 of the patent application scope, wherein the activation process can be performed by plasma (Plasma), reactive ion etching (RIE), and ion metal plasma (Ion Metal plasma (IMP) manufacturing process is performed in one way so that the surface to be bonded between the substrate and the wafer exhibits a nano-level atomic or molecular structure. 14. The flip-chip semiconductor device according to item 12 of the patent application scope, wherein an insulating layer is formed on the surface of the substrate, and the insulating layer is tightly bonded to the peripheral edge of the electrical connection end of the substrate, and is exposed through a thinning process. The upper surface of the electrical connection end of the substrate is exposed. 15. The flip-chip semiconductor device according to item 12 of the patent application scope, wherein an insulating layer is formed on the surface of the wafer, and the insulating layer is tightly bonded to the peripheral edge of the electrical connection end of the wafer, and the electrical connection of the wafer is exposed. Surface above the end. 17603 懋 .ptd page 18 1225673 17603 懋 .ptd Page 19