TWI225218B - Decoding method for decoding instructions in an executing package - Google Patents

Abstract

A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an identification segment and an instruction segment. The method also includes using the assembler to reorder the instructions by separating identification segments from instruction segments, grouping all identification segments of the execution package together, and grouping all instruction segments of the execution package together. The method uses the processor to decode identification segments of the instructions at the same time, and adds a length of each identification segment together to calculate a total length of the execution package.

Description

1225218 V. Description of the invention (1) Field of invention The present invention provides a method for decoding a plurality of instructions by a processor, especially a method capable of simultaneously decoding a plurality of instructions of different lengths in an execution packet. BACKGROUND OF THE INVENTION g In recent years, superscalar processors have been more and more widely used in computer systems. This type of processor can execute multiple instructions at once to increase the processor's ability to process data. . A typical processor's process for processing data includes steps such as fetching, decoding, and executing the data. In addition, this type of device must be accompanied by a translator (as s s e m b 1 e r), which is used to compile multiple instructions so that a processor with an ultrascalar architecture can execute these instructions simultaneously. The function of the assembler is to generate an execution package. The execution package contains a number of instructions, and the number of instructions in each execution package does not exceed the number of instructions that the processor can simultaneously execute. The processor can then All instructions in the execution packet are executed simultaneously. Many processors use instruction sets (s e t) containing multiple instructions of different lengths. Compared with an instruction set containing a plurality of instructions of uniform length, the advantage of these plurality of instructions of different lengths is that less memory is sufficient to store these instructions, because these instructions of different lengths are stored twice.

Page 5 1225218 V. Description of the Invention (2) The memory of the instructions (2) is smaller than the memory required for instructions of uniform length for storage. However, it is very difficult to decode these instructions of different lengths, because these instructions are different in length, so the decoder must know the exact length of each instruction before decoding these instructions, in order to decode these instructions. . Please refer to FIG. 1 'FIG. 1 is a block diagram of a conventional instruction 10 of variable length. The instruction 10 is divided into an identification section 12 and an instruction section 18, and the identification section 12 is further. It is divided into a position indication area 14 for indicating whether the instruction 10 is the last instruction in an execution packet, and a length display area 16 for displaying the instructions 10 by byte (by te). length. For example, the length display area 16 shows that the length of the instruction 10 is 3 bytes. The length of a typical identification segment 12 is a nibble or a single byte, and the remaining length of instruction 10 is occupied by instruction segment 18. Please refer to FIG. 2. FIG. 2 is a block diagram of a conventional execution packet 20. The execution packet 20 includes three instructions 25, 30, and 35. The structure of each instruction is the same as that of instruction 10. As shown in the identification segments 26, 32, and 36 in Figure 2, the lengths of the instructions 25, 30, and 35 are 2, 3, and 4 bytes, respectively, and the position indicators in the identification segments 26, 32 are The area is not painted with a slash, which means that the instructions 25, 30 are not the last instructions in the execution of the packet 20. On the other hand, the position indication area in the identification section 36 is painted with a slash, which indicates the instruction 35 is the last instruction in the packet 20.

1225218

Please refer to Figure 3 for the method of instruction packet length of the same length. Figure 3 is the conventional method for calculating multiple executions, processing data, and decoding to calculate an execution packet flowchart. Step 100: Step 10 2: Step Step 104: 106: Steps Step 108: 110: Step 112: Use the finger to use the instruction to place the code here, the longest place to the middle; view as the end of this step, a. The set of translators contains a plurality of instructions of different lengths. The translator compiles a set of instructions containing a plurality of different long-term instructions into an execution packet. The processor extracts the next execution packet. ΪΐΐϊΐΐΠ Identification in an instruction Segment solution: View the length display area in the command to know that the length of the instruction instruction is added to the total length of the execution packet. Inti position indication area to determine whether the instruction is the last one in the package Step 106; Take: (The total length of the packet has been calculated.) The disadvantage of the conventional method of calculating the length of the packet is that the cattle 108 and 110 are too inefficient, more Indeed, during the period of time, only instruction sections in one instruction can be decoded, and j; two $ I to the length of all instructions in the execution packet are accumulated. In other words, the execution packet The instruction length in s is followed by u

1225218 V. Description of the invention (4) Addition. This method of accumulating the length of only one instruction at a time to calculate the total length of all instructions is too time-consuming. Object and Summary of the Invention Therefore, the object of the present invention is to provide a method that can simultaneously calculate the length of a plurality of instructions in an execution packet to solve the above problems. The present invention uses a processor to decode a plurality of instructions in an execution packet, which includes using the processor to simultaneously decode instruction sections in the plurality of instructions. Each of the plurality of instructions includes an identification section and an instruction section. The method further includes using a set of translators by separating each recognition section from its corresponding instruction section, concentrating all the recognition sections in the execution packet, and all the sections in the execution packet. The instruction sections are grouped together to rearrange the plurality of instructions. The method uses the processor to decode the plurality of identification segments in the plurality of instructions simultaneously, and then adds up the lengths of all the identification segments to calculate the total length of the execution packet. Detailed description of the invention The instruction 10 and the execution packet 20 shown in Figs. 1 and 2 respectively are exactly the same as the instruction and the execution packet in the present invention. In fact, the difference between the present invention and the conventional technology lies only in the two. Using a processor to decode multiple instructions

1225218 V. Description of the invention (5) Method. Please refer to FIG. 4. FIG. 4 is a flowchart of a method for compiling, extracting, and decoding instructions of different lengths to calculate the total length of an execution packet according to the present invention: Step 1 30: Use the translator to form a complex array. An instruction set containing a plurality of instructions of different lengths that can be executed simultaneously by the processor; step 1 32: using the translator to rearrange the plurality of instructions in an instruction set and then including the plurality of instructions in the group The instruction set is compiled into an execution packet, and all the identification segments and all instruction segments in the execution packet are gathered together separately; Step 1 34: The processor fetches the next execution packet; Step 1 36: The processing The decoder decodes all the identification segments in the execution packet at the same time; Step 138: Calculate the total length of the execution packet. The key difference between the method for calculating the total length of the execution packet and the conventional method for calculating the total length of the execution packet is that the method of the present invention can simultaneously decode the plurality of identification sections in the execution packet to calculate the The total length of the execution packet, however, the conventional method can only decode the plurality of identification segments in the execution packet by decoding one identification segment at a time to calculate the total length of the execution packet. Obviously, the method of the present invention can save the processor considerable time when calculating the total length of the execution packet.

1225218 V. Description of the invention (6) Please refer to Figure 5. Figure 5 is a process diagram of the group of translators rearranging a plurality of instructions in an execution packet. Figure 5 is mainly a step 1 3 2 in Figure 4 for further Clarified. In the upper part of Figure 5, the instructions 25, 30, and 35 are in the uncompiled state, that is, the identification sections 2 6, 3 2, and 3 6 are located in the instruction sections 2 8, 3 4, and 3 next to 8. Please refer to the lower part of Figure 5. After being rearranged by the translator, the instructions 25, 30, and 35 respectively identify the sections 26, 32, and 36 together, and the instructions Sections 28, 34, and 38 are also grouped together and separated from the identification sections 26, 32, and 36 that are grouped together. Please refer to FIG. 6. FIG. 6 is a schematic diagram for calculating the total length of an execution packet according to the present invention. That is, FIG. 6 further illustrates steps 1 36 and 1 3 8 in FIG. As mentioned earlier, the maximum number of instructions that the processor can process simultaneously limits the number of instructions that an execution packet can contain. In the following example, it is assumed that the processor can process four instructions simultaneously. However, please note that The execution packet 20 in FIG. 2 contains only three instructions 25, 30, and 35. Figure 6 shows another length calculation module 45, which is used to calculate the total length of the execution packet 20. In the following description, it is assumed that the lengths of the recognition sections 26, 32, and 36 are all one byte. Because in the re-arranged execution packet, the identification section is always arranged in front of the instruction section, so the length calculation module 45 will assume that the aforementioned four instructions already exist in

Page 10 A225218, description of the invention (7) $, in package 20 'and ready to read the first four bytes in packet 20, miscellaneous materials and materials', so the first three read by length calculation module 4 5 The individual bytes will be the recognition segments 2 6, 3 2, and 36, and the fourth = tuple read by the length calculation module 4 5 belongs to the bytes in the instruction segment 2 §. Next, the control circuit 5 in the length calculation module 45 will read the position indication area (if any) in the first four bytes of the rearranged execution packet 20. The control circuit 50 reads the position indication area in the identification section 36, and learns through the position indication area in the identification section 36 that the command corresponding to the identification section 36 is to execute the last instruction in the packet 20. Therefore, the fourth byte, that is, the instruction segment 28, cannot be added to the total length of the execution packet 20, because the fourth byte is not an identification segment. 〆 The control circuit 50 controls the selection unit 5 2, 5 4, 5 6 ,; ς Q ^, the first four bytes in the new / listed execution packet 20 = 2 = take g to set the indication area, 2 ί circuit 5 0 recognition-length selection in the recognition segment in the recognition segment Unit: will be controlled to make the discriminator 60, so two = the corresponding length display area is rotated to the first four bytes of one plus: the productive force; = divided into 4 categories, ^ represents the execution of the packet The total length of 20 is equal to 3 + 0 !, 0 'which is ~ y bytes. Small ^ ^, the uninvented method can seal all -q 呷 / 爽 理 一 $ the total length of the line packet so the processor can calculate a time of ^ degrees ... view time, the above example assumes i

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1225218 V. Description of the invention (8) The processor can only process four instructions at a time. However, the method of the present invention covers all processors or digital signal processors that can process any number of instructions simultaneously. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the invention patent.

Page 12 1225218 Simple illustration of the diagram Simple illustration of the diagram Figure 1 is a block diagram of a conventional instruction of variable length. Figure 2 is a block diagram of a conventional execution packet. Figure 3 is a flowchart of a conventional method for translating, retrieving data, and decoding a plurality of instructions of different lengths to obtain an execution packet length. FIG. 4 is a flowchart of a method for translating a plurality of instructions of different lengths, retrieving data, and decoding to obtain an execution packet length. FIG. 5 is a process diagram of a group of translators in the present invention rearranging a plurality of instructions in an execution packet. FIG. 6 is a schematic diagram of calculating the total length of an execution packet according to the present invention. Symbol description of the drawing 10 '25 Instruction 12 ^ 26 Identification segment 14 Position refers to 16 Length display area 18' 28 Instruction segment 20 Execute packet 30 > 35 Instruction 32 '36 Identification segment 34' 38 Instruction segment 45 Length calculation module 50 control circuit 52 ^ 54 selection unit 56 '58 selection unit 60 adder

Claims (1)

1. A method for decoding a plurality of instructions in an execution packet by a processor, each instruction includes an identification section and an instruction section, the method 丨 includes: compiling a plurality of instructions using a set of translators Different execution packets; use the translator to separate each identification segment from its corresponding instruction segment, gather all the identification segments in the execution packet, and place the execution packet in Group all the instruction sections of, such as rearranging the plurality of instructions; Use the processor to decode the identification segments in the plurality of instructions at the same time; and sum up the length of each identification segment to calculate the total length of the execution packet. 2. The method described in item 1 of the scope of patent application, wherein each identification section contains data indicating whether the corresponding command is the last command in the execution packet. 3. The method as described in item 1 of the scope of patent application, wherein the length of the execution packet is the sum of the lengths of the plurality of identification segments. 4. The method described in item 1 of the scope of patent application, wherein the number of instructions in any one execution packet does not exceed the number of instructions that the processor can simultaneously process. Page 14 1225218 — ^ ______ Case No. 91119722 ______0 Year > Month Amendment ___________________________ 6. Scope of Patent Application 5. The method described in item 1 of the scope of patent application, wherein the plurality of instructions are instructions of different lengths. 6. The method according to item 1 of the patent application scope, wherein the processor is a digital signal processor. Page 15