TWI222141B - Semiconductor devices having a metal silicide bi-layer and the method for fabricating the same - Google Patents

Abstract

A method for fabricating a semiconductor device having a metal silicide bi-layer. First, a silicon substrate having a gate and a source/drain region thereon is provided. Next, a conformable nickel layer and a conformable cobalt layer are deposited overlying the silicon substrate in sequence. Next, heat treatment is preformed on the substrate to form a cobalt/nickel silicide bi-layer. Finally, the cobalt layer and the nickel layer without siliciding are removed. A semiconductor device having a metal silicide bi-layer is also disclosed.

Description

1222141 ----- V. Description of the invention (1) Field of invention: The present invention relates to a method for forming a metal silicide, in particular, B 2 relates to a self-aligned metal petrified double-layer structure and a method for forming the same, and The above-mentioned double-layered semiconductor device and a method for forming the same. /, Prior technology: With the development of integrated circuits, component sizes have continued to shrink to increase the degree of component integration. When the component size is reduced, low resistance gates have become a widely discussed topic in the industry recently, and the use of metal silicide materials is important. Low-resistance metal silicides are currently widely used in gates and sources / sinks of two integrated circuits to reduce contact resistance. Recently, the most common fabrication method is self-aligned silicidation technology (self-aligned SALICIDE). ), The method of which is to first form a metal on the soil-and then react the metal with Shi Xi by heat treatment to form a metal silicide on the gate and source electrodes. 2. Among all current metal silicide materials, the resistivity of titanium disilicide (τ 丨 si), cobalt disilicide (CoSi2), and nickel silicide (NiSi) is low, about 15 ~ 20 / z〇hm. -cm. As far as the titanium silicide material is concerned, it has better thermal stability and can effectively reduce the original oxide on the surface of Shi Xi substrate. However, the process usually requires a two-stage tempering process to form a titanium alloy silicide (C54-TiSi2) with a low resistivity face-centered (f to) structure. In addition, from μ to ^ ,, Λ oc 1> Dan t, as the line width shrinks, such as below 0 · 2 5 # m, the thickness of titanium disilicide becomes 7I 浔, which is prone to agglomeration (aggl) 〇merati〇n) phenomenon and increase the chip resistance, the so-called narrow

1222141 V. Description of the invention (2) The narrow-line-width effect. Therefore, when the line width is as small as 0.25 or less, this material is no longer applicable. As far as the Shixi chemical recording material is concerned, its thermal stability is similar to that of the titanium silicide material, but its sheet resistance value is not as much related to the line width as the titanium silicide material, so it has become a process of less than 18 V m Commonly used materials. However, it cannot reduce the native oxide layer on the surface of silicon like titanium, and it is necessary to pay attention to the β / 糸 on the surface of silicon. The process also requires a two-stage tempering process to form a rock with low resistivity. When the line width is reduced below π nm, the high tempering temperature will cause agglomeration and increase its sheet resistance value. π As far as nickel silicide materials are concerned, only one stage of the tempering process is required in the process and the temperature does not need to be too high, but too high will form a nickel disilicon phase with higher resistivity (NiSi2) phase. In addition, its resistivity does not change greatly with the narrowing of the line width. "In addition, it consumes less silicon than titanium silicide ', which can avoid spiking on shallow junctions. Unfortunately, when manufacturing integrated circuits, they are often applied to the plasma process containing fluorine, and the electrons are liable to bond with the nickel atoms of this material to cause the formation of ′, phases on the surface, resulting in an increase in sheet resistance. U.S. Patent No. 5,047,367 to Japan and Japan discloses a method for forming a self-contained double-layered structure, which sequentially deposits and deposits titanium and titanium metal layers and metal layers on a Shixi substrate, and then Heat treatment in a nitrogen-containing atmosphere completes the fabrication of a titanium nitride / cobalt silicide double-layer structure. Furthermore, US + Jun. 6,509, 265 discloses a method for manufacturing a contact window barrier layer. 1 A titanium-niobium alloy layer is deposited on a silicon substrate, and then by including a picture, it is completed first by titanium oxynitride / titanium silicide. Double-layer structure is made by heat treatment. Shaped by the above method

0503-9975TW (Nl); TSMC2003-0015; Spin.ptd Page 7 1222141 V. Description of the invention (3) In the double-layer structure formed, the focus is on forming a contact window barrier layer on the metal silicide layer to avoid subsequent fabrication Spikes occur during plugging, reducing the guilt of the components. However, the metal petrochemical materials used for it are the current Chin metal or cobalt metal, and these materials cannot be applied to the process of very small line width, as described earlier. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a novel metallization double-layer structure and a method for forming the same, and a semiconductor device having a metal silicide double-layer structure and a method for forming the same, by forming a nickel metal silicide layer / Cobalt metal_ The double-layer structure of the lithography layer replaces the traditional metal silicided single-layer structure and is applied to the process of small line width. Furthermore, the thick nickel metal silicide layer at the lower layer avoids the rise of the sheet resistance caused by the narrow line width effect, and the thin nickel metal oxide layer at the upper layer protects the lower nickel metal oxide layer at a later stage Damaged during the process of fluorine-containing plasma. According to the above object, the present invention provides a metal silicide double-layer structure, which includes a silicon substrate and a cobalt / nickel double metal silicide. A cobalt / nickel double metal silicide is placed on a silicon substrate. Among them, the nickel metal silicide layer is located above the silicon substrate, and the cobalt metal silicide layer is located above the nickel metal silicide layer. Furthermore, the thickness of the cobalt silicide layer is 5% to 30 ° / of the thickness of the cobalt / nickel double metal silicide. , And preferably 15%. Furthermore, the cobalt / nickel double metal silicide is formed by applying a heat treatment to the nickel / nickel double metal on the silicon substrate at the same time. Among them, the metal layer

0503-9975TW (Nl); TSMC2003-0015; Spin.ptd Page 8 1222141 V. Description of the invention (4) ---- = thickness f is in the range of 100 ~ 200 Angstroms, and the thickness of the cobalt metal layer is 5 〇 ~ 200。, the range. In addition, the temperature of the heat treatment is in the range of 35 to 55, and the time of the heat treatment is in the range of 10 to 60 seconds. According to the above object, the present invention provides a method for forming a metal silicided double-homogeneous structure. First, a silicon substrate is provided, and a nickel metal layer and a cobalt metal layer are sequentially and sequentially deposited on the silicon substrate. Then, a heat treatment is performed on the silicon substrate to form a cobalt / nickel double metal silicide on the silicon substrate. Furthermore, the thickness of the nickel metal layer is 100 to 2000 angstroms, and the thickness of the fan layer is 50 to 2 angstroms. 00 angstrom range. Target and cobalt gold Furthermore, the above heat treatment is a rapid thermal tempering treatment. Among them, the temperature of the rapid tempering treatment is in the range of 350 to 55 0 t, and the time of the rapid tempering is in the range of 10 to 60 seconds. Metal silicide Further, the thickness of the cobalt metal silicide layer is 5% to 30%, and preferably 15%, of the thickness of the cobalt / nickel double layer. According to the above-mentioned purpose #, the present invention provides a semiconductor device having a double-layer structure, which includes a silicon substrate and a layer of metal oxide. The substrate has a closed electrode (nickel: / nickel double-layer metal oxide) "In the inter-electrode and source" = in the drill, the nickel metal silicide layer is located on the gate and source / drain regions. The metal silicide layer is located above the nickel metal silicide layer. And the double metal silicide layer is simultaneously on the silicon substrate. In addition, the thickness of the metal silicide layer is 5% to 30% of the thickness of the cobalt / metal, and preferably 15%. Furthermore, the cobalt / nickel double-layer metal silicide is obtained by

1222141

The recorded / nickel double-layer metal is formed by performing a heat treatment. The thickness of the nickel metal layer is in a range of 100 to 200 angstroms, and the thickness of the cobalt metal layer is in a range of 50 to 200 angstroms. In addition, the temperature of the heat treatment is in the range of 35 to 55 ° t, and the time of the heat treatment is in the range of 10 to 60 seconds. Also, according to the above object, the present invention provides a method for forming a semiconductor device having a metallized double-layered structure. First, a silicon substrate is provided, which has a gate and a source / drain region, and a nickel metal layer and a cobalt metal layer are sequentially and compliantly deposited on the silicon substrate. Then, a heat treatment is performed on the silicon substrate to form a cobalt / nickel double-layer metal silicide on the gate and source / drain regions. It further includes removing the non-silicided cobalt metal layer and nickel metal layer by a sulfuric acid and hydrogen peroxide mixed solution (SPM). Furthermore, the thickness of the nickel metal layer is in the range of 100 to 200 angstroms, and the thickness of the cobalt metal layer is in the range of 50 to 200 angstroms. Furthermore, the heat treatment is a rapid thermal tempering treatment. Among them, the temperature of the rapid thermal tempering is in the range of 350 to 55 ° C, and the time of the rapid tempering is in the range of 10 to 60 seconds. Moreover, the thickness of the silicide layer of cobalt metal is cobalt / nickel. The thickness of the double-layer metal silicide is from 5% to 30%, and preferably 15%. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are given below with the accompanying Schematic, detailed description as an embodiment: First Example

1222141 V. Description of the invention (6) The method of forming a metal silicide double-layered structure on a stone wick substrate according to the first embodiment of the present invention will be described below with reference to Figures 1a to 1b. First, please refer to Figure 1 to provide a silicon substrate 10, such as a stone evening sphere. Then, by conventional deposition techniques, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), the silicon substrate 10 is deposited on

A nickel metal layer 12 and a cobalt metal layer 4 are deposited sequentially and compliantly. In this embodiment < ' the nickel metal layer 12 is formed by chemical vapor deposition, and its thickness is in the range of 100 to 200 angstroms. Furthermore, the cobalt metal layer η is also formed by chemical vapor deposition, and its thickness is in the range of 50 to 200 angstroms. Next, referring to FIG. 1b, a heat treatment is performed on the silicon substrate 10, for example, using a conventional annealing furnace tube (annea 1 ingfurnace) method or rapid thermal annealing (RTA) to make the metal recording layer 12 And the nickel atoms and cobalt atoms in a cobalt metal layer 14 diffuse into the stone substrate 10 to form a double / nickel double metal stone compound 19 on the substrate 50. Here, the cobalt / nickel double-layer metal silicide 19 includes a nickel metallization layer 16 located above the silicon substrate 10 and a cobalt metal silicide layer 8 located above the recording metal silicide layer 16. Furthermore, a cobalt nickel silicide layer (not shown) is formed at the interface between the nickel metal silicide layer 16 and the cobalt metal petrochemical layer 18.

In this embodiment, a rapid thermal tempering process is performed on the silicon substrate 10 to form a cobalt / nickel double-layer metal silicide 19, wherein the temperature of the rapid thermal tempering process is 3 50 to 5 50 °. C, and the time of rapid thermal tempering is in the range of 10 to 60 seconds. Under this tempering condition, two phases of cobalt silicide (CoSi) and dicobalt silicide (co2Si) coexist. Therefore, its

0503-9975TWF (Nl); TSMC2003-0015; Spin.ptd Page 11 1222141 V. Description of the invention (7) The chip resistance value is more than two 'but no agglomeration will occur. Compared to nickel atoms, cobalt atoms are less likely to bond with fluorine atoms. Therefore, the cobalt metal silicide layer formed over the nickel metal silicide layer 16 can be used as a protective layer to prevent fluorine atoms from directly interacting with the nickel atoms in the nickel metal silicide layer 16 in the subsequent plasma-containing plasma process. Bonding generates an amorphous phase on the surface thereof, which causes the sheet resistance value of the nickel metal silicide layer 16 to increase and the contact resistance to increase.

At the same time, in order to reduce the overall sheet resistance of the cobalt / nickel double metal silicide 19, in this embodiment, the thickness of the cobalt metal silicide layer 18 is 5% of the thickness of the cobalt / nickel double metal silicide 19 ~ 30%. Preferably, the thickness of the cobalt metallization layer 18 is the thickness of the cobalt / nickel double-layer metal silicide 19 ⑽. Similarly, please refer to FIG. 1b, which illustrates a schematic cross-sectional view of a metal silicided double-layer structure according to the first negative embodiment of the present invention / which includes a

And an inscription / recorded double-layered metal dream 19. The double-layered metal 19 is set on the Shixi substrate 10. It includes: a metalized metalized layer 16 is located above the edge of the stoned layer, and a cobalt metalized layer 18 is located on the nickel metalized layer 16 in this embodiment. The thickness of the nickel shoulder metal silicide 19 is 5% to 30%, and preferably 15%. Single-layer titanium, cobalt, and nickel metal: conventional compounds, conventional materials, and double-layer metal petrochemicals *, because the tempering temperature is lower than 700 C, the upper layer of cobalt metal silicide layer There will be no blockiness. At the same time, it can protect the nickel metal silicide layer from damage caused by Dianzhongzhong, and the overall sheet resistance of the cobalt / nickel double-layer metal silicide will not increase. buckle

1222141

V. Description of the invention (8) That is, 'the contact resistance is kept low. In addition, the nickel-metal oxide thick layer in the lower layer, as described in the conventional technology, can avoid the phenomenon that the sheet resistance increases due to the narrow line width effect. Second Embodiment A method for forming a semiconductor device having a self-aligned (se 1 f-al igned) double-layered metal silicide layer structure according to a second embodiment of the present invention is described below with reference to FIGS. 2a to 2d. First, please refer to FIG. 2a, and provide a silicon substrate 20, such as a stone evening sphere. It has an active area and an isolation structure 28, such as a shallow trench isolation structure, surrounding the active area. The active region has a semiconductor element, such as a MOS transistor, which includes a source region 21, a drain region 23, and a gate structure. Here, the gate structure includes a gate dielectric layer 2 2, a gate 24, and a gate spacer 26. Among them, the line width of the gate electrode 24 may be less than 65 nm. Next, please refer to FIG. 2b. Using conventional deposition techniques, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), in the isolation region 28 and the source region 21 and the drain region of the active region A nickel metal layer 30 and a cobalt metal layer 32 are sequentially and compliantly deposited on the gate structure. In this embodiment, the nickel metal layer 30 is formed by chemical vapor deposition, and its thickness is in the range of 100˜200 Angstroms. Furthermore, the cobalt metal layer 32 is also formed by chemical vapor deposition, and its thickness is in the range of 50 to 200 angstroms. Next 'please refer to Figure 2c and heat-treat the silicon substrate 20 in Figure 2b', such as using a conventional tempering furnace tube method or rapid thermal tempering (RTA) 'to make the nickel metal layer 30 and a cobalt Nickel atoms in the metal layer 32 and

1222141 V. Description of the invention (9) Initial atom diffusion to source region 21 of active region, drain region 23, and gate 24 of gate structure to form cobalt / nickel in source region 21 and drain region 23 A double metal silicide 33 and a cobalt / nickel double metal silicide 35 are formed on the gate 24. Here, the cobalt / nickel double-layer metal silicide 33 includes a nickel metal silicide layer 30b located above the source region 21 and the drain region 23, and a cobalt metal silicide layer 32b ′ is located at the nickel metal oxide layer 3 〇b 上. Similarly, the start / nickel double-layer metal silicide 35 includes a nickel metal silicide layer 30a above the source gate 24, and a cobalt metal silicide layer 32a above the nickel metal silicide layer 30a. Furthermore, a primary nickel oxide layer (not shown) is formed at the interface between the nickel metal silicide layers 30a and 301) and the cobalt metal silicide layers 323 and 3 2 b. In this way, the semiconductor device with a self-aligned metal silicide double-layer structure of the present invention is completed. In this embodiment, a rapid thermal tempering process is performed on the silicon substrate 20 to form the start / record double-layer metal stone compounds 33 and 35. The temperature of the rapid thermal tempering process is in the range of 350 ~ 550 C. And the time of rapid thermal tempering is in the range of 10 ~ 60 seconds. As described in the first embodiment, under this tempering condition, the sheet resistance of the metallization layer 18 is relatively high, but no agglomeration will occur. Next, the non-silicided cobalt metal layer 32 and nickel metal layer ® 30 above the isolation structure 28 and the gate spacer 26 are selectively removed by plasma etching or a suitable solution. In this embodiment, the cobalt metal layer 32 and the nickel metal layer 30 are removed by using a mixed solution (s ρ μ) of sulfuric acid and hydrogen peroxide. Finally, please refer to Fig. 2d ', a dielectric layer 36 is formed on the square of Shi Xi substrate 20 in Fig. 2c, and the material can be: plasma silicon oxide, low dielectric constant spin.

0503-9975TW (Nl); TSMC2003-0015; Spin.ptd 1222141 V. Description of the Invention (ίο) Coated glass (SOG), tetraethoxy silicon glass (TEOS oxide), scale-doped silicon oxide, fluorosilica glass ( FSG), Phosphor-Silicon Glass (PSG), undoped silica glass (HDP-USG) deposited by high-density plasma, silicon oxide (HDP-Si02) deposited by high-density electrodeposition, sub-pressure chemical vapor deposition (SACVD) and silicon oxide deposited by ozone-tetraethoxy silicon sintering (Os-TEOS). Next, by the conventional plasma etching process, a contact window 37 is formed in the dielectric layer 36 above the source region 21 and the drain region 23, and a contact is formed in the dielectric layer 36 above the gate 24. The window 39 exposes the initial / nickel double metal silicides 33 and 35. If the plasma etching process contains fluorine, it will easily bond with the nickel atoms in the nickel metal silicide layers 30a and 30b to increase the sheet resistance value and increase the contact resistance, as described previously. Therefore, the cobalt metal silicide layers 32a and 32b formed above the nickel metal silicides 30a and 305 ^ can be used as a protective layer to increase the contact resistance. Similarly, as described in the first embodiment, > In order to reduce the overall sheet resistance of the initial / zinc layer metal silicides 33 and 35, it is preferably 5% to 30%, and preferably 15%. also

A cross-section diagram of a double-conductor + conductor arrangement according to a second embodiment of the present invention having gold. This semiconductor Shi Xi substrate, such as a Shi Xi wafer, has: : = W isolation structure 28 ′ < column like shallow trench isolation structure two-moving :: body element, such as one, transistor, which contains-source moving electrode = one-: pole conduction

1222141 V. Description of the invention (11) Zone 23 and a gate structure. Here, the gate structure includes a gate dielectric layer 22, a gate 24, and a gate spacer 26. Cobalt / nickel double-layer metal silicides 35 and 33 are disposed on the gate 24 and the source region 21 / drain region 23, respectively. Among them, nickel metallization layers 30b and 30a are located above gate 24 and source region 21 / inverter region 23, respectively, and cobalt metal silicide layers 32b and 32a are located above nickel metal silicide layers 30b and 30a, respectively. Here, the thicknesses of the cobalt metal silicide layers 32b and 32a are 5% to 30%, and preferably 15%, of the thicknesses of the initial / nickel double-layer metal silicides 33 and 35, respectively.

As described in the first embodiment, in the cobalt / nickel double-layer metal silicide of the present invention, the thin metal silicide layer which is located on the upper layer will not be agglomerated. At the same time, it can protect the nickel metal silicide layer from being damaged by the fluorinated plasma and keep low contact resistance. Furthermore, the thick layer of nickel metallization in the lower layer can avoid the rise of the sheet resistance caused by the narrow line width effect. Therefore, it can be applied to the process of very small line width. … Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the invention. Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of an invention § is determined by the scope of the attached patent application.

1222141

Figures 1a to 1b are schematic cross-sectional views of a process for forming a metal silicide double-layer structure on a silicon substrate according to a second embodiment of the present invention. Figures 2a to 2d are schematic cross-sectional views illustrating a process for forming a semiconductor device having a self-aligned metal silicide double-layer structure according to a second embodiment of the present invention. Explanation of symbols: 10, 20 to silicon substrate; 12, 30 to nickel metal layer; 14, 32 to initial metal layer; 16, 30a, 30b to nickel metal silicide layer; 18, 32a, 32b to cobalt metal silicide layer; 19, 33, 35 ~ Cobalt / Ni double-layer metal silicide; 21 ~ Source region; 2 2 ~ Gate dielectric layer; 2 3 ~ Drain region; 2 4 ~ Gate; 2 6 ~ Gate gap 28 ~ isolated structure; 36 ~ dielectric layer; 37, 39 ~ contact window.

Claims (1)

1222141 Six 'patent application scope1. A metal silicide double-layer structure including a silicon substrate; and a cobalt / nickel double metal silicide disposed on the silicon substrate, wherein the cobalt / nickel double metal silicide includes A nickel metallization layer is located above the silicon substrate, and a metal silicidation layer is located above the nickel metallization layer. 2. The metal silicide double-layer structure as described in item 1 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 5% to 30% of the thickness of the cobalt / nickel double metal silicide. 3. The metal silicide double-layer structure as described in item 1 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 15% of the thickness of the cobalt / nickel double metal silicide. 4. The metal silicided double-layer structure according to item 1 of the scope of the patent application, wherein the cobalt / nickel double-layer metal silicide is formed by simultaneously performing a heat treatment on the nickel / cobalt double-layer metal on the silicon substrate. · 5 · The metal silicided double-layer structure according to item 4 of the scope of the patent application, wherein the thickness of the nickel metal layer is in the range of 100 to 200 angstroms. 6. The metal silicided double-layer structure as described in item 4 of the scope of patent application, wherein the thickness of the cobalt metal layer is in the range of 50 to 200 angstroms. 7. The metal silicided double-layer structure as described in item 4 of the scope of patent application, wherein the temperature of the heat treatment is in the range of 350 ~ 550 ° C. 8. The metal silicided double-layer structure as described in item 4 of the scope of patent application, wherein the heat treatment time is in the range of 10 to 60 粆. 9 · A method for forming a metal silicided double-layer structure, including the following steps 0503-9975TWF (Nl); TSMC2003-0015; Spin.ptd Page 18 Provide a silicon substrate; sequentially and compliantly deposit a nickel metal layer and a cobalt metal layer on the stone substrate; and perform a heat treatment on the 4th substrate to form a cobalt / recorded double layer on the silicon substrate Metal silicide. The method of forming a metal silicided double-layered junction as described in item 9 of the scope of the patent application, wherein the thickness of the nickel metal layer is in the range of 100 to 200 angstroms. Structure 1 2 · The method for forming a metal silicided double-layered junction as described in item 9 of the scope of the patent application, wherein the thickness of the cobalt metal layer is in the range of 50 to 200 angstroms. Structure 1 2 · The method for forming a metal silicided double-layered junction as described in item 9 of the scope of the patent application, wherein the heat treatment is a rapid thermal tempering treatment. 1 3 · The ancient and earth-forming method for forming a metal silicided double-layer structure as described in item 12 of the scope of the patent application, wherein the temperature of the rapid thermal tempering is in the range of 3 50 ~ 550 ° C. 14 · The metal silicided double-layered structure t, soil times as described in item 12 of the scope of the patent application, wherein the time of the rapid thermal tempering treatment is in the range of 10 to 60 seconds. 2 1 5 · The method for forming a metal silicided double-layer junction as described in item 9 of the scope of the patent application, wherein the thickness of the cobalt metal silicided layer is 5% to 30% of the thickness of the cobalt / nickel double-layered metal oxide %. 16. The method for forming a metal silicided double-layer junction as described in item 9 of the scope of the patent application, wherein the thickness of the cobalt metal silicided layer is 15/0 of the thickness of the cobalt / nickel double-layer metal petrified compound. 1222141 6. Scope of patent application 17. A semiconductor device with a metal silicide double-layer structure, including: Shi Xi substrate 'which has a gate and a source / dead region; and And is disposed on the gate and the source // and electrode regions, where the cobalt / nickel double-layer metal silicide includes a nickel metal petrified layer is located above the gate and the source / non-electrode regions. , And Yiqin metallization layer is located above the nickel metal silicide layer. Surname 1 8 · The semiconductor device with a metal silicide double-layer structure as described in item 17 of the scope of patent application, wherein the thickness of the cobalt metal silicide layer is 5% of the thickness of the cobalt 30%. 19 · The semiconductor device having a metal silicide double-layer structure as described in item 7 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 5% of the thickness of the cobalt / nickel double metal silicide. 20 · The semiconductor device having a metal silicide double-layer structure as described in item 7 of the patent application scope, wherein the cobalt / nickel double-layer metal silicide is implemented simultaneously on the nickel / cobalt double-layer metal on the silicon substrate A heat treatment is formed. 21. The semiconductor device having a metal silicide double-layered structure as described in item 20 of the scope of patent application, wherein the thickness of the nickel metal layer is in a range of 100 to 200 angstroms. 22. The semiconductor device having a metal silicide double-layer structure as described in item 20 of the scope of the patent application, wherein the thickness of the cobalt metal layer is in a range of 50 to 200 angstroms. 23. Having a metal silicided double layer as described in item 20 of the scope of patent application 0503-9975TW (Nl); TSMC2003-0015; Spin.ptd Page 20 1222141 VI. Patent application structure semiconductor device, where the temperature of the heat treatment is in the range of 350 ~ 55 0 t. 24. The semiconductor device having a metal silicide double-layered structure as described in item 20 of the scope of the patent application, wherein the heat treatment time is in the range of 10 to 60 seconds. A method for conducting a semiconductor device includes the following steps: providing a silicon substrate having a gate and a source / drain region; and sequentially and compliantly depositing a nickel metal layer and a cobalt metal layer on the silicon substrate And performing a heat treatment on the silicon substrate to form a cobalt / nickel double-layer metal silicide on the gate and the source / inverted regions. 26. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of the patent application, further comprising removing the non-lithified junction metal layer and the nickel metal layer. 27. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 26 of the scope of the patent application, wherein the cobalt metal layer and the nickel metal layer are removed by a sulfuric acid and hydrogen peroxide mixed liquid (SPM). 28. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the nickel metal layer is in the range of 100 to 200 angstroms. 29. The method for forming a semiconductor device with a metal sanded double-layer structure as described in item 25 of the scope of the patent application, wherein the cobalt metal layer has a thickness in the range of 50 to 200 angstroms. a 1222141 VI. Scope of patent application 30. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of patent application, wherein the heat treatment is a rapid thermal tempering process. 31. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 30 of the scope of the patent application, wherein the temperature of the rapid thermal tempering process is in the range of 350 to 550 X :. 32. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 30 of the scope of the patent application, wherein the time of the rapid thermal tempering treatment is in the range of 10 to 60 seconds. 33. The method for forming a semiconductor device with a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 5% of the thickness of the cobalt / nickel double metal silicide ~ 30 ° / 〇. 34. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 15% of the thickness of the cobalt / nickel double metal silicide . 0503-9975TW (Nl); TSMC2003-0015; Spin.ptd Page 22