TWI220462B - None-sticking detection method - Google Patents
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- TWI220462B TWI220462B TW92122399A TW92122399A TWI220462B TW I220462 B TWI220462 B TW I220462B TW 92122399 A TW92122399 A TW 92122399A TW 92122399 A TW92122399 A TW 92122399A TW I220462 B TWI220462 B TW I220462B
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Description
1220462 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種用於製造陣列模塑封裝構造(Μ AP (mold array p a c k a g e ))之銲不黏偵測方法。 【先前技術】 在晶片封裝製程中,打線接合(w i r e b ο n d i n g)係最常用 於晶片連接的技術。一般而言,半導體晶片與基板係利用 熱壓合銲接或超音波銲接將彼此連接。在習知封裝製程 中,半導體晶片一般係經由一膠層(e ρ ο X y )貼在一基板 上。然後利用前述打線接合技術,將鋅線(b ο n d i n g w i r e ) 連接至晶片表面的晶片銲墊以及基板上導電線路的手指。 最後,該晶片、銲線以及該基板之一部份(包括大部分的 導電線路)係為一封膠體包覆。 在上述封裝製程中,其一般必須在打線接合後檢測銲線 與晶片銲墊的電性連接是否良好,亦即進行銲不黏偵測。 習知的銲不黏偵測係利用人工以目視檢測的方法完成。然 而目視檢測無法達成所要的準確度。此外,在打線製程進 行中,無法以目視檢測的方法得知是否有銲不黏現象。因 此,目視檢測係在封裝構造完成後的可靠性測試 (r e 1 i a b i 1 i t y t e s t ) 時一併進行。假如在打線製程產生 問題,則所有後續製程步驟將是一種時間以及材料的浪 費。 因此,美國專利第5 7 1 2 5 7 0與5 8 9 3 5 0 8號揭示之一種在打 線製程進行時進行銲不黏偵測的方法,其係於打線製程進 行時施加電力於打線機的銲嘴(c a p i 1 1 a r y )上,並偵測是1220462 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a soldering non-stick detection method for manufacturing an array molding package structure (M AP (mold array p a c k a g e)). [Previous Technology] In the chip packaging process, wire bonding (w i r e b ο n d i n g) is the most commonly used technology for chip connection. Generally, a semiconductor wafer and a substrate are connected to each other by thermal compression bonding or ultrasonic welding. In the conventional packaging process, a semiconductor wafer is generally attached to a substrate via an adhesive layer (e ρ ο X y). Then, the aforementioned wire bonding technology is used to connect the zinc wires (b ο n d i n g w i r e) to the wafer pads on the surface of the wafer and the fingers of the conductive lines on the substrate. Finally, the wafer, bonding wires, and a portion of the substrate (including most of the conductive lines) are covered with a gel. In the above-mentioned packaging process, it is generally necessary to test whether the electrical connection between the bonding wire and the chip pad is good after wire bonding, that is, to detect non-stick soldering. The conventional welding non-stick detection is performed by manual visual inspection. However, visual inspection cannot achieve the required accuracy. In addition, during the wire bonding process, it is not possible to know whether there is no solder stickiness by visual inspection. Therefore, the visual inspection is performed at the same time as the reliability test (r e 1 i a b i 1 i t y t e s t) after the package structure is completed. If problems arise in the wire bonding process, all subsequent process steps will be a waste of time and material. Therefore, U.S. Patent Nos. 5 7 1 2 5 7 0 and 5 8 9 3 5 0 8 disclose a method for detecting non-stick welding during the wire bonding process, which involves applying power to the wire bonding machine during the wire bonding process. On the welding tip (capi 1 1 ary), and the detection is
00711.ptd 第6頁 1220462 五、發明說明(2) 否有回路(1 00 P)電流藉此判斷是否有銲不黏現象。然而, 美國專利第5 7 1 2 5 7 0與5 8 9 3 5 0 8號所揭示之方法均需於基板 上特別設計測試線路,因而增加基板上電路佈局(c i r c u i t 1 a y o u t)的困難度。此外,用於形成陣列模塑封裝構造 (MAP (mold array package))之基板片(substrate s t r i p ) —般包含複數個陣列排列之基板單元(一般為3 6個 基板單元或更多)。若要將上述習知方法應用於製造陣列 模塑封裝構造(M A P ( m ο 1 d a r r a y p a c k a g e )),則必須針對 每個基板單元設計測試線路,而這將大大增加增加基板上 電路佈局的困難度。 【發明内容】 本發明之主要目的係提供一種用於打線製程之銲不黏偵 測方法,其可克服或至少改善前述之先前技術問題。 根據本發明之銲不黏偵測方法係配合一已設有複數個半 導體晶片之基板片(substrate strip)實施,該基板片包 含複數個基板單元、複數條電鍍線(plat ing bar )設於該 複數個基板單元之間以及複數個連接於電鍍線之接墊,其 中該每一基板單元具有複數條導線(丨e a d s )直接連接至相 鄰的電鍍線。 根據本發明之銲不黏偵測方法係包含··( a )將該探針與 該複數個連接於電鍍線之接墊之一接觸;(b)形成一第一 銲線電性連接於該複數個半導體晶片之一與該複數條導線 (leads)之一;(c)利用一打線機(wire bonder)之録嘴 (cap i 11 ary )將一第二銲線之一第一端連接於該已電性連00711.ptd Page 6 1220462 V. Description of the invention (2) Whether there is a loop (1 00 P) current to judge whether there is welding non-stick phenomenon. However, the methods disclosed in U.S. Pat. Nos. 5 7 1 2 5 7 0 and 5 8 9 3 5 0 8 require special design of test lines on the substrate, thereby increasing the difficulty of the circuit layout (ci r c u i t 1 a y o u t) on the substrate. In addition, the substrate sheet (substrate s t r i p) used to form a MAP (mold array package) generally includes a plurality of substrate units (typically 36 substrate units or more) arranged in an array. If the above-mentioned conventional method is applied to fabricate an array molded package structure (M A P (m ο 1 d a r r a y p a c k a g e)), a test circuit must be designed for each substrate unit, which will greatly increase the difficulty of increasing the circuit layout on the substrate. SUMMARY OF THE INVENTION The main object of the present invention is to provide a soldering non-stick detection method for wire bonding process, which can overcome or at least improve the aforementioned prior technical problems. The welding non-stick detection method according to the present invention is implemented in conjunction with a substrate strip that has been provided with a plurality of semiconductor wafers. The substrate strip includes a plurality of substrate units, and a plurality of plating bars are provided in the substrate strip. Between the plurality of substrate units and the plurality of pads connected to the plating line, each substrate unit has a plurality of wires (eads) directly connected to adjacent plating lines. The welding non-stick detection method according to the present invention comprises: (a) contacting the probe with one of the plurality of pads connected to a plating line; (b) forming a first bonding wire to be electrically connected to the One of the plurality of semiconductor wafers and one of the plurality of leads; (c) using a cap i 11 ary of a wire bonder to connect a first end of a second bonding wire to The already electrically connected
00711.ptd 第7頁 1220462 五、發明說明(3) 接第一銲線之 探針之谓測器 以及(e ) 在該 步驟之後5檢 若該第二銲 好,則該探針 該與衩針接觸 線、該已電性 一端、 c i r c u i 時,若 良好, 電流則 片。可 量,則 狀態不 由於 電鍍線 不需大 程進行 根據 嘴將該 後檢查 前述 該銲嘴 t )。因 該第二 則該偵 代表該 以理解 代表該 良。 根據本 作為測 幅更改 時測出 本發明 第二銲 該偵測 之電力 半導體 ;(d) 第二銲 查該偵 線之第 、與探 之接墊 連接第 以及該 此,當 銲線之 測器可 弟一 4干 的是, 第二銲 晶片 施加 線第 測器 一端 針接 以及 一銲 偵測 打線機 土 一 rL 尤5又疋 之連接 偵測到 導體晶 接墊、 5該 一預 一端 是否 與半 觸之 該第 線之 器會形成 係電性連接於一具有 量的電 步驟以 電流 ° 力於該銲嘴; 及該探針接觸 片之間 該第一 一銲線之間的 半導體晶片、 施加一預先設定 第一端與半導體 到電流。反 端並未 到的電 端與半 偵測 線之 若所 線之 第一 偵測 第 的鲜接 銲線、 電鍍線 該第二 路(c 1〇 力於該 間的鲜 偵測不 閉合電 量的電 晶片之 之,若 銲接至該半導 流小於一預先 導體晶片之間 狀態良 連接在 以及導 銲線第 s e d 銲嘴 接狀態 到任何 體晶 -J-rL δ又疋 的銲接 發明之銲不黏偵測方法係利用基板片原有之 試線路,因此根據本發明之銲不黏偵測方法 基板上原有之電路佈局,而又可以在打線製 銲線與半導體晶片之間的銲接狀態。 之銲不黏偵測方法可另包含利用打線機之銲 線之一第二端連接於該複數條導線之一,然 器是否已偵測不到電流。 施加步驟可藉由將一電源(例如一直流或交00711.ptd Page 7 1220462 V. Description of the invention (3) The probe connected to the probe of the first bonding wire and (e) After this step 5 check if the second welding is good, the probe should be connected with When the needle touches the wire, the electrically charged end, and the circui, if the current is good, the current is sliced. If it can be measured, the state is not because the plating line does not need to be carried out according to the nozzle. Then check the welding tip t). Because the second investigative representative should understand the representative of the good. According to the change of the measurement range, the power semiconductor for the detection of the second welding of the present invention is measured; (d) the second detection of the detection wire, the connection with the probe pad and the measurement of the welding wire. What the device can do is that the end of the second welding chip application wire is pin-connected to the end of the tester, and a welding detection wire is connected to the wire, rL, especially 5 and the connection detects a conductor crystal pad, 5 a pre-end Whether a semi-touched device with the second wire is electrically connected to an electrical step with a quantity of force to the welding tip; and a semiconductor between the first and the bonding wire between the probe contact piece. The chip is applied with a preset first terminal and a semiconductor to the current. The opposite end of the electrical terminal and the half detection line, if the line is the first detection, the fresh welding wire, the electroplating line, the second circuit (c 10 force between the fresh detection and the non-closed battery). Among the electric wafers, if the semi-conducting current is less than that of a pre-conductor wafer, the state of the connection is good, and the state of the sed tip of the wire is connected to any body-J-rL δ. The non-stick detection method utilizes the original test circuit of the substrate sheet. Therefore, the original circuit layout on the substrate according to the soldering non-stick detection method of the present invention can also be used for the welding state between the bonding wire and the semiconductor wafer. The welding non-stick detection method may further include using a second end of a wire of the wire bonding machine to be connected to one of the plurality of wires, and whether the current is not detected by the device. The applying step may be performed by applying a power source (for example, One DC or AC
0071i.ptd 第8頁 1220462 五、發明說明(4) 流電源、或一電容器)電性連接在該録嘴與該探針之間而 達成。 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵,下文特舉本發明較佳實施例,並配合所附圖示, 作詳細說明如下。 [實施方式】 第1圖所示為用於本發明之基板片(s u b s七r a 1 e s t r i p ) 1 〇 〇,其包含複數個陣列排列之基板單元1 1 〇以及複 數條電鍍線(plating bar ) 120設於該複數個基板單元 之間。該基板片1 0 0設有複數個連接於電鍍線1 2 0之接塾 1 2 4。該每一基板單元1 1 〇之上表面係設有複數條導線 (1 eads) 11 2。如第1圖所示,該每一條導線1 1 2之第一端部 1 1 2 a係用以電性連接至一半導體晶片(未示於圖中)。該 每一條導線1 1 2之第二端部1 1 2 b係直接連接至相鄰的電鍍 線1 2 0。該每一個基板單元1 1 〇下表面設有複數個錫球銲墊 (未示於圖中),其分別電性連接至該基板單元上表面相 對應之導線1 1 2。 該基板片1 0 0之製程包含··( A )將一導電金屬層(例如經 過表面粗糙化的銅箔)以習用之方法(例如熱壓合法)層 壓(laminating)於一介電層(適合之介電材質如 BT(bismaleimide-triazine)樹脂或FR-4玻璃纖維強化環 氧樹月旨(fiberglass reinforced epoxy resin))之兩面 。 (B)在(A)之產物上形成介層洞(via)或通孔 (t hrough-ho 1 e ),其可以任何習知的方法形成,例如機械0071i.ptd Page 8 1220462 V. Description of the invention (4) A current source, or a capacitor) is electrically connected between the recording nozzle and the probe. In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention in detail with reference to the accompanying drawings. [Embodiment] FIG. 1 shows a substrate sheet (subs 7ra 1 estrip) 1 00 used in the present invention, which includes a plurality of substrate units 1 1 0 arranged in an array and a plurality of plating bars 120 Provided between the plurality of substrate units. The substrate sheet 100 is provided with a plurality of contacts 1 2 4 connected to the plating line 1 2 0. A plurality of wires (1 eads) 11 2 are provided on an upper surface of each substrate unit 1 10. As shown in FIG. 1, the first end portion 1 1 2 a of each of the wires 1 12 is used to be electrically connected to a semiconductor chip (not shown in the figure). The second end 1 1 2 b of each of the wires 1 1 2 is directly connected to the adjacent plated wire 1 2 0. A plurality of solder ball pads (not shown in the figure) are provided on the lower surface of each substrate unit 110, which are respectively electrically connected to corresponding leads 1 12 on the upper surface of the substrate unit. The manufacturing process of the substrate sheet 100 includes (A) laminating a conductive metal layer (such as copper foil with roughened surface) on a dielectric layer (for example, hot pressing). Suitable dielectric materials such as BT (bismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin (fiberglass reinforced epoxy resin) on both sides. (B) Formation of vias or through-holes in the product of (A), which can be formed by any conventional method, such as mechanical
00711.ptd 第9頁 1220462 五、發明說明(5) 鑽孔或雷射鑽孔。並且以習知的方法如無電極電鍍 (e 1 e c t r ο 1 e s s p 1 a t 1 n g )在該介層洞或通孔塗覆一層導電 金屬例如銅。(C )微影(p h 〇 t ο 1 i t h 〇 g r a p h y ) —預先設定圖 案(例如第1圖所示圖案)並且蝕刻(e t c h i n g )該導電金屬 層以形成所要之導電線路或導電區域。(D )將一可光顯像 的拒銲劑(p h〇t ο 1 m a g a b 1 e s ο 1 d e r m a s k )(未示於圖中) 覆蓋於(C)之產物表面,轉移所要之圖案,然後顯影使得 導線1 1 2之第一端部1 1 2 a、錫球銲墊以及該接墊12 4係裸露 於該拒銲劑;以及(E )將與習用連接線(b ο n d i n g w i r e )材 料結合力佳之材料例如金或鈀電鍍在未被拒銲劑覆蓋的導 電金屬層。值得注意的是’在步驟(E )中5該電鑛線1 2 0係 作為電鍍金或鈀層之電傳遞路徑。 在將複數個半導體晶片(只有一個半導體晶片200示於 第2圖)利用一膠層(例如環氧樹脂)固著於該基板片1 0 0 上之後,進行一打線製程包含:形成一球接合(b a 1 1 b ο n d )於該半導體晶片2 0 0之銲墊2 0 2 ;形成一線弧於銲墊 2 0 2與導線1 1 2之第一端部1 1 2 a間;最後形成一壓印接合 (s t i t c h b ο n d ) 至導線1 1 2之第一端部1 1 2 a而完成該銲線 之連接。 根據本發明之銲不黏偵測方法將配合前述打線製程詳述 於後。 首先,形成一第一銲線3 1 0電性連接於該半導體晶片2 0 0 之銲墊2 0 2與導線1 1 2之第一端部1 1 2 a。可以理解的是,該 第一銲線3 1 0可以電性連接於該半導體晶片2 0 0上的任何地00711.ptd Page 9 1220462 V. Description of the invention (5) Drilling or laser drilling. And, a conventional method such as electrodeless plating (e 1 e c t r ο 1 e s s p 1 a t 1 n g) is used to coat the via or via with a conductive metal such as copper. (C) Lithography (p h 0 t ο 1 i t h 0 g r a p h y) — A pattern is set in advance (for example, the pattern shown in FIG. 1) and the conductive metal layer is etched (e t c h i n g) to form a desired conductive line or conductive area. (D) Cover a surface of the product of (C) with a photoimageable solder resist (ph〇t ο 1 magab 1 es ο 1 dermask) (not shown), transfer the desired pattern, and develop to make the wire 1 1 2 The first end portion 1 1 2 a, the solder ball pad and the pad 12 4 are exposed to the solder resist; and (E) a material having a good bonding force with a conventional connecting wire (b ο ndingwire) material such as Gold or palladium is plated on a conductive metal layer that is not covered by the solder resist. It is worth noting that 'in step (E) 5 the electric ore line 120 is used as an electric transmission path for the electroplated gold or palladium layer. After a plurality of semiconductor wafers (only one semiconductor wafer 200 is shown in FIG. 2) are fixed on the substrate sheet 100 using an adhesive layer (such as epoxy resin), a wire-making process is performed including: forming a ball joint (Ba 1 1 b ο nd) on the semiconductor wafer 2 0 2 pads 2 0 2; forming a line arc between the pad 2 2 and the first end 1 1 2 a of the wire 1 1 2; finally forming a Stamp bonding (stitchb ο nd) to the first end portion 1 1 2 a of the wire 1 1 2 to complete the connection of the bonding wire. The welding non-stick detection method according to the present invention will be described in detail with the aforementioned wire bonding process. First, a first bonding wire 3 1 0 is electrically connected to the bonding pad 2 2 of the semiconductor wafer 2 0 and the first end portion 1 1 2 a of the lead 1 12. It can be understood that the first bonding wire 3 1 0 can be electrically connected to any ground on the semiconductor wafer 2 0 0
00711.ptd 第10頁 1220462 五、發明說明(6) 方包括直接銲在晶片表面上,只要該第一銲線3 1 0可以在 該半導體晶片與導線1 1 2之間形成電性連接即可。 接著,利用一打線機(w i r e b ο n d e r )之銲嘴(c a p i 1 1 a r y ) 4 0 0將一第二銲線3 2 ϋ之一第一端3 2 0 a連接於該已電性連接 第一銲線3 1 0之半導體晶片2 0 0上。詳細言之,前述製程係 包含先在由銲嘴4 0 0拉出的銲線末端形成一球體,再加熱 且按壓該球體在銲墊2 0 2上,藉此將該第二銲線3 2 0第一端 形成之球體接合在半導體晶片2 0 0之銲墊2 0 2上。銲線球體 與銲墊2 0 2之間的附著力可以在球體接釜時藉由施以超音 波而增加。 值得注意的是,該打線機係電性連接於一具有探針4 1 0 之偵測器4 2 0。在將該探針4 1 0與該接墊1 2 4接觸之後(可 以理解的是,該探針4 1 0與接墊1 2 4可以在打線製程一開始 時便接合在一起),若該第二銲線320之第一端與半導體 晶片之銲墊2 0 2間的銲接狀態良好,如第3圖所示,該探針 4 1 0、與探針接觸之接墊1 24、該第一銲線3 10、連接在該 與探針接觸之接墊以及該第一銲線之間的電鍍線1 2 0以及 導線1 1 2、該已電性連接第一銲線之半導體晶片2 0 0、該第 二銲線3 2 0、該銲嘴4 0 0以及該偵測器4 2 0會形成一閉合電 路(closed circuit)。因此,當一預先設定量的電力被施 加於該銲嘴時(例如可在測試機台中裝設有一電池,而當 該第二銲線3 2 0之第一端與半導體晶片之銲墊2 0 2間接觸 時,電池便會提供電流),若該第二銲線3 2 0之第一端與 半導體晶片之銲墊2 0 2之間的銲接狀態良好,則該偵測器00711.ptd Page 10 1220462 V. Description of the invention (6) The method includes soldering directly on the surface of the wafer, as long as the first bonding wire 3 1 0 can form an electrical connection between the semiconductor wafer and the wire 1 1 2 . Next, a first end 3 2 0 a of a second bonding wire 3 2 利用 is connected to the first end 3 2 0 a of a second bonding wire 3 2 利用 by a capi 1 1 ary of a wireb ο nder. The bonding wire 3 1 0 is on a semiconductor wafer 2 0 0. In detail, the aforementioned process includes forming a sphere at the end of the welding wire drawn by the welding tip 400, and then heating and pressing the sphere on the welding pad 2 02, thereby the second welding wire 3 2 is formed. The ball formed at the first end of 0 is bonded to the pad 2 2 of the semiconductor wafer 2 0 0. The adhesion between the bonding wire sphere and the bonding pad 202 can be increased by applying an ultrasonic wave when the sphere is connected to the kettle. It is worth noting that the wire printer is electrically connected to a detector 4 2 0 having a probe 4 1 0. After contacting the probe 4 1 0 with the pad 1 2 4 (it can be understood that the probe 4 10 and the pad 1 2 4 can be joined together at the beginning of the wire bonding process), if the The soldering state between the first end of the second bonding wire 320 and the pad 2 2 of the semiconductor wafer is good. As shown in FIG. 3, the probe 4 10, the pad 1 24 in contact with the probe, and the first A bonding wire 3 10, a plating line 1 2 0 and a lead 1 1 connected between the pad in contact with the probe and the first bonding wire 2 The semiconductor wafer 2 0 electrically connected to the first bonding wire 0, the second bonding wire 3 2 0, the welding tip 4 0 0 and the detector 4 2 0 will form a closed circuit. Therefore, when a predetermined amount of power is applied to the welding tip (for example, a battery may be installed in the test machine, and when the first end of the second bonding wire 3 2 0 and the bonding pad 2 of the semiconductor wafer are 0 When the two contacts are in contact, the battery will supply current.) If the welding state between the first end of the second bonding wire 3 2 0 and the pad 2 of the semiconductor wafer is good, the detector
00711.ptd 第11頁 1220462 五、發明說明(7) 4 2 0可偵測到一電流。反之,若偵測不到任何電流則代表 該第二銲線3 2 0之第一端並未銲接至該半導體晶片。此 夕卜,根據本發明之銲不黏偵測方法亦可利用一電流計測量 測試線路中的電流強度,若所偵測到的電流小於一預先設 定量,則代表該第二銲線3 2 0之第一端與半導體晶片之間 的銲接狀態不良。前述之電力施加步驟亦可藉由將一交流 電4或一電容器電性連接在該銲嘴與該探針之間而達成。 可以理解的是,該電源可以整合於該偵測器4 2 0或打線機 内,或外接於該銲嘴4 0 0與該探針4 1 0之間。 參見第4圖,在將該第二銲線3 2 0之第一端3 2 0 a連接於晶 片2 0 0之後,銲線3 2 0係被該銲嘴4 0 0導引至該導線1 1 2之第 一端部1 1 2 a,然後將該第二銲線3 2 0之第二端3 2 0 b壓印接 合至該導線1 1 2之第一端部1 1 2 a。在壓印接合完成後,剩 餘的銲線會被切斷,藉此完成銲線3 2 0之打線作業。由於 銲線被切斷後會形成開路(0 p e n C i r c u i t ),因此即使施加 一預先設定量的電力於該銲嘴,若銲線被確實切斷,則該 偵測器4 2 0應無法偵測任何電流。若仍可偵測到電流,則 代表發生銲不黏現象。由於根據本發明之銲不黏偵測方法 係利用基板片原有之電鍍線1 2 0作為測試線路。因此根據 本發明之銲不黏偵測方法之優點為完全不需大幅更改基板 上原有之電路佈局,而又可以在打線製程進行時測出銲線 與半導體晶片之間的銲接狀態。 雖然本發明已以前述較佳實施例揭示,然其並非用以限 定本發明,任何熟習此技藝者,在不脫離本發明之精神和00711.ptd Page 11 1220462 V. Description of the invention (7) 4 2 0 can detect a current. Conversely, if no current is detected, it means that the first end of the second bonding wire 3 2 0 is not soldered to the semiconductor wafer. In addition, according to the welding non-stick detection method of the present invention, a current meter can also be used to measure the current intensity in the test circuit. If the detected current is less than a preset amount, it represents the second welding wire 3 2 The soldering state between the first end of 0 and the semiconductor wafer is not good. The aforementioned power application step can also be achieved by electrically connecting an alternating current 4 or a capacitor between the welding tip and the probe. It can be understood that the power supply can be integrated in the detector 4 200 or the wire-bonding machine, or externally connected between the welding tip 4 0 0 and the probe 4 1 0. Referring to FIG. 4, after connecting the first end 3 2 0 a of the second bonding wire 3 2 0 to the wafer 2 0, the bonding wire 3 2 0 is guided to the wire 1 by the welding tip 4 0 0. The first end portion 1 1 2 a of 1 2 is then embossed and bonded to the first end portion 1 1 2 a of the second bonding wire 3 2 0 3 2 0. After the embossing is completed, the remaining welding wire will be cut off, thereby completing the bonding operation of the welding wire 320. Because the welding wire is cut off, an open circuit (0 pen C ircuit) will be formed. Therefore, even if a predetermined amount of power is applied to the welding tip, if the welding wire is cut off, the detector 4 2 0 should not be able to detect Any current. If the current can still be detected, it means that the welding is not sticking. Since the welding non-stick detection method according to the present invention uses the original plating line 120 of the substrate sheet as a test circuit. Therefore, the welding non-stick detection method according to the present invention has the advantage that the original circuit layout on the substrate does not need to be greatly changed, and the welding state between the bonding wire and the semiconductor wafer can be measured during the wire bonding process. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention.
00711.ptd 第12頁 122046200711.ptd Page 12 1220462
00711.ptd 第13頁 1220462 圖式簡單說明 【圖式簡單說明】 第1圖:用於本發明之基板片之上視圖; 第2圖:其係用以說明根據本發明一實施例之銲不黏偵 測方法; 第3圖:用以顯示本發明銲不黏偵測方法之偵測電路的 電路方塊圖;及 第4圖:其係用以說明根據本發明另一實施例之銲不黏 偵測方法。 圖號 說明: 100 基 板 片 1 10 基 板 ασ 早 元 120 電 鍍 線 124 接 墊 112 導 線 1 12a 第 一 端 部 112b 第 —— 端 部 200 半 導 體 晶片 202 銲 墊 310 第 一 銲 線 320 第 二 銲 線 3 2 0 a 第 一 端 3 2 0 b 第 端 400 銲 嘴 420 偵 測 器00711.ptd Page 13 1220462 Brief description of the drawings [Simplified description of the drawings] Figure 1: Top view of the substrate sheet used in the present invention; Figure 2: It is used to explain the welding according to an embodiment of the present invention Sticky detection method; Figure 3: a circuit block diagram showing a detection circuit of the soldering non-sticky detection method of the present invention; and Figure 4: it is used to illustrate soldering non-stickyness according to another embodiment of the present invention Detection method. Description of drawing number: 100 substrate piece 1 10 substrate ασ early 120 plating line 124 pad 112 wire 1 12a first end 112b first-end 200 semiconductor wafer 202 pad 310 first wire 320 second wire 3 2 0 a First end 3 2 0 b First end 400 Welding tip 420 Detector
00711.ptd 第14頁00711.ptd Page 14
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| TWI665771B (en) * | 2014-10-31 | 2019-07-11 | 矽品精密工業股份有限公司 | Non-sticking testing method and substrate used by the method |
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