1299567 19$47twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種非揮發性記憶體及其製造方 法，且特別是有關於一種相變化記憶體及其製造/方^。 【先前技術】 隨著半導體技術不斷的更新演進，記憶體元件的製程 也快速往物理極祕進。其巾，機化記憶體(phase change =7〇ry，PCM)具備小體積、低耗電、讀寫速度快與高容 篁密度等優點，是目前極力發展的非揮發性記憶體元件之 圖4為繪示習知一種相變化記憶體的剖面示音圖。相 變化記憶體彻包括下電極術、介電層姻、力=熱電極 410、相變化材料層4〇6以及上電極4〇8。其中，上電極*⑽ ^於下電極術上。介電層姻配置於上電極柳與下 ^極402之間。相變化材料層概配置於上電極撕^介 ，層404之間。加熱電極41〇配置於介電層4〇4中，^加 熱電極4U)分別與下電極術以及相變化材料層條接 ^ °相變化記憶體400可利用相變化材料層4〇6做為記 亥心，並透過電流加熱使這種材料發生溫度變化，如此^ =使此類㈣在結晶態與非㈣之間不停轉換，亦即能 產生不同的電阻值來進行記憶功能。 而，習知之相變化記憶體的結晶態_非晶態之轉換速 二目虽快速，如此一來在施加極小的電壓情況下，即會使 =相變化記憶體從T變成1 ”或”i，，變AT，而無法^ 交化記憶體做為多階(multi-level)使用。 !299567 19547twf.doc/e 【發明内容】 有鑑於此，本發明的目的1299567 19$47twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory and a method of manufacturing the same, and more particularly to a phase change memory and its manufacture/ Fang ^. [Prior Art] With the continuous evolution of semiconductor technology, the process of memory components is also rapidly moving toward physics. Its towel, computerized memory (phase change = 7〇ry, PCM) has the advantages of small size, low power consumption, fast reading and writing speed and high capacity density. It is a map of non-volatile memory components that are currently under development. 4 is a cross-sectional sound map of a phase change memory. The phase change memory includes the lower electrode, the dielectric layer, the force = the hot electrode 410, the phase change material layer 4〇6, and the upper electrode 4〇8. Among them, the upper electrode * (10) ^ on the lower electrode. The dielectric layer is disposed between the upper electrode and the lower electrode 402. The phase change material layer is disposed between the upper electrode tearing layer and the layer 404. The heating electrode 41 is disposed in the dielectric layer 4〇4, and the heating electrode 4U) is respectively connected to the lower electrode and the phase change material layer. The memory 400 can be used as the memory layer 4〇6. Haixin, and through the current heating to make this material temperature change, so ^ 4 such (4) between the crystalline state and non-(four) constantly switching, that is, can produce different resistance values for memory function. However, the phase change memory of the phase change memory of the conventional phase is fast, so that when a very small voltage is applied, the phase change memory is changed from T to 1 or "i". ,, change to AT, and can not be used as a multi-level use. !299567 19547twf.doc/e SUMMARY OF THE INVENTION In view of the above, the object of the present invention
駚7 ^疋在&供一種相變化記愔 體’此夠使相變化記憶體做為多階使用。 又^己U 本發明的另一目的是提供一 1、種相變化記憶體的生 方法，此夠‘造多階之相變化記憶體。 又k 本發明提出-種相變化記憶體，其包 電層、加執電極、導，P气臨、后在Λ 、 電極、介 4，下；=署=相變化材料層以㈣^ . 置在基底上。介電層配置於下電極上。加 雜“办〜 熱電極的底部與下電極相接 t且加熱電極_部表面高於介電層_部表面。另外， ¥體間隙壁配置於加熱電極的側壁，且位於介電層上，其 中‘體間隙壁的電阻值高於加熱電極的電阻值。相變化材 料層配置於介電層上，且覆蓋導體_壁與加熱電極。上 電極配置在相變化材料層上。 依妝本發明的貫施例所述之相變化記憶體，其中導體 間隙壁的材質例如是氮化鈦、氮她或氮化欽铭。、 依照本發明的實施例所述之相變化記憶體，其中相變 化材料層例如是一硫屬化合物層（chalcogenide)。 依照本發明的實施例所述之相變化記憶體，其中加熱 電極的材質例如是鎢。 其中上， 依照本發明的貫施例所述之相變化記憶體 極例如是金屬層。 其中下 依照本發明的貫施例所述之相變化記憶體 極例如是金屬層。 1299567 19547twf.doc/e 的實施_狀相變化記《，A中介電 層的材貝例如是氧化矽或氮化矽。 /、中；〖電 本每明提出一種相變化記憶體的製造方法，此制、4 法例如是，先在基底上依序形成下電二二 層中形成有底《露訂t極表_接觸且介電 電r加熱電極的頂部表面高於;電:: :導體間隙壁的電阻值高於加熱電極的=間= ;|電層上形成相變化材料層，^ ; 隙壁與力姻極。然後，在相變;=層覆蓋導體間 «本發明的實施例所相述=二:方 t其中導《_的材質例如是氮化故、氮化组或氮化 、，照本發明的實施例所述之相變化記憶體的製 法，其中導體m鐘的形成方法例如是，於介 = =導體材料層，然後進行一靖程:移;;‘ 材料層，以形成之。 |刀夺聪 法，自《的製造方 依照本發明的實施綱述之相變化記紐的勢造 法，其中加熱電極的形成方法例如是，於介電層上 =電極材料層，且填滿接觸f，而此加熱電極材料層^ 貝例如是鎮。紐，進行—平垣化製程，以移除部分加= 1299567 19547twf.doc/e 電極材料層，至暴露出介電層表面。 法 層’使加熱電極的頂部表面高於=著’移除部分介電 依照本發明的實施例所述 ^的頂部表面。。 其中下電極例如是金屬層。’欠化纪憶體的製造方 法 依照本發明的實施例所述之 ，其中上電極例如是金屬層。夂化纪憶體的製造方 法 依照本發明的實施例所述 其中介電層的材質例如是氧體的製造方 本發明之相變化記情體 次虱化矽。 間隙壁，料體_義電阻值配置有導體 因此在70件操作過程尹，可使得相變化的電阻值， 變化情形，而能夠做為多階使用。文化心隱體具有兩段相 為讓本發明之上述和其他目的、特 ί懂’下文特舉實施例’並配合所附圖 【實施方式] 圖1為依照本發明一實施例所緣 剖面示意圖。 <相、交化記憶體的 本實施例之相變化記憶體100包括： 電層刚、加熱電極⑽、導體間隙壁 =102、介 no以及上電極112。 相受化材料層 其中，上箪極102配置於基底(未繪示 例如是金屬層。介電層104配置於下電極搬；^極102 刚的材質例如是氮化石夕、氧化石夕或其他合適之^二 1299567 料。加熱電極106配置於介電層1〇4中，且加熱電極川6 的j部與下電極102相接觸，加熱電極1〇6的頂部表面高 於介電層104的頂部表面。加熱電極106的材質例如是鎢。 ^體間隊2 1⑽配置於加熱電極106的侧壁，且位於 介電層^104上。導體間隙壁1〇8的材質例如是氮化鈦 (ΤιΝ)、氮化组(TaN)或氮化鈦銘(ΉΑ1Ν)。而且，導體間隙 壁108的電阻值高於加熱電極1〇6的電阻值。 另外’相變化材料層110配置於介電層104上，且覆 盍導體間隙壁108與加熱電極106。相變化材料層11〇例 如疋硫屬化合物層（chalCOgenide)，其可例如是二元材料 層、三元材料層或多元材料層。其中，二元材料層的材質 例如是銻化銦(InSb)、銻化鎵(GaSb)、硒化銦(InSe)、銻化 碲(Sb2!^)或銻化鍺(GeTe);三元材料層的材質例如是銻化 碲鍺(GQSbJe5)、銻化碲銦(InSbTe)、銻化碲鎵((^%1^)、 銻化碲錫(SnSbTe4)或鍺化銻銦(InSbGe);多元材料層的材 質例如是 AgluSbTe、（Ge，Sn)SbTe、GeSb(SeTe)或駚 7 ^ 疋 in & for a phase change record 此 this enough to make phase change memory as a multi-stage use. Further, another object of the present invention is to provide a method for producing a phase change memory, which is sufficient to create a multi-order phase change memory. Further, the present invention proposes a kind of phase change memory, such as an electric charge layer, an additive electrode, a lead, a P gas, a post electrode, an electrode, a dielectric layer, a lower layer, a lower phase, a phase change material layer, and a (four) layer. On the substrate. The dielectric layer is disposed on the lower electrode. The bottom of the hot electrode is connected to the lower electrode and the surface of the heating electrode is higher than the surface of the dielectric layer. In addition, the bulk spacer is disposed on the sidewall of the heating electrode and on the dielectric layer. Wherein the resistance value of the bulk wall is higher than the resistance value of the heating electrode. The phase change material layer is disposed on the dielectric layer and covers the conductor wall and the heating electrode. The upper electrode is disposed on the phase change material layer. The phase change memory of the embodiment, wherein the material of the conductor spacer is, for example, titanium nitride, nitrogen or nitriding. The phase change memory according to the embodiment of the invention, wherein the phase change The material layer is, for example, a chalcogenide. The phase change memory according to the embodiment of the invention, wherein the material of the heating electrode is, for example, tungsten. wherein, the phase according to the embodiment of the present invention The change memory electrode is, for example, a metal layer. The phase change memory electrode according to the embodiment of the present invention is, for example, a metal layer. 1299567 19547twf.doc/e Implementation _ phase change record ", A dielectric The material shell is, for example, yttrium oxide or tantalum nitride. /, medium; 〖Electricity each proposed a method for manufacturing phase change memory, this method, 4 method, for example, first form a second power on the substrate The bottom surface of the layer is formed with a bottom surface and the top surface of the dielectric electrode is higher than the upper surface of the electrode; the electrical:: : the resistance value of the conductor spacer is higher than that of the heating electrode =; Varying material layer, ^; gap wall and force marriage. Then, in the phase change; = layer covering the conductor «the embodiment of the invention is said = two: square t where the material of the "_ is, for example, nitrided, Nitriding or nitriding, according to the method for fabricating a phase change memory according to an embodiment of the present invention, wherein the forming method of the conductor m clock is, for example, a layer of conductor material, and then performing a process: shifting; a material layer formed to form a method of forming a phase change of a phase change according to an embodiment of the present invention, wherein a method of forming a heating electrode is, for example, on a dielectric layer = electrode material layer, and fills the contact f, and the layer of the heating electrode material is, for example, a town. Flattening the process to remove a portion of the electrode material layer = 1299567 19547 twf.doc / e to expose the surface of the dielectric layer. The layer 'make the top surface of the heating electrode higher than = 'removing part of the dielectric according to the present invention The top surface of the embodiment is: wherein the lower electrode is, for example, a metal layer. The method of manufacturing the underlying memory is in accordance with an embodiment of the invention, wherein the upper electrode is, for example, a metal layer. The manufacturing method of the body according to the embodiment of the present invention, wherein the material of the dielectric layer is, for example, the production of oxygen, the phase change of the present invention. The spacer, the material body has a conductor with a conductor Therefore, in 70 operating procedures, the phase change resistance value can be changed, and it can be used as a multi-stage. The present invention has two phases for the above and other objects of the present invention, and the following detailed description of the present invention is made in conjunction with the accompanying drawings. FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention. . <Phase and Crosslinked Memory The phase change memory 100 of this embodiment includes: an electric layer just, a heating electrode (10), a conductor spacer = 102, a dielectric no, and an upper electrode 112. The upper germanium 102 is disposed on the substrate (the unillustrated example is a metal layer. The dielectric layer 104 is disposed on the lower electrode; the material of the gate 102 is, for example, nitrided, oxidized, or other suitable The heating electrode 106 is disposed in the dielectric layer 1〇4, and the j portion of the heating electrode tube 6 is in contact with the lower electrode 102, and the top surface of the heating electrode 1〇6 is higher than the top of the dielectric layer 104. The material of the heating electrode 106 is, for example, tungsten. The interbody 2 1 (10) is disposed on the sidewall of the heating electrode 106 and is located on the dielectric layer 104. The material of the conductor spacer 1 〇 8 is, for example, titanium nitride (ΤιΝ). And a nitrided group (TaN) or a titanium nitride (ΉΑ1Ν). Moreover, the resistance value of the conductor spacer 108 is higher than the resistance value of the heating electrode 1〇6. Further, the 'phase change material layer 110 is disposed on the dielectric layer 104. And covering the conductor spacer 108 and the heating electrode 106. The phase change material layer 11 is, for example, a chalcogenide layer, which may be, for example, a binary material layer, a ternary material layer or a multi-material layer. The material of the binary material layer is, for example, indium antimonide (InSb) or gallium antimonide ( GaSb), indium selenide (InSe), antimony telluride (Sb2!^) or germanium telluride (GeTe); the material of the ternary material layer is, for example, germanium telluride (GQSbJe5), germanium telluride (InSbTe),锑 碲 gallium ((%%1^), bismuth telluride (SnSbTe4) or bismuth telluride (InSbGe); the material of the multi-material layer is, for example, AgluSbTe, (Ge, Sn) SbTe, GeSb (SeTe) or
TwGhSbJ2。另外，上電極丨12配置在相變化材料層j ι〇 上，上電極112例如是金屬層。 ’以圖1與圖2說明本發明之相變化記憶體的TwGhSbJ2. Further, the upper electrode 丨12 is disposed on the phase change material layer j ι , and the upper electrode 112 is, for example, a metal layer. The phase change memory of the present invention will be described with reference to FIGS. 1 and 2.
分別是代輯具有不同厚度(或接觸面積)之導體間隙壁 接下來，以圖1與 相變化原理。 圖2 量與電阳 電流量， I299567_c/e 的相變化圮憶體所做之測試。當然，本發明並不對相變化 記憶體之導體間隙壁做任何特別的限定，其可依照實際元 件的需要做最佳化的調整。圖2之曲線〗代表習知的相變 化記憶體所做之測試，曲線丨是僅有發生一段相變化情 形’即從結晶態完全轉變為非結晶態。 、請再次參照圖1，在對下電極102施加電壓時，由於 導體間隙壁的電阻值較加熱電極的電阻值高，因此電流會 先經由加熱電極106，而直接流到與加熱電極1〇6接觸之 相變化材料層110的介面(如電流路徑12〇所示），以產生 熱能，使加熱電極106頂部的相變化材料層11〇發生相變 化。亦即是，加熱電極1〇6頂部的相變化材料層ιι〇會從 結晶態變成非結晶態，且加熱電極1〇6頂部的相變化^料 層110會產生高電阻。請同時參照圖2，圖2中之J區域 的曲線2、3疋代表電流路徑120對加熱電極1〇6頂部的相 變化材料層110所誘發之相變化情形，隨著時間增加(即累 積電流$增加）’則加熱電極1〇6頂部的相變化材料声 之電阻值也會增加，直到加熱電極舰頂部的相變^ 層110完成相變化。 接著，在加熱電極106頂部的相變化材料層11()完成 相變化而產生高電阻之後，則電流會由加熱電^ 1〇6 ^到 導體間隙壁1〇8(如圖1之電流路徑122所示），以產^熱 能，使導體間隙壁108側壁之相變化材料層11〇發生相= 化。上述之電流路徑122對導體間隙壁1〇8側壁^相變= 材料層110所誘發之相變化情形，可如圖2之Η區域=曲 10 1299567 19547twf.doc/e 增加，ί至^其電阻值會隨累積電流量增加而 1直叫體間E宁、壁⑽側壁之相變化材 相受化。特別是，II區域的曲線2、3之曲二 ^ :=巧、3之曲線斜率小。而且 &相變化情形不同，曲線2、3皆 f、有 =«_⑽㈣之__層==相 1 匕則導體^壁⑽側壁之她_層m ‘ 生1阻，此時整個相變化材料層no即可完成相變化。 力敎ίΓ4寸別注思的是，本實施例之相變化記憶體10〇於 =熱電極106的侧壁配置有導體間 隙壁108的電阻值高於加敎且騎體間 對下雷極107^ 3 士 的電阻值。因此，在 電極102 %加讀^，會有兩段相變化情形，如此一 件相變化記憶體具有多個電阻決定態，其能允許元 ===：=㈣綱化記憶體 制^下°兒明本發明之可做為多階使用之相變化記憶體 一々錢方法。® 3Α· 3D為細本㈣之—實施例所繪 不、相變化記憶體的製造方法的流程剖面示意圖。 I先，請參照圖3A，提供一基底(未繪示），隨後在基 ，上形成下電極302，下電極3〇2例如是金屬層。接著， H ^電極302上形成介電層304，介電層304的材質例如 =氮化矽、氧化矽或其他合適之介電材料。然後，在介電 运/〇4中形成底部曝露出下電極302表面的接觸窗306。 於接觸自306中形成加熱電極308。加熱電極308 11They are the conductor spacers with different thicknesses (or contact areas), respectively. Next, the principle of phase change is shown in Fig. 1. Figure 2 is a test of the phase change of the ICHAN cation flow, I299567_c/e. Of course, the present invention does not make any particular limitation on the conductor spacers of the phase change memory, which can be optimally adjusted according to the needs of the actual components. The curve of Fig. 2 represents a test performed by a conventional phase change memory, in which only a phase change condition occurs, i.e., complete conversion from a crystalline state to an amorphous state. Referring again to FIG. 1, when a voltage is applied to the lower electrode 102, since the resistance value of the conductor spacer is higher than the resistance value of the heating electrode, the current flows directly to the heating electrode 1 through the heating electrode 106. The interface of the phase change material layer 110 that is in contact (as shown by current path 12A) is used to generate thermal energy to cause a phase change in the phase change material layer 11〇 on top of the heating electrode 106. That is, the phase change material layer ιι at the top of the heating electrode 1 〇 6 changes from a crystalline state to an amorphous state, and the phase change layer 110 at the top of the heating electrode 1 〇 6 generates high resistance. Referring to FIG. 2 at the same time, the curves 2 and 3 of the J region in FIG. 2 represent the phase change induced by the current path 120 on the phase change material layer 110 on the top of the heating electrode 1〇6, which increases with time (ie, the accumulated current). $ increase) 'The resistance value of the phase change material at the top of the heating electrode 1 〇 6 is also increased until the phase change layer 110 at the top of the heated electrode vessel completes the phase change. Then, after the phase change material layer 11 () on the top of the heating electrode 106 completes the phase change to generate high resistance, the current will be from the heating electrode to the conductor spacer 1 〇 8 (the current path 122 of FIG. 1). As shown, the phase change material layer 11 of the sidewall of the conductor spacer 108 is phased out by the heat energy. The above-mentioned current path 122 changes the phase change induced by the sidewall of the conductor spacer 1 = 8 = the material layer 110 can be increased as shown in Fig. 2 = 10 10 1299567 19547twf.doc/e, The value will increase with the amount of accumulated current and the phase change between the body and the wall of the wall (10). In particular, the curves of the curves 2 and 3 of the II region are 2^:=, and the slope of the curve of 3 is small. Moreover, the & phase change is different, the curves 2, 3 are f, the =__(10) (four) __ layer == phase 1 匕 the conductor ^ wall (10) sidewall of her _ layer m 'sheng 1 resistance, at this time the entire phase change material Layer no can complete the phase change.敎 Γ 寸 寸 寸 寸 寸 寸 寸 寸 寸 寸 寸 寸 寸 寸 本 本 本 本 本 本 本 本 本 本 本 本 本 = = = = = = = = = = = = = = = = = 热 热 热 热 热3 resistance value. Therefore, when the electrode 102% is read, there will be two phase changes. Such a phase change memory has a plurality of resistance determining states, which can allow the element ===:=(4) to program the memory system. The invention can be used as a phase change memory method for multi-stage use. ® 3Α·3D is a schematic diagram of a flow chart of a method for manufacturing a phase change memory. First, referring to Fig. 3A, a substrate (not shown) is provided, and then a lower electrode 302 is formed on the substrate, and the lower electrode 3〇2 is, for example, a metal layer. Next, a dielectric layer 304 is formed on the H^ electrode 302. The material of the dielectric layer 304 is, for example, tantalum nitride, hafnium oxide or other suitable dielectric material. Then, a contact window 306 is formed in the dielectric/germanium 4 to expose the surface of the lower electrode 302. The heating electrode 308 is formed in contact 306. Heating electrode 308 11
1299567 l9547twf.doc/e ，。接著，進行— 材料層，直至暴露出介電層304表面，而於電極 形成加熱電極308。 、屯層3〇4中 千场tf請參照圖3B，移除部分介電層_，以❹八 ㈣馳。上述移除部分介電層 =成介 餘刻製程。而且，移除部分介電層綱後，力 的頂部表面會高於介電層304a的頂部表面。、、、 之後，請參照圖3C，於加熱電極駕的側 ，間隙,310。導體間隙壁31〇的材質例如是氮‘ 鼠化组或氮化鈦IS。導體_:壁的形成方法例如:， 於介電層304a上順應性形成一導體材料層（未纷疋然 後，進行-钱刻製程，移除部分導體材料層，以形成之了 特別疋，由於導體間隙壁31〇的電阻值高於加執電極細 的電阻值，因此在後續對下電極3〇2施加電壓，、、可使元件 具有2段相變化情形。 之後，請參照圖3D，於介電層304上形成相變化材 料層312，且相變化材料層312覆蓋導體間隙壁31〇與加 熱電極308。相變化材料層312例如是硫屬化合物層，其 可例如是二元材料層、三元材料層或多元材料層。其中， 二元材料層的材質例如是InSb、GaSb、InSe、Sb2Te3或 GeTe ;三元材料層的材質例如是Ge2Sb2Te5、insbTe、 GaSbTe、SnSbTe4或InSbGe ;多元材料層的材質例如是 12 1299567 19547twf.d〇c/e1299567 l9547twf.doc/e , . Next, a material layer is applied until the surface of the dielectric layer 304 is exposed, and the heating electrode 308 is formed on the electrode.屯 Layer 3〇4 Thousands of fields tf Please refer to Figure 3B, remove part of the dielectric layer _, to eight (four) Chi. The above removal of a portion of the dielectric layer = forming a process. Moreover, after removing a portion of the dielectric layer, the top surface of the force will be higher than the top surface of the dielectric layer 304a. After that, please refer to FIG. 3C on the side of the heating electrode and the gap 310. The material of the conductor spacer 31 is, for example, a nitrogen "mouse group" or a titanium nitride IS. The conductor_: wall is formed by, for example, forming a layer of conductive material on the dielectric layer 304a (not divergently, then performing a process to remove a portion of the conductor material layer to form a special flaw due to The resistance value of the conductor spacer 31〇 is higher than the resistance value of the addition electrode, so that a voltage is applied to the lower electrode 3〇2, and the element can have two phases of phase change. Thereafter, refer to FIG. 3D. A phase change material layer 312 is formed on the dielectric layer 304, and the phase change material layer 312 covers the conductor spacers 31 and the heating electrode 308. The phase change material layer 312 is, for example, a chalcogenide layer, which may be, for example, a binary material layer, a ternary material layer or a multi-material layer, wherein the material of the binary material layer is, for example, InSb, GaSb, InSe, Sb2Te3 or GeTe; and the material of the ternary material layer is, for example, Ge2Sb2Te5, insbTe, GaSbTe, SnSbTe4 or InSbGe; The material is for example 12 1299567 19547twf.d〇c/e
AglnSbTe > (Ge,Sn)SbTe ^ GeSb(SeTe)^ Te81Ge15Sb2S2 〇 m 之，f相變化材料層312上形成上電極似，上電極叫 例如是金屬層。如此，即可完成相變化記憶體3⑻的製造。 綜士所述，本發明之相變化記憶體的加熱電極侧 置有導體間隙壁，且導體間隙壁的電阻值高於加熱電 電阻值’目此在元賴作過財，可使得機化記呈 有兩段相變化情形，而能夠做為多階使用。 ^ 雖然本發明已以實施例揭露如上，然其並非 本發明’任何制此技藝者，在不脫離本發明之 圍内’當可作些許之更動與潤飾，因此本發明之:口耗 當視後附之申請專利範圍所界定者為準。 ,、範圍 【圖式簡單說明】 圖2依照本發明-實施例所繪示之相變 剖面不思圖。 ^體的 圖2為本發明之一實施例的相變化記憶 量與電阻值之關係圖。 系積電流 圖3A至圖3D為依照本發明之一實施人一 變化記憶體的製造方法的流程剖面示意圖:歹1斤繪示的相 圖4為繪示習知一種相變化記憶體的 立 【主要元件符號說明】 "不思圖。 卜2、3 :曲線 100、300、400 ··相變化記憶體 102、302、402 :下電極 104、304、304a、404 :介電層 13 1299567 19547twf.doc/e 106、308、410 :加熱電極 108、310 :導體間隙壁 110、312、406 :相變化材料層 112、314、408 :上電極 120、122 :電流路徑 306 ··接觸窗AglnSbTe > (Ge,Sn)SbTe ^ GeSb(SeTe)^ Te81Ge15Sb2S2 〇 m, the upper electrode is formed on the f-phase change material layer 312, and the upper electrode is called a metal layer, for example. Thus, the fabrication of the phase change memory 3 (8) can be completed. According to the comprehensive person, the phase change memory of the phase change memory of the present invention has a conductor spacer on the side, and the resistance value of the conductor spacer wall is higher than the value of the heating electrical resistance. There are two phases of phase change, and can be used as multi-stage. Although the present invention has been disclosed in the above embodiments, it is not the subject of the present invention, and the present invention can be used to make some changes and retouching without departing from the scope of the present invention. The scope defined in the appended patent application shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view of a phase change diagram according to an embodiment of the present invention. Figure 2 is a graph showing the relationship between the amount of phase change memory and the resistance value according to an embodiment of the present invention. 3A to 3D are schematic cross-sectional views showing a method for fabricating a human-modified memory according to one embodiment of the present invention: a phase diagram of FIG. 4 is a diagram showing a conventional phase change memory. The main component symbol description] " not thinking. Bu 2, 3: Curves 100, 300, 400 · Phase change memory 102, 302, 402: Lower electrode 104, 304, 304a, 404: Dielectric layer 13 1299567 19547twf.doc/e 106, 308, 410: Heating Electrodes 108, 310: conductor spacers 110, 312, 406: phase change material layers 112, 314, 408: upper electrodes 120, 122: current path 306 · contact window
1414