TWI298544B - Method of fabricating a liquid crystal display - Google Patents

Description

1298544 - · Nine, invention description: [Technical field to which the invention pertains] " The present invention relates to a method of manufacturing a liquid crystal display. [Prior Art] Due to its low radiation, thin thickness and low power consumption, liquid crystal displays have been widely used in electronic devices such as notebook computers and mobile phones. Please refer to FIG. 1' for a schematic diagram of a prior art liquid crystal display. The liquid crystal display 10 includes a plurality of mutually parallel gate lines 100, a plurality of data lines 110 parallel to each other and perpendicularly insulated from the gate lines 100, a plurality of thin film transistors (TFTs) 130, a plurality of pixel electrodes 140, and Complex capacitor 120. The thin film transistor 130 is disposed at the intersection of the gate line 100 and the data line 110. The pixel electrode 140 and the capacitor 120 are located between the gate line 100 and the data line 110. Referring to FIG. 2 to FIG. 7, FIG. 2 is a flow chart showing a method of manufacturing the liquid crystal display device. FIG. 3 to FIG. 7 are schematic diagrams showing main steps of the manufacturing method of the liquid crystal display device 10 in the m-in φ direction. The manufacturing method of the liquid crystal display 10 includes three mask processes, and the specific steps are as follows: 1. The first mask process step 1 sequentially forms a gate metal layer and a first photoresist layer; see FIG. 3, providing an insulation The substrate n includes a thin film transistor region 12, a display region 13 and a capacitor region 14. A gate metal layer 101 and a first photoresist layer 102 are sequentially deposited on the insulating substrate 11. Step 2, forming a gate and a first capacitor electrode; exposing the first photoresist layer 102 with a first mask, and developing the first photoresist layer 102 of the germanium 298544, thereby forming a first photoresist pattern, and then The gate metal layer 101 is patterned to form a gate 132 of the thin film and a first capacitor electrode 122 of the capacitor region 14 as shown in FIG. Layer 102. Second, the second mask process step 3, sequentially forming an insulating layer, an amorphous germanium layer, a doped amorphous germanium layer, a source/drain metal layer and a second photoresist layer; having the gate 132 and the first An insulating layer 103, an amorphous germanium layer 104, a doped amorphous germanium layer 105, a source/drain metal layer 106 and a second photoresist layer are sequentially deposited on the insulating substrate of a capacitor electrode 122. 107, as shown in Figure 5. Step 4: forming a thin film transistor, an early element and a capacitor, exposing the second photoresist layer 107 with a second mask, and developing the second photoresist layer 107 to form a second photoresist pattern, and then etching away The source/drain metal layer 106, the doped amorphous germanium layer 105, the non-k germanium layer 104, and the insulating layer 103 of the display region 13 form a thin film transistor unit and a capacitor 120 as shown in FIG. The capacitor 120 includes the first capacitor electrode 122, the second capacitor electrode 121, and the doped amorphous germanium layer 105, the amorphous germanium layer 104, and the insulating layer 103 sandwiched therebetween. The thin film transistor unit includes the gate 132, the insulating layer 103, the amorphous germanium layer 104, the doped amorphous germanium layer 105, and the source/drain metal layer 106. Third, the third mask process step 5, sequentially forming a transparent metal layer and a third photoresist layer; on the insulating substrate 11 having the thin film transistor unit and the capacitor 120, I298544 Xia deposition a transparent gold lip layer and a first Three photoresist layers. Step 6, forming a source, a drain, and a pixel electrode; exposing the third photoresist layer with a third mask, and developing the third photoresist layer to form a three-resist pattern, and then etching the film : the transparent metal layer 14G of the body unit and the source/drain metal layer (10), and further the shape of the pixel electrode 14〇 as shown in FIG. 7, the source power of the thin film transistor 13〇, and the step 133, further (4) The thin film transistor unit is doped with the non-layer 105, thereby forming a trench I% in the doped amorphous germanium layer 1〇5. Through the above steps, the liquid crystal display 10 can be formed. The capacitance value of the electric valley 120 is calculated by the following formula: wherein CST represents the capacitance value of the capacitor 12〇, ε is a constant, and 八 represents the corresponding area of the first capacitor electrode 122 and the second capacitor electrode 121. Representing the insulating layer 1〇3, the amorphous germanium layer ι〇4, and the doped amorphous rock eve

The sum of the thicknesses of the three layers of the φ layer 1〇5. Therefore, the capacitance value cST of the capacitor 120 is proportional to the corresponding area A of the electrodes 122, 121 and inversely proportional to the thickness d. However, since the insulating layer 1〇3 of the capacitor 120 is in the same layer as the insulating layer 103 of the thin film transistor, and the thickness of the insulating layer 1〇3 of the thin film transistor 13 is limited, the capacitor is 12〇. The thickness of the insulating layer 1〇3 is not easily adjusted. In addition, since the two electrodes 122 and 121 of the capacitor 120 include not only the insulating layer 103 but also the amorphous germanium layer 1〇4 and the doped amorphous germanium layer 105, the thickness d of the capacitor 120 is large. Therefore, when the actual 1279854 current capacitance value, the corresponding area A of the two electrodes 122, 121 needs to be large. However, if the corresponding area A of the electrodes 122, 121 is large, the aperture ratio of the liquid crystal display device 10 is small, thereby affecting the display effect of the liquid crystal display. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a method of manufacturing a liquid crystal display having a high aperture ratio. A liquid crystal display manufacturing method comprising the steps of: providing an insulating substrate comprising: a thin film transistor region, a display region t-capacitor region, sequentially depositing on the germanium edge substrate - a gate metal layer And a light sheet exposing the first photoresist layer to: =, the pole between the body regions and the capacitor region of the capacitor region are amorphous and a second photoresist layer; step ^, -; The layer and the doped photoresist layer are exposed, and the: the mask is doped to the second region and the capacitor region, and then the photoresist layer is etched away. a layer and an insulating layer; on the bottom of the step, a 1st metal layer is deposited, and a third photoresist = a second mask is used to expose the third photoresist layer, and the source " and the metal layer are Thin film electricity: ==7: _ eight, with a fourth reticle for the fourth light in the capacitor (four) ' 彳 the purification layer, π, on the substrate sequentially deposited a 1298454 five metal layer and a fifth light a resist layer; step 10, exposing the second and second resist layers with a fifth mask, and developing the fifth photoresist layer, and then etching the transparent metal Μ ^, you, 9, in the thin The transistor region, the display region and the capacitor region form a pixel ray; κ complex pq °, the pixel region corresponding to the capacitor electrode, the capacitor electrode and the passivation layer sandwiched between the 曰 constitute a capacitor. The passivation layer of the capacitor is formed separately, and the thickness thereof is easy to adjust. Moreover, the two electrodes of the capacitor only include a passivation layer, and _ 'the degree of drought is small, so that when a large capacitance value is realized, the correspondence between the two electrodes Therefore, when the liquid crystal display manufacturing method realizes a large capacitance value, a high aperture ratio can be obtained. [Embodiment] Referring to FIG. 8, a schematic diagram of a liquid crystal display of the present invention is shown. The device 20 includes a plurality of mutually parallel gate lines 2 〇〇, a plurality of data lines 21 相互 parallel to each other and perpendicularly insulated from the gate lines 200 , a plurality of thin film transistors 230 , a plurality of capacitors 220 , a plurality of capacitor electrodes 222 , and a plurality of pixels The electrode transistor 230 is disposed at the intersection of the gate line 2 and the data line 210. The capacitor electrode 222 and the pixel electrode 221 are located between the gate line 200 and the data line 210. . The capacitor electrode 222 and the pixel electrode 221 intersect to form the capacitor 22A. Referring to FIG. 9 to FIG. 19, FIG. 9 is a flow chart of a preferred embodiment of the method for manufacturing the liquid crystal display 20. Figure 19 is a schematic diagram showing the main steps of the manufacturing method of the liquid crystal display 20 in the χ-χ direction. The manufacturing method of the liquid crystal display 20 includes five mask processes, and the specific steps are as follows:

11 1298544 First, the first mask process step si, forming a gate metal layer; • “Please refer to FIG. 10, providing an insulating substrate 3G, which may be a glass or the like. The insulating substrate 30 includes a thin film electricity. A crystal region Μ, a., ', a beie region 32, an electric valley region 33 and a line region 34 are formed, and a gate metal layer 2〇1 and a first photoresist layer 2 are sequentially deposited on the insulating substrate 3〇. 2. Step S2, forming a gate in the thin film transistor region, forming a gate electrode in the capacitor region, and forming a gate line in the line region; 々 exposing the first photoresist layer 2〇2 with the first mask And developing the first photoresist layer 202 to form a first photoresist pattern, and etching the gate metal layer 2〇1 with the first photoresist pattern as a mask, thereby forming a photoresist layer as shown in FIG. The gate 232 of the thin film transistor region 31, the electric valley electrode 222 of the capacitor region 33 and the gate line 200 of the wiring region 34 remove the photoresist layer. / 2. The second mask process Step S3, forming an insulating layer, an amorphous germanium layer, and a doped amorphous germanium layer; please refer to FIG. 12 together, having the gate 232 and the capacitor electrode 222 On the insulating substrate 30 of the gate line 200, a chemical vapor deposition (c}jemicai Vapor Deposition, CVD) method is used to form a tantalum nitride (SiNx) by using a reactive gas (8 out of 4) and ammonia (NH3). An insulating layer 203 is formed; and an amorphous layer 2〇4 is deposited on the insulating layer 203 by a chemical vapor deposition method; and then doped on the surface of the amorphous germanium layer 204 to form a doped amorphous rock Layer 205 〇Step S4, using a slit mask to form in the thin film transistor region and the line region

12 Γ298544 Second resist pattern with different thickness; please refer to _13 together to provide a second mask/cover (wrist resistance), the second light armor 4 includes - the shading area ^ is a slit light 42 and a light transmissive region 43, a light shielding (four), a slit region, the light transmissive region 43 corresponding to the axis display region 32 and the capacitor region 31 having a slit region 42 corresponding to the line region 34. With the 33rd setting, the two photoresist layers are exposed 'and then the second photoresist layer is advanced 4: the first formation-second photoresist pattern', that is, the portion of the slit region 42 is widened Part of the photoresist of zone 41 is 2 illusory. First, according to step S5, the doped non-slip layer and the insulating layer of the display area and the capacitor region are removed; the eclipse, non-day--the remaining portion of the photoresist 253, 263 and the mask, ^ region 32 and the doping of the capacitor region 33 are not (four) layer shift, : = layer two 3 ' as shown in FIG. The method can be a wet heart, and a mixture of both nitric acid and phosic acid is used as a residual liquid. Step S6, removing the second photoresist pattern; all gray to make a thin portion of the light... the residual photoresist 253 and the remaining photoresist 254, as shown in FIG. 253Γ263, oxygen or ozone electricity, ashing the remaining portion Part of the photoresist

Step S7, the engraved amorphous austenitic layer of the line region and the non-single-type doped amorphous slab layer 205 of the line region 34 are removed; 曰二:4, and then removed by using 嗣(1) This residual photoresist J does not. W丄13 1298544 Third, the third mask process step S8, forming a source/drain metal layer; depositing a source sequentially on the insulating substrate 30 having the doped amorphous germanium layer 205, the capacitor electrode 222 and the insulating layer 203 / Bipolar metal layer and a third photoresist layer. Step S9, forming a source and a drain in the thin film transistor region, forming a data line in the line region, exposing the third photoresist layer with a third mask, and developing the third photoresist layer to form a first Three photoresist pattern. Etching the source/drain metal layer with the third photoresist pattern as a mask, the etching solution etching only the source/drain metal layer without surname the capacitor electrode 222' to form a film in the thin film transistor region 31 a source 231 and a drain 233, a data line 210 is formed in the line region 34, and the doped amorphous germanium layer 205 is further etched to form a trench 238 in the doped amorphous germanium layer 205, and finally moved. Except for the third photoresist layer, as shown in FIG. Fourth, a fourth mask process step S10, forming a passivation layer; sequentially depositing a passivation layer and a first layer on the insulating substrate 30 having the source electrode 231, the drain electrode 233, the capacitor electrode 222, and the data line 210 Four photoresist layers. Step S11, forming a capacitive insulating layer in the capacitor region; exposing the fourth photoresist layer with a fourth mask, and developing the fourth photoresist layer to form a fourth photoresist pattern, the fourth photoresist pattern The pattern is a mask to etch the passivation layer, thereby exposing the thin film transistor region 31

14 1298544 A portion of the drain 233 is formed such that the display region 32 exposes the insulating substrate 30, and a purification layer 225 is formed in the capacitor region 33, and the fourth photoresist layer is removed, as shown in FIG. 5. The fifth mask step S12, forming a transparent metal layer; depositing a transparent metal layer and a fifth photoresist layer on the insulating substrate 30 having the drain 233 and the passivation layer 225. The transparent metal layer may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZ0). Step S13, forming a pixel electrode; exposing the fifth photoresist layer with a fifth mask, and developing the fifth photoresist layer to form a fifth photoresist pattern, wherein the fifth photoresist pattern is a mask The transparent metal layer is etched to form a pixel electrode 221 in a portion of the thin film transistor region 31, the display region 32, and the capacitor region 33, as shown in FIG. The pixel electrode 221 corresponding to the capacitor region 33, the φ capacitor electrode 222, and the passivation layer 225 sandwiched therebetween form a capacitor 220. After the above steps, the liquid crystal display 2 can be formed. The capacitance value of the capacitor 220 is calculated by the following formula: where CST represents the capacitance value of the capacitor 220, ε represents the dielectric constant of the passivation layer 225, and a represents the corresponding area of the capacitor electrode 222 and the pixel electrode 221, d The thickness of the passivation layer 225 is indicated. Therefore, the capacitance value CsT of the capacitor 220 is proportional to the corresponding area A of the two electrodes 222 and 221,

15 1298544 is inversely proportional to thickness d. Compared to the prior art, the passivation layer 225 of the capacitor 220 is formed separately in step S11, and its thickness is easily adjusted. Moreover, the second electrodes 222 and 221 of the capacitor 220 include only a passivation layer 225 having a small thickness d, so that the corresponding area A of the two electrodes 222 and 221 is small when a large capacitance value is realized. Therefore, the liquid crystal display manufacturing method can obtain a higher aperture ratio when achieving a large capacitance value. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a prior art liquid crystal display. 2 is a flow chart of a method of manufacturing the liquid crystal display shown in FIG. 1. 3 to 7 are schematic views showing main steps of a manufacturing method of the liquid crystal display shown in Fig. 1 along the m-πι direction. Figure 8 is a schematic illustration of a liquid crystal display of the present invention. Figure 9 is a flow chart showing a preferred embodiment of the method of fabricating the liquid crystal display device of Figure 8. Fig. 10 through Fig. 19 are schematic views showing the main steps of the manufacturing method of the liquid crystal display shown in Fig. 8 in the X-X direction.

16 1298544 [Description of main components] LCD 20 Insulation substrate 30 Thin-film transistor area 31 Display area 32 Capacitor area 33 Line area 34 Second mask 40 Shading area 41 Slit area 42 Transmitted area 43 Gate line 200 Gate Polar metal layer 201 first photoresist layer 202 insulating layer 203 amorphous germanium layer 204 doped amorphous germanium layer 205 data line 210 capacitor 220 pixel electrode 221 capacitor electrode 222 passivation layer 225 thin film transistor 230 source 231 gate 232 汲Pole 233 trench 238 partial photoresist 253, 263 residual photoresist 254

17

Claims (1)

1298544 X. Patent application scope: 1. A method for manufacturing a liquid crystal display, comprising the following steps: * Step 1, providing an insulating substrate comprising a thin film transistor region, a display region and a capacitor region on the insulating substrate Depositing a gate metal layer and a first photoresist layer in sequence; step 2, exposing the first photoresist layer with a first mask, developing the first photoresist layer, and then the gate metal The layer is etched to form a gate of the thin film transistor region and a capacitor electrode of the capacitor region; t step 3, sequentially depositing an insulating layer, an amorphous germanium layer, a doped amorphous germanium layer on the substrate a second photoresist layer; step 4, exposing the second photoresist layer with a second mask, developing the second photoresist layer, and then etching away the doped amorphous germanium layer of the display region and the capacitor region And an amorphous germanium layer and an insulating layer; step 5, sequentially depositing a source/drain metal layer and a third photoresist layer on the substrate; > step six, using the third mask to the third photoresist The layer is exposed, and the third photoresist layer is developed and then etched Etching the source/drain metal layer to form a source and a drain in the thin film transistor region; and step 7, depositing a passivation layer and a fourth photoresist layer on the substrate; step eight, to fourth Exposing the fourth photoresist layer to the fourth photoresist layer, and then etching the passivation layer to form a passivation layer in the capacitor region; Step 9: sequentially depositing a transparent metal layer on the substrate and a fifth photoresist layer; 18 (S. 1.298544 step 10, exposing the fifth photoresist layer with a fifth mask, developing the fifth photoresist layer, and then etching the transparent metal layer, the film is electrically The crystal region, the display region and the capacitor region form a pixel electrode, and the pixel electrode, the capacitor electrode and the passivation layer sandwiched therebetween form a capacitor. 2. The liquid crystal display according to claim 1 The manufacturing method, wherein the insulating substrate of the first step is a glass. The liquid crystal display manufacturing method according to claim 1, wherein the insulating substrate of the step 1 further comprises a line region. The liquid crystal display manufacturing method of the third aspect, wherein the second photomask of the step 4 is a slit mask, comprising a light shielding area, a slit area and a light transmission area, wherein the light shielding area corresponds to The thin-film transistor region, the slit region corresponds to the line region, and the light-transmitting region corresponds to the display region and the capacitor region. 5. The liquid crystal display manufacturing method according to claim 4, wherein the step 4 is After exposure and development, a photoresist pattern is formed, that is, a part of the photoresist of the slit region is thinner than a portion of the light-shielding region of the light-shielding region. The step 4 further includes ashing the photoresist pattern so that when the thinner portion of the photoresist is completely ashed, the thicker portion of the photoresist is further reduced. 7. As claimed in claim 3 The method of manufacturing a liquid crystal display, wherein the step one further comprises forming a gate line in the line region. 8. The method of manufacturing a liquid crystal display according to claim 3, wherein the step 6 further comprises forming a data line in the line region. The method for manufacturing a liquid crystal display according to claim 1, wherein the insulating layer of the third step is tantalum nitride. 10. The method for fabricating a liquid crystal display according to claim 1, wherein the deposition method of the third step is chemical vapor deposition. 11. The method of manufacturing a liquid crystal display according to claim 1, wherein the etching method of the fourth step is wet etching, and a mixture of both nitric acid and hydrofluoric acid is used as the etching liquid. 12. The method of fabricating a liquid crystal display according to claim 1, wherein the etching liquid of the step 6 etches only the source/drain metal layer.