1297564 玖、發明說明： 【發明所屬之技術領域】 相關申請案 - 本申請案對於2002年4月26日所提出申請之美國專利 5臨時申請案號Ν〇·60/406,217作優先權主張，其内容在此併 入作為參考。 - 發明領域 · 本發明是有關使用於交流馬達驅動系統中用於相位電 流感測電路之輸入濾波器，並且更尤其是有關用於去除漣 _ 10波雜訊之改良式濾波器，此雜訊會影響馬達電流控制之正 痛性。 【先前技術3 發明背景 現代馬達驅動器通常使用脈衝寬度調變(pWM)切換變 15頻器，以產生具有準確控制特徴之馬達驅動電流。此種系 統因為成本低廉且顯示低功率消耗而特別有利。 第1圖顯示傳統式PWM馬達驅動器之簡化概要圖式， 其通常以10表示。在此，所輸入之二或三相交流電力供應 給整流電路12，其在滙流排16與18上提供直流電給變頻器 20 14。此變頻器然後在線路22a-22c上提供經控制的交流電給 馬達20。 目前存在多種變頻器設計，但其通常包括成對❻以灼的 功率半導體開關（未圖示）’例如：用於各馬達相位之金屬氧 化物半導體場效應電晶體(MOSFET)或絕緣閘控雙載子電 5 1297564 晶體(IGBTS)。此等變頻器由在信號通路26上之PWM控制 電路24所提供之脈衝寬度調變(PWM)閘控制信號切換成導 通(on)或切斷(off)。 對於三相馬達，控制電路24將在固定頻率fpWM之三角 5形波與以120°異相之三個正弦參考信號比較，並且在三角 形波與參考信號之相交點產生PWM閘控驅動信號。此等表 考信號是由相電流回饋信號導出，其可以各種方式提供， 例如：藉由測量跨在馬達電流驅動線路22a-22c中感測電阻 器28a-28c之電壓降而提供。此所想要的馬達速率可以根據 10獨立控制之速率設定點信號30而決定。此項技術為熟習此 技藝人士所熟知，在此為了簡短起見省略進一步的說明。 PWM變頻器馬達驅動器所遭遇主要問題是，此由變頻 器14所提供之電流包含相當大的漣波成份。此驅動電流典 型的形狀是由在第2圖中線(a)說明。此驅動電流是由：典型 15在0-500Hz範圍（線⑼）中的信號成份，以及變頻器雜訊成份 (線(c))所構成。當在頻率領域中分析驅動電流時，發現雜 訊成份是在頻率fpwm，以及其諧波典型是在4kHz與以上。 去除此雜訊之直截了當的方法，似乎只要藉由使用傳 統式低通濾波器，將4kHz以上的頻率成份衰減即可。然而， 20 此方法會造成兩個不相容的要求： 春為了獲得6〇dB等級之信號對雜訊此須要準確的轉 換’這須要靠近5〇〇Hz有許多極點（階數>5)。 _為了避免在控制迴路中過度的延遲，此濾波器須要 在其通帶中導入非常小的相位延遲，其須要低等級 1297564 之濾波器與遠離500Hz之極。因為此等互相衝突的 須求’無法有效的使用低通濾波器法。 在事實上，此相位電流之雜訊成份是以兩種傳統方式 之-處理。-種方式是以隨機頻率取樣電流信號，此頻率 5並未與PWM信號作任何同纟。然❿，此種方法無法排除連 波與高頻率雜訊（而留下高至信號3〇%之雜訊成份）。 另一種方法是與三角形波的轉換同步取樣。如果載體 頻率高於PWM參考信號之頻率很多，在此三角形波正與負 之尖峰，此電流信號的漣波成分在理論上為零。在此等時 1〇刻取樣電流。因為在變頻器切換中高頻率非同步雜訊與空 載時間將S/N比例劣化，所以在系統之正常操作期間此種方 法不足以獲得60dB(相當於10位元之解析度)之信號對雜訊 比0 亦可使用與濾波器耦合連接之寬頻帶感測器。然而， 15此種方式是昂貴的，且須要在剩餘漣波與處理延遲之間抵 換。 — 總之，任何傳統方法均不能完全解決漣波問題，或以 小於PWM半週期之延遲反應。因此令人非常期望有較佳方 式以去除高頻雜訊成份或將其最少化，而同時亦對相位電 20流改變提供快速響應。本發明尋求滿足此須求。 【發明内容J 發明概要 因此，本發明之目的是提供一種用於在PWM馬達驅動 器中用於相位電流感測之改良式輸入濾波器。 1297564 本發明另一個目的是提供一種改良式輸入濾波器，其 在PWM三角形波與其諧波之頻率有效地減少在相位電流 回饋信號中之高頻率雜訊。 本發明相關的目的是提供此種改良式輸入濾波器，其 5 亦顯示對相位電流改變快速之響應。 本發明之另一目的為提供一種輸入濾波器，其對變頻 器切換特徵中之改變自行調變。 此等目的是根據本發明，在由用於閘驅動器控制電路 之改良式輸入濾波器所描述型式之P WM馬達驅動系統中 10 達成，此電路包括具有操作週期之積分電路，而在三角形 波fPWM頻率之整數倍或比例之頻率，由系統微控制器所產 生的SYNC信號觸發。此頻率較佳是三角形波頻率之兩倍。 根據本發明之一觀點，此改良式輸入濾波器包括： 電路其由以下所構成··直接耦合連接至代表馬達驅動 15 電流之信號之第一積分器，經由延遲電路耦合連接至馬達 驅動電流信號之第二積分器，其導入等於PWM三角形波半 週期之延遲；耦合連接第一與第二積分器輸出之減法電 路；以及以fPWM兩倍頻率操作之取樣與保持電路。 根據本發明之第二觀點，此積分電路是由電壓對時間 20 轉換器構成，其在等於PWM三角形波半週期之第一期間將 相位電流信號積分，其藉由以與馬達驅動電流信號相反極 性之參考信號之積分值，在PWM三角形波之後半週期間， 減少此經積分相位電流信號之值，並且此積分電路在第二 期間當此積分電路回到預先設定位準（例如：零）時提供顯 1297564 不 ο 根據本發明之第二觀點，此電壓對時間轉換器包括： 積分器，第一切換元件將相位電流信號輕合連接至積分器 5 2輸人’以及第二切換元件將參考信職合連接至積分器 輪入，其中對等於PWM三角形波半週期之連續第—與第二 期間:將第一切換元件交替地導通㈣與切斷(。·此第二 切換兀件在第-期間切斷且在第二期間導通，且其包括位 ;偵測器，、在第—期間當此整合器輸出朗零位準時提 供顯示。 10 15 仍;、、;還根據本發明第二觀點，此渡波電路是由第二電 壓對時間轉換器構成，其包括：第二積分器，第三切換元 件將馬達驅動電流信_合連接至第二積分器之輸入，以 及第四切換元件將參考信_合連接至第二積分器之輸 入’並且其中將第三切換元件交替地在第二關導通且在 第一期間切斷’將第四切換元件在第-期間導通且在第二 ，月間切斷，並且其中在第_期間當此來自第二積分器之輸 出回到零位準時，綠準彳貞測_提供顯*。 根據本發明之第三觀點，此改良式遽波器由切換電容 器⑽積分電路構成，而以由系統微控制器在pwM三角形 20波頻率所產生SYNC^號同步之高速時脈操作，此系統微控 制器經由取樣開關連接至類比至數位轉換器（adc)，此開關 在SYNC信號之每半週期對積分器輸出取樣。 本毛月之特點與優點將由以下對本發明之描述並參考 所附圖式而為明顯。 1297564 在所有的圖式中，相同的部份由相同的參考號碼代表。 圖式簡單說明 第1圖為概要圖顯示傳統PWM切換馬達驅動器之基本 特性； ° ^ 第2圖為波％圖顯示包括信號與雜訊(漣波)成份之馬達 驅動電流； 第3圖為概要圖顯示本發明第一實施例之基本觀念； 第4A與4B圖說明第一實施例之操作； 第5圖為概要圖，其說明本發明第二實施例之執行. 1〇 第6圖說明第2實施例之操作； ’ 第7圖為概要電路說明本發明第三實施例之執行。 第8圖說明第三實施例之操作。 H jiT 】 季父佳實施例之詳細說明 15 …請參考第，，在本發明第-實施财，此輸入攄波 通*以31代表’是由^級之積分電路伽縣樣與^持, 路34所構成’其以由系統微控器（未圖示)在等於PWM:; 形波頻率W兩倍之頻率fs所產生SYNC信號之= ::=Γ波，C信號，以及由SYNC信號所^ 、s之關係是在第4A與4B圖中說明。如同π 對於各馬達相位时各別㈣波電路3卜 =然參考第3圖，積分電路32包括第一積分％ 跨電阻器28而用於相位電流之-信號之❹ -立電流信號(參考第1圖）。第二積分器38經法 20 1297564 延遲電路40連接至相位電流信號，此延遲電路將第二積分 路輸入延遲SYNC信號之一半週期。此用於延遲電路4〇之控 制可以經由信號通路50，由來自系統控制器（其典型為未圖 示之數位信號處理器（DSP))之SYNC信號直接提供。取樣與 保持電路34可以同樣由經信號通路52所提供SYNC信號所 控制。 積分器36與38可以任何適當方式建構而成，例如：使 用具有串聯輸入電阻器44之放大器42,以及耦合連接介於 放大器輸入與輸出之間之積分電容器46建構而成。 積分器36與38之輸出連接至減法電路48，其將被延遲 半S YN C週期之相位電流之積分減去相位電流信號之積 分。因此，減法電路48之輸出具有此形式：。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The content is incorporated herein by reference. - FIELD OF THE INVENTION The present invention relates to an input filter for a phase current sensing circuit used in an AC motor drive system, and more particularly to an improved filter for removing 涟 10 wave noise, this noise Will affect the positive pain of motor current control. [Prior Art 3 BACKGROUND OF THE INVENTION Modern motor drivers typically use a pulse width modulation (pWM) switching variable frequency converter to produce a motor drive current with accurate control characteristics. Such systems are particularly advantageous because of their low cost and low power consumption. Figure 1 shows a simplified schematic of a conventional PWM motor driver, which is generally indicated at 10. Here, the input two or three-phase AC power is supplied to the rectifier circuit 12, which supplies DC power to the inverters 20 14 on the bus bars 16 and 18. The frequency converter then provides controlled alternating current to the motor 20 on lines 22a-22c. There are a variety of drive designs available today, but they typically include a pair of xenon-powered semiconductor switches (not shown), such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gating pairs for each motor phase. Carrier 5 597564 crystal (IGBTS). These frequency converters are switched on or off by a pulse width modulation (PWM) gate control signal provided by PWM control circuit 24 on signal path 26. For a three-phase motor, control circuit 24 compares the triangular 5-shaped wave at a fixed frequency fpWM with three sinusoidal reference signals that are out of phase with 120° and produces a PWM gating drive signal at the intersection of the triangular wave and the reference signal. These reference signals are derived from the phase current feedback signal, which may be provided in various ways, for example, by measuring the voltage drop across the sense resistors 28a-28c across the motor current drive lines 22a-22c. This desired motor rate can be determined based on 10 independently controlled rate setpoint signals 30. This technique is well known to those skilled in the art, and further description is omitted herein for the sake of brevity. A major problem encountered with PWM inverter motor drives is that the current provided by inverter 14 contains a significant amount of chopping components. The typical shape of this drive current is illustrated by line (a) in Figure 2. This drive current consists of a typical 15 signal component in the 0-500 Hz range (line (9)) and a frequency converter noise component (line (c)). When the drive current is analyzed in the frequency domain, the noise component is found to be at the frequency fpwm, and its harmonics are typically at 4 kHz and above. A straightforward way to remove this noise seems to be to attenuate frequency components above 4 kHz by using a conventional low-pass filter. However, this method will cause two incompatible requirements: Spring in order to obtain a signal of 6〇dB level, which requires accurate conversion of noise. This requires a lot of poles near the 5〇〇Hz (order >5) . _ In order to avoid excessive delays in the control loop, this filter needs to introduce a very small phase delay into its passband, which requires a low level 1297564 filter and a farther away from 500 Hz. Because these conflicting requirements “cannot effectively use the low-pass filter method. In fact, the noise component of this phase current is processed in two conventional ways. The way is to sample the current signal at a random frequency, which is not the same as the PWM signal. Then, this method cannot eliminate continuous wave and high-frequency noise (and leave the noise component as high as 3〇% of the signal). Another method is to sample synchronously with the conversion of the triangular wave. If the carrier frequency is much higher than the frequency of the PWM reference signal, the chopping component of this current signal is theoretically zero at the positive and negative peaks of the triangular wave. At this time, the sampling current is 1 〇. Because the high frequency non-synchronous noise and no-load time degrade the S/N ratio during the inverter switching, this method is insufficient during the normal operation of the system to obtain a signal interference of 60 dB (equivalent to 10-bit resolution). A wideband sensor coupled to the filter can also be used for analog 0. However, this approach is expensive and requires a trade-off between residual chopping and processing delay. – In summary, any conventional method cannot fully solve the chopping problem, or react with a delay less than the PWM half cycle. It is therefore highly desirable to have a better way to remove or minimize high frequency noise components while also providing a fast response to phase current changes. The present invention seeks to satisfy this need. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved input filter for phase current sensing in a PWM motor driver. 1297564 Another object of the present invention is to provide an improved input filter that effectively reduces high frequency noise in the phase current feedback signal at the frequency of the PWM triangle wave and its harmonics. A related object of the present invention is to provide such an improved input filter, which also exhibits a fast response to phase current changes. Another object of the present invention is to provide an input filter that self-modulates changes in the switching characteristics of the frequency converter. These objects are achieved in accordance with the present invention in a P WM motor drive system of the type described by an improved input filter for a gate driver control circuit, the circuit comprising an integrating circuit with an operational period, and a triangular wave fPWM The integer multiple of the frequency or the frequency of the ratio is triggered by the SYNC signal generated by the system microcontroller. This frequency is preferably twice the frequency of the triangular wave. According to one aspect of the present invention, the improved input filter comprises: a circuit comprising: a first integrator coupled directly to a signal representative of a motor drive 15 current, coupled to the motor drive current signal via a delay circuit a second integrator that introduces a delay equal to a half cycle of the PWM triangular wave; a subtraction circuit coupled to the first and second integrator outputs; and a sample and hold circuit operating at twice the frequency of the fPWM. According to a second aspect of the present invention, the integrating circuit is constituted by a voltage versus time 20 converter which integrates the phase current signal during a first period equal to a half period of the PWM triangular wave by opposing the polarity of the motor driving current signal The integrated value of the reference signal, the value of the integrated phase current signal is reduced during the second half of the PWM triangular wave, and the integrating circuit returns to the preset level (for example, zero) during the second period. According to a second aspect of the present invention, the voltage-to-time converter includes: an integrator, the first switching element directly coupling the phase current signal to the integrator 52 and the second switching element will reference The letter combination is connected to the integrator wheel, wherein the pair is equal to the continuous first and second periods of the PWM triangle wave half cycle: the first switching element is alternately turned on (four) and cut off (.. this second switching element is in the - the period is cut off and turned on during the second period, and it includes a bit; the detector, during the first period, when the integrator outputs a zero level, the display is provided. 10 15 still; According to a second aspect of the present invention, the wave circuit is constituted by a second voltage-to-time converter, comprising: a second integrator, the third switching element connecting the motor drive current signal to the input of the second integrator And the fourth switching element connects the reference signal to the input of the second integrator and wherein the third switching element is alternately turned on at the second off and turned off during the first period 'the fourth switching element is at the first The period is turned on and is cut off at the second, month, and wherein during the _th period, when the output from the second integrator returns to the zero level, the green quasi-measurement_provides a display*. According to the third aspect of the present invention, The modified chopper is composed of a switching capacitor (10) integrating circuit, and is operated by a high-speed clock synchronized by a system microcontroller at a pwM triangle 20-wave frequency. The system microcontroller is connected to the analogy via a sampling switch. To the digital converter (adc), which switches the integrator output during each half cycle of the SYNC signal. The features and advantages of the present invention will be apparent from the following description of the invention and with reference to the drawings. 1297564 In all the drawings, the same parts are represented by the same reference numerals. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing the basic characteristics of a conventional PWM switching motor driver; ° ^ Fig. 2 is a wave % graph display The motor drive current includes signal and noise (chopping) components; FIG. 3 is a schematic view showing the basic concept of the first embodiment of the present invention; FIGS. 4A and 4B are diagrams illustrating the operation of the first embodiment; The figure illustrates the execution of the second embodiment of the present invention. Fig. 6 is a view showing the operation of the second embodiment; 'Fig. 7 is a schematic circuit for explaining the execution of the third embodiment of the present invention. Fig. 8 is a view showing the third embodiment. Example operation H jiT 】 Detailed description of the embodiment of the season father 15 ... Please refer to the first, in the first implementation of the invention, this input 摅 通 * 以 以 以 以 31 31 31 是 是 是 是 是 是 是 是 是 是And the circuit 34 constitutes 'the SYNC signal generated by the system microcontroller (not shown) at a frequency fs equal to twice the PWM frequency; twice the frequency of the wave W = ::= chopping, C signal, And the relationship between the SYNC signal and s is illustrated in Figures 4A and 4B. As for π for each motor phase, each (four) wave circuit 3 = reference to Figure 3, the integration circuit 32 includes a first integral % across the resistor 28 for the phase current - the signal ❹ - the vertical current signal (refer to 1 picture). The second integrator 38 is coupled to the phase current signal via a delay circuit 12 1297564, which delays the second integrating input by one half cycle of the SYNC signal. This control for the delay circuit 4 can be provided directly via the signal path 50 by a SYNC signal from a system controller, which is typically a digital signal processor (DSP) not shown. The sample and hold circuit 34 can likewise be controlled by the SYNC signal provided via signal path 52. Integrators 36 and 38 can be constructed in any suitable manner, for example, using an amplifier 42 having a series input resistor 44 and an integrating capacitor 46 coupled between the input and output of the amplifier. The outputs of integrators 36 and 38 are coupled to a subtraction circuit 48 which subtracts the integral of the phase current of the delayed half S YN C period by the integral of the phase current signal. Therefore, the output of subtraction circuit 48 has this form:
Vm為用在討論中相位之相位電流信號，且 15 信號之週期。 第4A圖說明積分電路32之轉換功能。在此期間τ/2之積 分具有類似於在頻率fpWM之單實極之頻率響應，因此將高 頻雜訊(即，在fPWM以上)大幅抑制。此外，其轉換特性正好 在偶數諧波顯示多個傳送零，因此將此等頻率大幅地衰減。 2〇 取樣與保持電路34可以任何傳統方式構成，其運作以 衰減之基本頻率與奇數諧波。這是在第4B圖找明。 在此，線⑷說明具有重疊切換位準56之三角形載波M，此 換位準代表所想要之相位電流。如同在師)中所示，當三 1297564 角形波在切換位準上時，此反轉器（請參考第1圖）操作，以 產生方形波58形式之電壓，而方形波所具有的負載週期是 由用於馬達所須相位電流所決定。 5 10 15 20 此所產生的相位電流由於電感性馬達負載因此為斜 面’而以簡化的形式顯示於線(C)中。漣波（雜訊）包括在基 本頻率fpWM之諧波之後之成份，但是為了簡單起見，在線(d) 與(e)只顯示基本與第三諧波，因為如同先前說明，積分電 路去除了偶數諧波。線(0與(g)說明在減法電路48之輸出之 信號。由於積分電路32是由兩個平行積分通路構成，其作 用是在基本與奇數諧波中導入90。（1/4週期）之相位移。 線(h)與⑴顯示用於操作濾波器31之兩個充替的SYNC L號第一替代線(h)為方形波，其位準轉換與三角形波線 ⑷之方向改變重合。第二替代線⑴，其相位移⑽。，因此其 位準轉換與三角形波之零交點重合。 如同先前說明，取樣與保持電路34是在SYNC信號之各 轉換(即，在等於2fPWM之解)上操作。在第侧之線⑴與 此跡_)之SYNC信狀取樣相是由向上指向 一月J頁所T如同可以看出，在此等取樣時間之基本與第 三譜波(収其料數雜)是在最大鱗，並且因此並未由 取樣與保㈣作所抑制，但此可供㈣ 對於三角形波方向轉僅微 f ==統到達其穩定狀態時，馬達電流在週期 。這是當此整個系統須要最高準確 度日身，亦可看出，由於隨著時間會產生馬達 12 1297564 負裁或设定速率之改變’此日守間期間較三角形波54之週期 為長。基本波之連縯樣本’例如樣本60a與60b之振幅實質 相等但極性相反。這對於奇數諧波當然是相同的情形。因 此，DSP可獲得連續樣本之平均值，並且因此提供此等頻 5 率有效的衰減，其代價為另外半週期之延遲。 可以使用在線⑴中所示SYNC信號之第二形式達成基 本波與奇數諧波更有效之抑制。對此，向下指向箭頭顯示 取樣時間。如同可以看出，在此等取樣時間，基本，第三， 以及所有其他奇數諳波是在最低位準，並且因此被取樣與 10保持操作強烈地抑制。此僅以相對於由積分過程所導入三 角形波方向轉換90。相位移為代價，而產生較佳濾波，這可 藉由比較第4B圖之線⑷與(f)以及線⑷與⑷而看出。 在第5圖中所說明通常以64代表之第一實施例觀念之 另一種實施方式。在此處，將積分、取樣、以及保持功能 15合併入單一電路中，其作用為雙斜面積分器。濾波電路64 包括單一積分器66,具有如同第3圖中積分器36與38相同結 構，而以輸入電阻器68連接至第一與第二開關68與7〇。此 等開關68與70之閘控，是由SYNC方形波之位準轉換控制， 而開關68在第一半週期被導通(on)，而在第二半週期被切斷 20 (〇ff)。相反的，開關7〇在第一半週期被切斷，以及在第二 半週期被導通。積分器66之輸出連接至位準偵測器，較佳 為零交叉偵測器72，如同以下說明者。 開關68連接至相位電流信號，而開關7〇連接至具有振 幅Vref之參考信號，並且極性與相位電流信號之極性相反。 13 1297564 在第6圖中說明第5圖電路之操作。如同在線⑷與⑻中 所示，SYNC信號之第一半週期從刊至丁丨為積分期間，在 期間將輸入之相位電流信號積分至位準Vout，其與相位電 路信號振幅與積分週期Tpwm/2之乘積除以積分器66之時間 5 之RC時間常數之值成正比，即Vm is the phase current signal used in the phase of the discussion, and the period of the 15 signal. Fig. 4A illustrates the conversion function of the integrating circuit 32. During this period, the integral of τ/2 has a frequency response similar to that of a single real pole at the frequency fpWM, thus greatly suppressing high frequency noise (i.e., above fPWM). In addition, its conversion characteristics show multiple transmitted zeros in even harmonics, so these frequencies are greatly attenuated. The sample and hold circuit 34 can be constructed in any conventional manner that operates to attenuate the fundamental frequency and odd harmonics. This is found in Figure 4B. Here, line (4) illustrates a triangular carrier M having overlapping switching levels 56, which represents the desired phase current. As shown in the division, when the three 1297564 angular wave is on the switching level, the inverter (refer to Figure 1) operates to generate the voltage in the form of square wave 58, and the duty cycle of the square wave It is determined by the phase current required for the motor. 5 10 15 20 The resulting phase current is shown as a ramp in the inductive motor load and is shown in simplified form in line (C). Chopping (noise) includes components after the harmonics of the fundamental frequency fpWM, but for the sake of simplicity, lines (d) and (e) only show the basic and third harmonics, because the integration circuit is removed as previously explained. Even harmonics. The lines (0 and (g) illustrate the signal at the output of the subtraction circuit 48. Since the integration circuit 32 is composed of two parallel integration paths, its function is to introduce 90 in the basic and odd harmonics. (1/4 cycle) Phase Displacement Lines (h) and (1) show that the first alternate line (h) of the two SYNC L numbers used to operate the filter 31 is a square wave whose level transition coincides with the direction change of the triangular wave line (4). The second alternative line (1) has a phase shift (10), so its level transition coincides with the zero crossing of the triangular wave. As previously explained, the sample and hold circuit 34 is at each transition of the SYNC signal (ie, at a solution equal to 2fPWM) Operation. The SYNC signal sampling phase of the line (1) on the first side and the trace _) is as pointed up by pointing upwards to the J page of January, as can be seen in the basic and third spectral waves of the sampling time. The number is mixed at the maximum scale, and therefore is not suppressed by sampling and protection (4), but this is available (4) For the direction of the triangle wave, only the micro f == system reaches its steady state, the motor current is in the cycle. This is because the entire system requires the highest accuracy. It can also be seen that the motor 12 1297564 is negatively cut or the set rate is changed over time. The period during the custodial period is longer than the period of the triangular wave 54. The samples of the basic wave are performed, for example, the amplitudes of the samples 60a and 60b are substantially equal but opposite in polarity. This is of course the same for odd harmonics. Therefore, the DSP can obtain an average of consecutive samples and thus provide this equal-rate effective attenuation at the expense of another half-cycle delay. A more effective suppression of the fundamental and odd harmonics can be achieved using the second form of the SYNC signal shown in line (1). In this regard, the downward pointing arrow shows the sampling time. As can be seen, at these sampling times, the basic, third, and all other odd choppings are at the lowest level, and thus are strongly suppressed by the sampling and 10 holding operations. This is only converted 90 with respect to the direction of the triangular wave introduced by the integration process. The phase shift is at the expense of better filtering, as can be seen by comparing lines (4) and (f) of Figure 4B with lines (4) and (4). Another embodiment of the concept of the first embodiment, generally indicated at 64, is illustrated in Figure 5. Here, the integration, sampling, and hold functions 15 are combined into a single circuit that acts as a double-slope area divider. The filter circuit 64 includes a single integrator 66 having the same structure as the integrators 36 and 38 of Fig. 3, and connected to the first and second switches 68 and 7 by an input resistor 68. The gates of these switches 68 and 70 are controlled by the level shifting of the SYNC square wave, while the switch 68 is turned "on" during the first half cycle and 20 (〇ff) during the second half cycle. Conversely, switch 7 is turned off during the first half cycle and turned on during the second half cycle. The output of integrator 66 is coupled to a level detector, preferably zero cross detector 72, as explained below. Switch 68 is coupled to the phase current signal and switch 7 is coupled to the reference signal having amplitude Vref and is of opposite polarity to the phase current signal. 13 1297564 The operation of the circuit of Figure 5 is illustrated in Figure 6. As shown in lines (4) and (8), the first half cycle of the SYNC signal is integrated from the publication to Ding, during which the input phase current signal is integrated to the level Vout, which is related to the phase circuit signal amplitude and integration period Tpwm/ The product of 2 is proportional to the value of the RC time constant of time 5 of integrator 66, ie
Vout=Vin/RCxTPWM/2 (2) 此各SYNC信號之第二半週期為零位準計算時期，在此 期間將在第一半週期期間所獲得積分器輸出之值，減去參 考號Vref之負積分。在第一半週期之後從v〇ut之值開始， 10 則在時間t之後輸分器輸出，，Vout，，將是：Vout=Vin/RCxTPWM/2 (2) The second half of each SYNC signal is a zero-bit calculation period during which the value of the integrator output obtained during the first half-cycle is subtracted from the reference number Vref. Negative points. After the first half cycle, starting from the value of v〇ut, 10 after the time t, the output of the divider, Vout, will be:
Vout=Vref/RCx 1/2 (3) 零交叉偵測器72決定用於此參考信號負積分，將積分 器輸出信號降低為零所須之時間t。藉由將用於積分期間之 Vout等於用於轉換期間t-T1之v〇ut，，而可獲得： 15 VinxTpwM/2=Vrefxt 或 ⑶Vout = Vref / RCx 1/2 (3) The zero crossing detector 72 determines the time t required for the negative integration of the reference signal to reduce the integrator output signal to zero. By setting Vout for the integration period equal to v〇ut for the conversion period t-T1, it is possible to obtain: 15 VinxTpwM/2=Vrefxt or (3)
Vin=Trefx2t/TPWM4 (4) 此根據第二實施例之電路避免連續時間積分器之飽和 問題而無須任何類比延遲，並且積分器電容器亦實施取樣 與保持功能以儲存類比資訊。此外，其輸出為時間區間， 2〇有用於驅動積分位準位移器。除此之外，使用此雙斜而方 去去除積分器66之RC時間常數之效應，以及例如由於溫度 變化或製造公差所造成積分電容器74之非線性效應。 因為此雙斜面之實施要求：此SYNC矩形波之第一半週 期用於積分以及第二半週期之部份用於計算回歸至零之時 14 1297564 結束時將會㈣間wh，在此期 _實：==訊。為7避免此_，在雙 TU使用兩個各別的積分電路。可以有 效地使料此電壓對時間轉換結束與新轉換開始開始之間 所剩餘，時間，以達成在放A||66上抵消補償之任務。 10 二 在第6B圖中，以如同在線⑷與⑻中所說明之SYNC矩 形波與三肖形PWM_，此第—積分爾⑷)在第一半週 期（T0至τ卜T2至T3等）實施積分，而在第二半週期⑺至 丁2、T3至T4)期間實施零位準計算(並抵消補償）。反之，第 二積分器（線⑷)在第一半週期(T(^T1、丁2至丁3等)期間實 施零件準計算與抵消補償，並且在第二半週期(Τ1Η2、Τ3 至Τ4)期間實施積分。 本發明原理之另一實施例，如同於第7圖中80所說明 者，使用切換電容(sc)積分器82,經由取樣開關86耦合連接 15至類比至數位轉換器（ADC)84。此實施例之優點為只須用於 各馬達相位之單一積分器，以及直接提供代表所測量電流 之免除雜訊之數位信號。 現在已知有各種形式之SC積分器，並且可以採用任何 適當的設計用於根據本發明的裝置，此如同由熟習此技術 20之人士所瞭解者。然而，為了說明的目的，如同在第7圖中 所示，SC積分器82由放大器88所構成，其具有：積分電容 器90，以及連接介於放大器輸入94與輸出96之間的電容器 並聯開關92a。串聯輸入電路90包括··第一開關92b、電容 器100、以及第二開關92c ;以及連接至電容器1〇〇相對端之 15 1297564 5 10 15 20 接地開關92d與92e亦連接至輸入94。開關％以及咖-似由 高速時脈驅動，此時脈與相位鎖定迴路(未圖示)之各個信號 線102與104上之SYNC信號同步。此時脈典型地較sync頻 率快32至64倍。 開關與92e由高速時脈之—相位同時操作，而開關 92c與9M疋由k脈之第二非重疊相操作。取樣開關财 SYNC矩形波之各半結束之賴作，將積分值傳送給 ADC84。開_政在取樣開_之後操作，例如幻覽 信號轉換時操作，以重新狀積分器82。第8圖顯示相對於 SYNC信號(線b)在積分器、輸出％之波形(線a)。由於積八哭 82可以有SYNC信號之各半週期之開始被重新設定，而= 如同在第5與6圖之雙斜面實施例中使用雙積分器在交替的 半週期中操作。 請再參考第7圖，除了由ADC 84所提供直接輪出之 外’可㈣個連續樣本相加的形式提供第二輪出。 由經延遲電路106搞合連接ADC輸出信號而達成，入^ 於一半SYNC·之輯至加法魏⑽，其將此經延遲斑 未經延遲信號相加。此由加法電路⑽所提供之組 單獨未經延遲之信號顯不較佳之信號對雜訊比。化 由以上所作揭示，熟習此技術人士可瞭解，此 發明之積分渡波器之結構提供具有良好信號對雜本 有效濾波，並且可以簡單的實施作為pWM馬達系之 ，統零件之-部份。此濾波騎構亦料自行調整2 证’即’纽ϋ傳送魏之傳送零與整_狀改變> 以正 16 1297564 好抑制由變頻器之切換所導入之雜訊諧波，只要此等改變 由正確的SYNC信號追蹤。 在此方面根據瞭解在正常的情況下，此用於給定變頻 為之二角形波之頻率固定，但即使當此系統運作時頻率改 5 ^ ’此等m可以追縱改變且正確地操作，而在第7與8 圖實施例的情形中受限於PLL鎖定新頻率所須之任何等待 時間。 雖然本發明是關於特殊實施例說明，然而由此說明而 對於热習此項技術人士為明顯，可以作其他的變化，修正 1〇與應用。因此其用意為，本發明並不受限於在此所作之特 殊揭示，而是受限於所附申請專利範圍之整個範圍。 【圖式簡單說明】 第1圖為概要圖顯示傳統pWM切換馬達驅動器之基本 特性； 15 第2圖為波形圖顯示包括信號與雜訊(漣波)成份之馬達 驅動電流； 第3圖為概要圖顯示本發明第一實施例之基本觀念； 第4A與4B圖說明第一實施例之操作； 弟5圖為概要圖，其說明本發明第二實施例之執行· 20 第6圖說明第2實施例之操作； 第7圖為概要電路說明本發明第三實施例之執行。 第8圖說明第三實施例之操作。 【圖式之主要元件代表符號表】 12…整流電路 10...PWM馬達驅動器 17 1297564 14…變頻器 16…匯流排 18…匯流排 20…馬達 22a，b，c···線路 24-"PWM控制電路 26…信號通路 28a···感測電阻器 30…速率設定點信號 3l···輸入渡波器 32…積分電路 34…取樣與保持電路 36…第一積分器 38…第二積分器 40…延遲電路 42…放大器 44…串聯輸入電阻器 46…積分電容器 48…減法電路 50…信號通路 52…信號通路 64…濾波器電路 66…積分器/放大器 68…第一開關 70…第二開關 72…零交叉偵測器 74…積分電容器 82…切換電容器 84…類比至數位轉換器 86…取樣開關 88…放大器 90…積分電容器 92a···電容器並聯開關 92b…第一開關 92c···第二開關 92d，e···接地開關 94…放大器輸入 96…放大器輸出 100···電容器 102…信號線 104…信號線 106···延遲電路 108···加法電路Vin = Trefx2t / TPWM4 (4) The circuit according to the second embodiment avoids the saturation problem of the continuous time integrator without any analog delay, and the integrator capacitor also implements a sample and hold function to store analog information. In addition, its output is the time interval, and 2〇 is used to drive the integral level shifter. In addition to this, the effect of the RC time constant of the integrator 66 is removed using this double skew and the nonlinear effects of the integrating capacitor 74 due to, for example, temperature variations or manufacturing tolerances. Because the implementation of this double bevel requires: the first half of the SYNC rectangular wave is used for integration and the second half of the cycle is used to calculate the return to zero when 14 1297564 ends, (four) between wh, in this period _ Real: == News. To avoid this _, use two separate integration circuits in the dual TU. It is possible to effectively make the remaining time between the end of the voltage-to-time conversion and the start of the new conversion to achieve the task of offsetting the compensation on the A||66. 10 in Figure 6B, with the SYNC rectangular wave and the three-Shaw PWM_ as described in lines (4) and (8), this first-integral (4) is implemented in the first half cycle (T0 to τ, T2 to T3, etc.) Integration, and zero level calculation (and offset compensation) during the second half cycle (7) to D2, T3 to T4). Conversely, the second integrator (line (4)) performs part quasi-calculation and offset compensation during the first half cycle (T (^T1, D2, D3, etc.), and in the second half cycle (Τ1Η2, Τ3 to Τ4) Integration is performed during the process. Another embodiment of the principles of the present invention, as illustrated by 80 in FIG. 7, uses a switched capacitor (sc) integrator 82 coupled via a sampling switch 86 to an analog to digital converter (ADC). 84. The advantage of this embodiment is that a single integrator is only required for each motor phase, and a digital signal that is free of noise representative of the measured current is directly provided. Various forms of SC integrators are known and any Appropriate design is used for the device according to the invention, as is known to those skilled in the art 20. However, for illustrative purposes, as shown in Figure 7, the SC integrator 82 is comprised of an amplifier 88, It has an integrating capacitor 90, and a capacitor shunt switch 92a connected between the amplifier input 94 and the output 96. The series input circuit 90 includes a first switch 92b, a capacitor 100, and a second switch 92c; Connected to the opposite end of capacitor 1 12 12 1297564 5 10 15 20 Grounding switches 92d and 92e are also connected to input 94. Switch % and coffee - like driven by high speed clock, pulse and phase locked loop (not shown) Each of the signal lines 102 is synchronized with the SYNC signal on 104. The pulse is typically 32 to 64 times faster than the sync frequency. The switch and 92e are operated simultaneously by the phase of the high speed clock, while the switches 92c and 9M are operated by the k pulse. The second non-overlapping phase operation. The sampling switch is terminated by the half of the SYNC rectangular wave, and the integrated value is transmitted to the ADC 84. The open state operates after the sampling open_, for example, the operation of the magical signal conversion, to re-integrate Figure 82. Figure 8 shows the waveform of the integrator, output % relative to the SYNC signal (line b) (line a). Since the accumulation of eight crying 82 can be reset at the beginning of each half cycle of the SYNC signal, and = The dual integrator is used in alternating half-cycles in the double bevel embodiment of Figures 5 and 6. Please refer back to Figure 7, in addition to the direct rotation of the ADC 84 to add (four) consecutive samples. The form provides a second round. By the delay circuit 106 This is achieved by connecting the ADC output signal, and adding half of the SYNC· to the addition Wei (10), which adds the delayed spots without delay signals. This is provided by the addition circuit (10). The incomprehensible signal-to-noise ratio is disclosed above, and those skilled in the art will appreciate that the structure of the integrator of the present invention provides good signal-to-subject effective filtering and can be implemented simply as a pWM motor system. Part of the system part. This filter ride is also subject to self-adjustment 2 certificate 'ie' 'Newton transmission Wei Zhi transmission zero and whole _ shape change> with positive 16 1297564 to suppress the introduction of the switch by the inverter switch Harmonics, as long as these changes are tracked by the correct SYNC signal. In this respect, it is understood that under normal circumstances, the frequency used for the given frequency conversion is fixed, but even if the frequency of the system is changed to 5 ^ ', the m can be changed and operated correctly. In the case of the seventh and eighth embodiment, it is limited by any latency required for the PLL to lock the new frequency. Although the invention has been described with respect to particular embodiments, it will be apparent to those skilled in the art that other modifications, modifications, and applications are possible. Therefore, it is intended that the invention not be limited to [Simple diagram of the diagram] Figure 1 is a schematic diagram showing the basic characteristics of a conventional pWM switching motor driver; 15 Figure 2 is a waveform diagram showing the motor drive current including signal and noise (chopping) components; Figure 3 is an overview The figure shows the basic concept of the first embodiment of the present invention; the 4A and 4B are diagrams illustrating the operation of the first embodiment; the fifth diagram is a schematic diagram illustrating the execution of the second embodiment of the present invention. The operation of the embodiment; Fig. 7 is a schematic circuit showing the execution of the third embodiment of the present invention. Figure 8 illustrates the operation of the third embodiment. [Main component representative symbol table of the drawing] 12...Rectifier circuit 10...PWM motor driver 17 1297564 14...Inverter 16...Bus line 18...Bus line 20...Motor 22a,b,c···Line 24--quot PWM control circuit 26...signal path 28a···sensing resistor 30...rate setpoint signal 3l···input waver 32...integrator circuit 34...sampling and holding circuit 36...first integrator 38...second integral 40...delay circuit 42...amplifier 44...series input resistor 46...integration capacitor 48...subtraction circuit 50...signal path 52...signal path 64...filter circuit 66...integrator/amplifier 68...first switch 70...second Switch 72... zero-crossing detector 74... integrating capacitor 82... switching capacitor 84... analog to digital converter 86... sampling switch 88... amplifier 90... integrating capacitor 92a···capacitor shunt switch 92b... first switch 92c··· Second switch 92d, e···grounding switch 94...amplifier input 96...amplifier output 100···capacitor 102...signal line 104...signal line 106···delay circuit 108···addition circuit
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