TWI296437B - Semiconductor package with stacked conductive via, and method for fabricating the same - Google Patents

Description

1296437 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package substrate with stacked conductive holes and a method for fabricating the same, and more particularly to a semi-conductive package substrate suitable for efficiently producing small apertures and stacked conductive vias And its method of production. [Prior Art] Due to the large-scale growth of various portable products such as the Internet and computers, the ball grid array (BGA) structure with a high density and multi-connected characteristics can be reduced by reducing the area of the integrated circuit. Packages such as flip-chips, wafer-size packages, and multi-chip cores are becoming the mainstream in the packaging market, and are often paired with high-performance chips such as microprocessors, chipsets, and graphics chips to perform even faster operations. Function, but because the 1€ package substrate with the wire has its own privacy restrictions, it transmits the chip signal and improves the bandwidth, control impedance and other functions. It becomes a high input/output (I/O) number. The development of the package is an obstacle. Therefore, when the integrated circuit process of the semiconductor wafer is reduced to 〇〇9μηι and the package size is also reduced to almost the same size as the wafer, how to develop a fine line, high density and small aperture which can be matched with it. Encapsulation of the substrate reduces the number of stacks of the substrate, and does not increase the excessive manufacturing cost. It is undoubtedly the weight of the integrated circuit and other related electronics industries entering the next generation of technology. R & D Division title. In the circuit board manufacturing industry, low cost, high reliability, and high wiring density have always been pursued. Therefore, a layering technique (build_called process) has been developed. The so-called build-up technique basically refers to stacking a plurality of dielectric layers and conductive layers on a surface of a core plate, and then forming a conductive via on the dielectric layer to provide electrical connection between the conductive layers. However, the number of build-up boards can be stacked more than one tier as required by actual industry conditions. To date, the technology of build-up boards has produced a number of multilayer boards loaded with various types of sub-components for use in a variety of commercial products. Generally, the manufacture of a build-up board requires the use of a double or multi-layer board as the core board to form a plurality of circuit layers on the surface of the core board. A schematic diagram of a conventional build-up multilayer circuit board is shown in FIG. Referring to FIG. 1 , a build-up multilayer circuit board 100 includes a circuit board 1〇1 as a core power 10 board and a two-line build-up structure 102. The board 101 includes two patterned circuit layers 103 and an insulating layer 1 therebetween. 〇4, a plated through hole (plated thr (10) gh h〇le, PTH) 105 is used as an electrical connection between the circuit layers 103. The circuit build-up structure 102 includes a circuit layer 106 and an insulating layer 〇7, and a conductive via 1 (conductive Via) is electrically connected between the circuit layers 106 of the circuit build-up structure 102. As shown in FIG. 1 , the circuit board ιοί is a two-layer circuit board (which may also be a multi-layer circuit board), and the line build-up structure 102 has two layers on the lower two sides of the circuit board 101, thus forming a six-layer layer. Board structure. In order to achieve a more sinful via hole design for a multilayer circuit board, Figures 2A through 2C show three via hole processes common in the industry. As shown in Fig. 2A, a 20-plated plated through hole (PTH) is schematically illustrated. The opening of the through hole extends through the circuit layer 2 〇 2, 203 overlying the surface of the insulating layer 201, and the conductive layer composed of the ferrous metal 204 is formed on the sidewall of the via hole. After the plating is completed, a conductive or non-conductive filler 205 is filled to fill the residual void to ensure the reliability of the via. 6 1296437 As shown in FIG. 2B, it is another form of via, a so-called bund via, whose opening extends into the interior of the insulating layer 206 but does not penetrate the circuit layer 207. After deposition of the bond layer 208, a conductive or non-conductive material 209 is filled in the recess to provide proper flatness for subsequent processes. 5, as shown in Fig. 2C, is a third type of through hole in which the opening of the blind hole extends through the insulating layer 210 but does not penetrate the circuit layer 21丨. After the via holes are filled in the conductive material 213, the circuit layer 212 is formed. Both of the above are common techniques, and it is quite easy to carry out in the above, however, in the case where the diameter of the through hole is less than 50 μm, the process will become difficult to implement. The reason is that the via portions are all burned by laser, and the current lower aperture to upper aperture ratio is about 80%, but the percentage of the aperture ratio will become smaller as the upper aperture decreases. When the upper aperture is 5〇μιη, only about 70% is left. When the upper aperture is 4〇μηι, only about 6〇% is left, which will result in the part of the upper and lower joints during the stacking process. Only 15 = ~ 4 〇 μ Π 1 , this product undergoes a deterioration test when the temperature difference changes rapidly and the reliability test is abrupt, a considerable proportion will break, this problem will indicate that the production of conductive holes and small aperture can not be produced in combination with each other. . SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a semiconductor package substrate with a stack of conductive holes and a method for fabricating the same, and to efficiently produce a small aperture and stack conductive The semiconductor package substrate of the hole. Another purpose of this month is to provide a semiconductor package substrate with stacked conductive holes and a method for manufacturing the same, which can reduce the reliability caused by the excessive difference between the upper and lower apertures of the laser hole during the conventional hole burning process. . In order to achieve the above object, the present invention provides a half-body package substrate having a stacked conductive hole, comprising: a circuit board, and a line build-up structure having a plurality of circuit layers and a plurality of conductive holes, wherein The aperture ratio of the aperture below the conductive aperture to the aperture of the upper aperture is (10) to (10)%, and the upper and lower conductive vias are stacked one above another. The above-mentioned semiconductor package wire with stacked conductive holes is especially suitable

10 15

20 For the case where the hole control is lower than 50 μm, it can maintain the hole-to-turn ratio of the upper hole and the lower hole to be 80 to 1 〇〇〇/0, and the hole diameter is preferably to the nearest. Right, the best is 95 to 100%. According to the foregoing semiconductor package substrate having stacked conductive vias, the present invention can be carried out in the following manner: (4) Providing a core circuit board having an upper surface, an opposite lower surface, and at least one circuit layer. (8) forming a first::: and a first photoresist layer on the upper surface and the lower surface of the private circuit board, and forming at least one opening at least one opening on the first photoresist layer Corresponding to the circuit layer, such that the first opening exposes a portion of the circuit layer. (4) Forming a first metal layer in the first opening as a conductive hole. The first photoresist layer and the first electrical layer covered by the first photoresist layer are removed. - forming a surface of the core circuit board having the metal layer formed thereon to remove the dielectric layer on the surface of the first metal layer. (7) in the 忒', the surface of the electric layer and the surface of the first metal layer form a second guide 8.1296437 electrical layer (g) forming a second photoresist layer on the surface of the second conductive layer to form a plurality of Two openings, the second openings being tied to the first metal layer. a pair of 5 (h) forming a second metal layer in the second openings

(1) The first conductive layer is removed. a second photoresist layer and the second layer covered by the second photoresist layer

10 15 (1) repeating steps (b) to (1) at least _ times on the surface of the second metal layer, forming a line of the line build-up structure and stacking the conductive hole structure. In the above-mentioned method, the openings are formed by photoresist exposure and development, and the upper diameter is almost the same, and a conductive hole having an aperture ratio of 8 〇 to 1 〇〇% can be obtained, but the yield in the process is increased, and It can mass produce semiconductor package substrates with small apertures and: conductive holes. The following is a description of the embodiments of the present invention by way of specific embodiments. Those skilled in the art can understand the other advantages and advantages of the present invention by the contents disclosed in the present specification. Executed or applied by other different 20 specific embodiments, the details in this specification ^

Two modifications and changes can be made without departing from the spirit and scope of the invention. U. Referring to FIG. 3A to FIG. 3L, a method for manufacturing a multi-layer circuit board according to an embodiment of the present invention is a two-layer or multi-layer circuit board structure, which is capable of performing a build-up process on both sides of the surface of the core power 9 1296437 road plate 300. To obtain a line-added structure, this figure only draws a one-sided line build-up structure. As shown in FIG. 3A, first, a core circuit board 300 is provided. The core circuit board 300 has an upper surface 300a and an opposite lower surface 300b and 5 each formed with at least one circuit layer 301 patterned by a line. The core circuit board 300 is formed with at least one plated via 300c as an electrical interconnection between the circuit layers 301. As shown in FIG. 3B, a first conductive layer 302 is formed on each of the upper and lower surfaces 300a, 300b by sputtering, evaporation, electroless plating, and chemical deposition, wherein the first conductive layer 302 can be, for example, Copper, 10 tin, recorded, complex, Qin, copper-alloy or tin-boat alloy. Or a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer may be used, and spin coating, ink-jet printing, screen printing or imprinting ( The first conductive layer 302 is formed by imprinting or the like. As shown in FIG. 3C, a first photoresist layer 303 is formed, for example, as a dry film or a liquid photoresist on the surface of the circuit layer 301, and at least a first surface is formed on the first photoresist layer 303 by exposure and development. The opening 304 is at least corresponding to the circuit layer 301, so that the first opening 304 exposes a portion of the circuit layer 301, wherein starting from FIG. 3C, in the drawing, both sides of the surface are manufactured 20 The same, so only the upper surface is displayed. As shown in FIG. 3D, a first metal layer 305, such as copper, is formed in the first opening 304 as a conductive via 305 by electroplating, and is electrically connected to the plating via 300c as a build-up wiring. Next, as shown in FIG. 3E, the first photoresist layer 303 and the first conductive layer 3〇2 covered by the first light 1296437 resist layer 303 are removed. As shown in FIG. 3F, a dielectric layer 306 is formed on the surface of the core circuit board 300 on which the first metal layer 3 is formed, and the dielectric layer 306 on the surface of the first metal layer 305 is removed by laser. The material used for the dielectric layer 306 can be, for example, 5 ABF (Ajinomoto Build-up Film) ^ BCB (Benzocyclo -buthene) ^ LCP (Liquid Crystal Polymer) ^ PI (P〇ly-imide), PPE (Poly (phenylene) Ether)), j>TFE (p〇iy (tetra-fluoroethylene)), FR4, FR5, BT (Bismal - eimide Triazine), aromatic nylon (Aramide), etc., or non-10-sensitive organic resin, or may be mixed with epoxy A group of materials such as resin and fiberglass. As shown in FIG. 3G, a second conductive layer 307 is formed on the surface of the dielectric layer 3〇6 and the surface of the first metal layer 3〇5 by sputtering, evaporation, electroless plating, and chemical deposition. The material of the second conductive layer 3〇7 and the forming method 15 are the same as those of the first conductive layer 302, and details are not described herein again. As shown in FIG. 3H, a second photoresist layer 308 is formed on the surface of the second conductive layer 3? 7, and the material used is, for example, a dry film or a liquid photoresist, and the second photoresist layer 308 is exposed and developed. In a manner, a plurality of second openings 3〇9 are formed, and the second openings 309 correspond to at least one of the first metal layers 3〇5. As shown in FIG. 31, a second metal layer 310 is formed by electroplating in the second openings 309, and the material used may be, for example, copper as a wiring layer. Next, as shown in FIG. 3J, the second photoresist layer 3〇8 and the second conductive layer 3〇7 covered by the second photoresist layer 308 are removed. Finally, as shown in FIG. 3B to FIG. 3j 11 -^296437, at least one of the lines of the line build-up structure 312 required by the steps of FIG. 3B to FIG. 3j 11 -^296, and the stack of conductive holes are required to be repeated on the surface of the second metal layer 310. 3〇, 士 ϋ 、 5,,, ° structure, as shown in Figure 3, which includes a circuit board 300, and a line Zengshi® α τ η ^ θ... structure 312, which has a plurality of lines ^ The layer 3 Π) and the plurality of conductive holes 3G5, wherein the hole diameter of the conductive hole is 80 to 1%, and the upper and lower conductive holes are overlapped by a circuit layer 310. As shown in the figure, the foregoing process is included in the line build-up structure 312 = surface, and an insulating protective layer 313 is formed, which may be a green paint solder layer (Solder Mask) 'Asian can be formed with an insulating protective layer opening μ, to show part of the line of the line build-up structure 312. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. 15 [Simple Description of the Drawings] Fig. 1 is a schematic view showing the structure of a multi-layered circuit board in a conventional layer. 2A to 2C are schematic views showing the structure of a conductive hole in the prior art. 3 to 3L are semiconductor package substrates having stacked conductive vias according to a preferred embodiment of the present invention. [Main component symbol description] 100 Multilayer circuit board 101 Circuit board Μ2, 312 line build-up structure 103 Patterned circuit layer 1〇4,1〇7,201,206,210 Insulation layer 105 Electrical via hole 12 1296437 106,202,203,207,211,212,301 Circuit layer

Conductive or non-conductive filler 208 electroplated conductive or non-conductive material 213 conductive material 108, 305 conductive hole 205 209 300 core circuit board 300b lower surface 302 first conductive layer 304 first opening 306 dielectric layer 308 second photoresist layer 310 Two metal layer 313 insulating protective layer 204 plating metal 300a upper surface 3〇〇c plating via 303 first photoresist layer 305 first metal layer 307 second conductive layer 309 second opening 312 line build-up structure 314 opening

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Claims (1)

1296437 X. Patent Application Range: 1. A semiconductor package substrate with stacked conductive holes, comprising: a circuit board; and a line build-up structure having a plurality of circuit layers and a plurality of apertures under the conductive holes The aperture ratio of the upper aperture is 8 〇 to 100%, and the upper and lower conductive vias are stacked one above the other. 2. The semiconductor package substrate of claim 1, wherein the circuit layers are copper. 3. The semiconductor package substrate according to claim 1, wherein the conductive holes are copper. 4. The semiconductor package substrate of claim 2, wherein the line build-up structure further comprises a plurality of conductive layers. 5. The semiconductor package substrate of claim 4, wherein the at least one of the conductive layers is selected from the group consisting of copper, tin, _, chrome, titanium, copper-cobalt alloy, tin-lead alloy, and conductive polymer. The group formed. 6. The semiconductor package substrate according to claim 1, wherein the aperture ratio is 90 to 1 Å. . - Method for manufacturing a semiconductor package substrate with stacked conductive holes, a package a first opening, the first opening is at least a lower surface, and a first portion is formed in sequence, and at least one corresponding to the circuit layer is formed on the first photoresist layer, so that the first opening is exposed to the 1296437 a circuit layer; (c) removing the first photoresist in the first opening (4); forming a dipole-metal layer as a conductive hole; a conductive layer; the first layer covered by the first photoresist layer Forming the first dielectric layer and moving the core " surface of the circuit board to form (f) the surface of the dielectric layer Wangu#人@增电层; Μ弟一金属层层形成形成第二guide 10 15 20 (g) forming a second photoresist on the surface of the second conductive layer: a plurality of second openings are formed in the resist layer, and the second openings are connected to the first metal layer; (h)一层 a layer in the second opening; 円 forming a metal layer to remove the second photoresist layer and the second conductive layer covered by the second photoresist layer as a line (1); and w — (1) The steps (b) to (1) are repeated at least once in the surface of the second metal layer to form a line of the wiring build-up structure and the stacked conductive via structure. 8. The method of claim 7, wherein the method of claim 7 is applied to the surface of the line build-up structure, an insulating protective layer is formed, and an insulating protective layer opening is formed to expose part of the line-added structure. The method of claim 7, wherein the first photoresist layer and the second photoresist layer are dry films or liquid photoresists. 10. The method of claim 7, wherein the method of claim 7 is The first metal layer and the second metal layer are formed by the method of claim 10, wherein the first metal layer and the second metal layer are The method of claim 7, wherein the first conductive layer and the second conductive layer are at least one selected from the group consisting of copper, tin, nickel, chromium, 5 titanium, and copper-chromium alloy. And the method of claim 12, wherein the first conductive layer and the second conductive layer are sputtered, vapor deposited, electrolessly plated, and chemically coated. One of the sediments is formed. The method of claim 7, wherein the 10 first conductive layer and the second conductive layer comprise a conductive polymer. 1 5 · The method described in claim 14 of the patent application, wherein A conductive layer and the second conductive layer are formed by one of spin coating, ink jet printing, screen printing, and embossing. The method of claim 7, wherein the dielectric layer is 15 layers. At least one selected from the group consisting of ABF (Ajin〇moto Build-up FUm), BCB (Benzocyclo-buthene) ^ LCP (Liquid Crystal • polymer), PI (P0ly_imide), ppE (Poly (phenylene ether)), PTFE (Poly (tetra) Photosensitive or non-photosensitive organic resins such as -flu〇r()ethylene)), FR4, FR5, BlXBismaleimide Triazine), aromatic polyamide 20 (Aramide), or a combination of epoxy resin and glass fiber. The method of claim 7, wherein the first opening and the second opening are formed by exposure and development. 18. The method of claim 7 (4) , which is used in step 16 1296437 (e) The exit surface of the dielectric layer of the first metal layer is removed. 17