1295664 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片，特別是指一種用於製備微 機電系統（MEMS，Micro Electro Mechanical System)，且 以標準互補式金乳半導體製程（Complementary Metal-Oxide1295664 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer, and more particularly to a method for fabricating a microelectromechanical system (MEMS) and using a standard complementary gold-milk semiconductor process ( Complementary Metal-Oxide
Semiconductor Process 5 CMOS Process )戶斤製借的晶片。 【先前技術】 目前，微機電系統例如致動器，是以SOC概念（ system on chip)整合在晶片上，特別是以標準互補式金氧 半導體製程所製備的CMOS晶片，因為是以規格化的標準 製程量產，品質穩定，同時價格也不昂貴，而成為整合微 機電系統的主要晶片種類。 參閱圖1、圖2，目前的CMOS晶片1包含一具有預定 設置微機電系統100之上表面111的基材n、一自該上表 面111向下形成在該基材11中的積體電路12，及複數彼此 相間隔地设置在該上表面111並分別對應地與該積體電路 12電連接的銲墊13，該複數銲墊13可分別供銲線（wire) 銲植（bonding)而使該晶片1以銲線對外電連接，每一銲 墊13是由銘及嫣等二種金屬所成的金屬層13ι彼此交錯堆 疊而成’且最遠離該積體電路12之最上層的金屬層131是 以紹構成以利銲線銲植，同時，以鎢構成之金屬層131的 結構悲樣是以鎢所成的多數塊粒彼此間隔地成陣列分布， 以減少相鄰兩金屬層131間的内應力分布。 參閱圖3、圖4，在以上述晶片i整合製備微機電系統 1295664 100，製得製備微機電晶片裝置2時，會經過至少一次的濕 蝕刻（wet etching)過程以成型微機電系統1〇〇的結構，而 濕蝕刻所使用的蝕刻液會同時將銲墊13的多數金屬層ΐ3ι 幾乎完全被蝕刻移除，進而使得積體電路12的最頂層（通 常是氧化層121)裸露出來。 而在銲墊13的金屬層131被蝕刻破壞之後，一來無法 再以探針對所製得的微機電晶片裝置2進行電性測試（ testing) ’二來裸露出的積體電路12頂層（即氧化層m) 也無法銲植銲線，供後續電子訊號的讀出/讀入。 因此，如何設計用於整合製備微機電系統1〇〇所用的 糕準互補式金氧半導體製程所製備的€]^〇8晶片1，使其銲 墊13不會因為濕蝕刻的過程而被蝕刻傷害，進而可以正確 知線進行電子訊號的讀出/讀入，是研製微機電系統J 〇〇時 必須解決的問題之一。 【發明内容】 因此，本發明之目的，即在提供一種用於整合製備微 機電系統’且為標準互補式金氧半導體製程所製備的cm〇s 晶片。 此外，本發明之另一目的，即在提供一種以標準互補 式金氧半導體製程所製備的CM〇s晶片，所整合製備出微 機電系統後的微機電晶片裝置。 *於疋，本發明一種用於製備微機電系統的晶片，是以 標準互補式金氧半導體製程製造，包含一基材、一積體電 路，及複數銲墊單元。 1295664 該基材具有一預定設置該微機電系統的上表面。 該積體電路自該上表面向下形成在該基材中。 該複數銲墊單元彼此相間隔地設置在該上表面上，每 一銲墊單元具有一與該積體電路電連接的電連接埠、一電 連接在該電連接埠上的第一銲墊，及一電連接在該電連接 埠上且與該第一銲墊相間隔的第二銲墊，該第一銲墊包括 複數分別以一第一金屬與一第二金屬構成且自該電連接埠 向上彼此父錯堆疊的金屬層，且最遠離該電連接埠的金屬 層是以該第一金屬構成，該第二銲墊包括複數分別以該第 金屬與第二金屬構成且自該電連接埠向上彼此交錯堆疊 的金屬層，及一形成在該等堆疊之金屬層上的保護層，該 保護層保護該第二銲塾的複數金屬層在製備該微機電系統 時不被鍅刻破壞。 另外’本發明一種微機電晶片裝置，包含一晶片，及 一微機電系統。 该晶片以標準互補式金氧半導體製程製造，具有一上 表面、一自該上表面向下形成的積體電路，及複數彼此相 間隔地設置在該上表面並分別對應地與該積體電路電連接 的銲塾單元，每一銲墊單元具有一與該積體電路電連接並 供對外電連接的電連接埠，及一設置在該電連接埠部分區 域上並與該電連接埠電連接的第二銲墊，該第二銲墊包括 複數分別以該第一金屬與第二金屬構成且自該電連接埠向 上彼此交錯堆疊的金屬層，及一形成在該等堆疊之金屬層 上而可保護該複數金屬層不受蝕刻破壞的保護層。 1295664 該微機電系統設置在該上表面上且與該積體電路電連 接。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中’類似的元件是以相同的編號來表示。 參閱圖5、圖6,本發明一種用於製備微機電系統的晶 片3的一較佳實施例，是以標準互補式金氧半導體製程製 造’包含一具有預定設置微機電系統1〇〇之上表面311的基 材31、一自該上表面311向下形成在該基材31中的積體電 路32 ’及複數彼此相間隔地設置在該上表面311的銲墊單 元4。 每一銲墊單元4具有一與該積體電路32對應電連接的 電連接埠41、一電連接在該電連接埠41上的第一銲墊42 ’及一電連接在該電連接埠41上且與該第一銲墊42相間 隔的第二銲墊43，該電連接埠41是以多晶矽（p〇iysilic〇n )為材料構成，對於濕蝕刻過程中所使用的蝕刻液具有高 度的抵抗力’而不易在整合製備微機電系統丨的濕鍅刻 過程中受到傷害，同時具有優良的導電性且可供銲線銲植 ’而不影響電子訊號的讀出/讀入。 第一銲墊42的結構與習知CMOS晶片1的銲塾13相 似，由銘及鎢等二種金屬所成的金屬層421自該電連接璋 1295664 向上彼此父錯堆疊而成，且最遠離該積體電路32之最上 層的金屬層421是以鋁構成，同時，以鎢構成之金屬層421 的結構態樣是以鎢所成的多數塊粒彼此間隔地成陣列分布 ，以減少各金屬層421之間的内應力分布。 第一1干墊43是相對該第一銲墊42較遠離該晶片3邊 緣二包括複數由鋁及鎢等二種金屬自該電連接埠41向上彼 此又錯堆豐的金屬層431，及一形成在該等堆疊之金屬層 431上的保瘦層432 (叩，第二銲墊43中由 鋁^鎢等二種金屬自該電連接埠41向上層疊的金屬層431 的又錯堆g順序與該第—銲* 42 ^目同，最遠離該電連接璋 2的金屬層431也是以！s構成，且，以鎢構成之金屬層 的、、、。構怨樣也是以鎢所成的多數塊粒彼此間隔地成陣列 分布，以減少相鄰兩金屬層431之間的内應力分布，同時 ^呆4層432則是以氮化碎（Si3N4)為材料形成，而可對 抗濕蝕刻過程中所使用的蝕刻液對其下的金屬層43ι蝕 傷害。 在此要特別說明的是，熟知互補式金氧半導體製程的 技2人仕，皆可自上述銲墊單元4中的結構，簡單推知雖 扃每一銲墊單元由電連接埠41與第一、二銲墊U、43構 成，然而其製造過程完全相容於標準互補式金氧半導體製 &中，，並無須特別加以設計或改變原先製冑，因此並無額 ^的製転增加成本，或是因為銲墊單元的結構設計而導致 曰曰^可靠度（reliability)不足的問題。由於如何以互補式 金氧半導體製程製備本發明之晶片並非本發明的重點所在 1295664 特性’而在整合製備出微機電系、统100之後，每一銲墊單 凡4仍可以電連接槔41對外銲植銲相讀出/讀人電子气號 ，同時以未打開保護層432之第二銲墊43供探針接觸以: 製備出的微機電晶片裝i 5進行電性測試，而確實以雙銲 塾的二道防線的設計’改善目前以標準互補式金氧半導體 製程所製備的CMOS晶片卜用於整合製備微機電系統1〇〇 而成微機電晶片裝置2時’其桿塾13會因為成型微機電系 統100結構的濕蝕刻製程而被蝕刻破壞，以致無法進行電 性測試，甚至無法銲植銲線以供後續電子訊號的讀出/讀入 的問題，確實達成本發明的創作目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 月b以此限疋本發明貫施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一俯視圖，說明習知用於整合製備微機電系統 ’且為標準互補式金氧半導體製程所製備的CMOS晶片； 圖2是一示意圖，說明圖1之CMOS晶片的局部結構 贅 圖3是一俯視圖，說明將一微機電系統整合製備於圖i 之CMOS晶片而成的一微機電晶片裝置； 圖4是一俯視圖，說明將一微機電系統整合製備於圖！ 之CMOS晶片上時，晶片之銲墊會蝕刻破壞而使積體電路 之一氧化層裸露； 11 1295664 圖5是一俯視圖，說明本發明一種以標準互補式金氧 半導體製程所製備之用於製備微機電系統的晶片的一較佳 實施例； 圖6是一不意圖’說明圖5之晶片的局部結構； 圖7是一俯視圖’說明將一微機電系統整合製備於圖5 之晶片而成的一微機電晶片裝置；及 圖8是一俯視圖，說明將一微機電系統整合製備於圖5 之晶片上後，晶片之一銲墊單元的結構。Semiconductor Process 5 CMOS Process). [Prior Art] At present, a microelectromechanical system such as an actuator is integrated on a wafer by a system on chip, in particular, a CMOS wafer prepared by a standard complementary MOS process because it is standardized. The standard process is mass-produced, the quality is stable, and the price is not expensive, but it becomes the main chip type for integrating MEMS. Referring to FIG. 1 and FIG. 2, the current CMOS wafer 1 includes a substrate n having a surface 111 on which a microelectromechanical system 100 is disposed, and an integrated circuit 12 formed in the substrate 11 downward from the upper surface 111. And a plurality of pads 13 disposed on the upper surface 111 and electrically connected to the integrated circuit 12, respectively, and the plurality of pads 13 can be respectively bonded by wire bonding. The wafer 1 is electrically connected to the outside by a bonding wire. Each of the bonding pads 13 is formed by stacking metal layers 131 made of two kinds of metals, such as 嫣 and 嫣, and the metal layer of the uppermost layer farthest from the integrated circuit 12. 131 is composed of a wire bonding weld, and the structure of the metal layer 131 made of tungsten is a pattern in which a plurality of blocks of tungsten are arranged in an array to be spaced apart from each other to reduce the interval between adjacent two metal layers 131. Internal stress distribution. Referring to FIG. 3 and FIG. 4, when the microelectromechanical system 1292664 100 is prepared by integrating the above-mentioned wafer i, and the microelectromechanical wafer device 2 is prepared, at least one wet etching process is performed to form the microelectromechanical system. The structure, and the etching solution used for wet etching, simultaneously removes most of the metal layer 焊3 of the pad 13 almost completely, thereby exposing the topmost layer of the integrated circuit 12 (usually the oxide layer 121). After the metal layer 131 of the pad 13 is etched and destroyed, it is no longer possible to electrically test the fabricated microelectromechanical chip device 2 with a probe to the top of the integrated circuit 12 exposed. Oxide layer m) It is also impossible to weld the bonding wire for subsequent reading/reading of electronic signals. Therefore, how to design a wafer 1 prepared by integrating the paste-complementary MOS process used in the preparation of the microelectromechanical system, so that the pad 13 is not etched by the wet etching process. Damage, and thus the correct reading of the electronic signal reading / reading, is one of the problems that must be solved when developing the MEMS J 〇〇. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a cm〇s wafer prepared for integrated fabrication of a microelectromechanical system' and which is a standard complementary MOS process. Further, another object of the present invention is to provide a microelectromechanical wafer device after microelectromechanical system integration by providing a CM 〇s wafer prepared by a standard complementary MOS process. * 疋, a wafer for fabricating a MEMS system of the present invention is fabricated by a standard complementary MOS process comprising a substrate, an integrated circuit, and a plurality of pad units. 1295664 The substrate has an upper surface that is predetermined to the microelectromechanical system. The integrated circuit is formed in the substrate downward from the upper surface. The plurality of pad units are disposed on the upper surface at intervals. Each pad unit has an electrical connection electrically connected to the integrated circuit, and a first pad electrically connected to the electrical connection. And a second bonding pad electrically connected to the electrical connection pad and spaced apart from the first bonding pad, the first bonding pad comprising a plurality of first metal and a second metal respectively and electrically connected thereto a metal layer stacked upwardly from each other, and a metal layer farthest from the electrical connection is formed of the first metal, and the second bonding pad includes a plurality of the first metal and the second metal and is electrically connected thereto. A metal layer stacked on top of each other, and a protective layer formed on the metal layers of the stack, the protective layer protecting the plurality of metal layers of the second solder fillet from being etched when the MEMS system is fabricated. Further, a microelectromechanical chip device of the present invention comprises a wafer, and a microelectromechanical system. The wafer is fabricated in a standard complementary MOS process, having an upper surface, an integrated circuit formed downward from the upper surface, and a plurality of spaced apart from each other on the upper surface and correspondingly corresponding to the integrated circuit An electrically connected soldering unit, each pad unit having an electrical connection 电 electrically connected to the integrated circuit and electrically connected to the external circuit, and a portion disposed on the electrical connection portion and electrically connected to the electrical connection a second solder pad comprising a plurality of metal layers respectively formed of the first metal and the second metal and staggered from each other in the electrical connection, and a metal layer formed on the stacked metal layers A protective layer that protects the plurality of metal layers from etching damage. 1295664 The MEMS is disposed on the upper surface and electrically coupled to the integrated circuit. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 5 and FIG. 6, a preferred embodiment of a wafer 3 for fabricating a microelectromechanical system of the present invention is fabricated by a standard complementary MOS process, comprising a microelectromechanical system having a predetermined arrangement. The substrate 31 of the surface 311, an integrated circuit 32' formed downward from the upper surface 311 in the substrate 31, and a plurality of pad units 4 provided on the upper surface 311 at intervals from each other. Each pad unit 4 has an electrical connection 41 electrically connected to the integrated circuit 32, a first pad 42' electrically connected to the electrical connection 41, and an electrical connection 41. a second pad 43 spaced apart from the first pad 42. The electrical connection port 41 is made of polysilicon (p〇iysilic〇n), and has a high degree of etching liquid used in the wet etching process. The resistance 'is not easily damaged during the wet engraving process of the integrated microelectromechanical system, and has excellent electrical conductivity and can be soldered to the wire' without affecting the reading/reading of the electronic signal. The structure of the first pad 42 is similar to that of the conventional CMOS wafer 1. The metal layer 421 made of two metals, such as tungsten and the like, is stacked up from the electrical connection 璋 1295664 and is farthest from each other. The uppermost metal layer 421 of the integrated circuit 32 is made of aluminum, and the metal layer 421 made of tungsten has a structure in which a plurality of blocks of tungsten are arranged in an array in an array to reduce each metal. The internal stress distribution between layers 421. The first dry pad 43 is opposite to the edge of the first pad 42 away from the edge of the wafer 3, and includes a plurality of metal layers 431 which are mutually offset from the electrical connection port 41 by two kinds of metals, such as aluminum and tungsten, and Forming the thin layer 432 on the stacked metal layer 431 (叩, the second solder pad 43 is composed of two kinds of metals such as aluminum, tungsten, and the like, and the metal layer 431 is stacked upward from the electrical connection 41 The same as the first welding, the metal layer 431 which is farthest from the electrical connection 璋2 is also composed of !s, and the metal layer made of tungsten is also formed of tungsten. Most of the granules are arranged in an array spaced apart from each other to reduce the internal stress distribution between the adjacent two metal layers 431, while the four layers 432 are formed of nitrided (Si3N4) material, which is resistant to the wet etching process. The etchant used in the etchant damages the underlying metal layer 43. It is specifically noted that the skilled CMOS process can be easily constructed from the pad unit 4 described above. It is inferred that although each pad unit is composed of an electrical connection 41 and first and second pads U, 43 The manufacturing process is completely compatible with the standard complementary MOS system & there is no need to specially design or change the original squeezing, so there is no cost to increase the cost, or because of the structural design of the pad unit. The problem of insufficient reliability is caused by how to prepare the wafer of the present invention in a complementary MOS process, which is not the focus of the present invention, the 1956656 characteristics, and after the integration of the microelectromechanical system 100, Each pad 4 can still be electrically connected to the external soldering phase to read/read the electronic gas number, and the second bonding pad 43 of the unprotected layer 432 is used to contact the probe to: The electromechanical chip package i 5 is electrically tested, and the design of the two-wire line of the double-welded wire is indeed improved. The CMOS wafer prepared by the standard complementary MOS process is improved for the integrated preparation of the MEMS. When the microelectromechanical chip device 2 is formed, its rod 13 is etched and destroyed due to the wet etching process of the structure of the microelectromechanical system 100, so that electrical testing cannot be performed, and even the welding wire cannot be soldered. The problem of reading/reading the subsequent electronic signals does achieve the creative purpose of the present invention. However, the above description is only a preferred embodiment of the present invention, and the present invention is not limited thereto. The scope of the invention, that is, the simple equivalent changes and modifications made by the invention in the scope of the invention and the description of the invention are still within the scope of the invention. [Fig. 1 is a top view, illustrating A CMOS wafer prepared for the integrated fabrication of a microelectromechanical system and being a standard complementary MOS process; FIG. 2 is a schematic view showing a partial structure of the CMOS wafer of FIG. 1. FIG. 3 is a top view showing a micro The electromechanical system integrates a MEMS wafer device fabricated in the CMOS wafer of Fig. i; Fig. 4 is a top view showing the integration of a MEMS system into the drawing! On a CMOS wafer, the pad of the wafer is etched and destroyed to expose one of the oxide layers of the integrated circuit; 11 1295664 FIG. 5 is a top view showing a preparation of the present invention in a standard complementary MOS process for preparation A preferred embodiment of a wafer of a microelectromechanical system; FIG. 6 is a partial view of the wafer of FIG. 5 not intended to illustrate; FIG. 7 is a top view illustrating the integration of a MEMS system into the wafer of FIG. A MEMS device; and FIG. 8 is a top plan view showing the structure of a pad unit of a wafer after a MEMS system is integrated on the wafer of FIG.
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