TWI293444B - Liquid crystal display device - Google Patents

Description

1293444 发明, invention description: Cross-reference of related applications This case is based on Korean Patent Application Nos. 2002-18942, P2002-61454 and P2002-87104, and the filing date is April 85, 2002, October 9, 2002, respectively. On December 30, 2002, the contents of each case are hereby incorporated by reference. TECHNICAL FIELD The present disclosure relates to a driver circuit for driving an active matrix driving display device and an active matrix driving display device having the driver circuit, particularly related to an improved display device display quality A driver circuit and a liquid crystal display device having the driver circuit. BACKGROUND OF THE INVENTION 15 Generally, a polycrystalline liquid crystal display (LCD) device has a high operating rate and low power consumption, but the fabrication process of a polycrystalline LCD device is complicated. A polycrystalline LCD device is usually used for a display device having a small screen. Amorphous LCD devices are commonly used in large screen display devices such as laptops (or laptops), LCD monitors, and high-definition televisions (HDTVs). 2〇 Recently, an amorphous LCD device uses a gate driver circuit formed on a glass substrate (or a thin film transistor substrate) of an LCD panel, thereby reducing the manufacturing steps of the LCD device. In general, the gate driver circuit includes a shift register and a wiring portion. The wiring section provides a shift register with a plurality of signals. The cloth 1293444 line w knife includes a plurality of wirings that affect the output signal output by the gate driver circuit. The output signal from the gate driver circuit may be distorted by the parent's wiring sense capacitance. Thus, the display quality of the LCD device is degraded. 5 The conventional gate driver circuit formed on a thin film transistor (TFT) substrate has the following problems when the gate driver circuit is used for a large screen and a high resolution amorphous LCD device. As the screen size of the LCD device becomes larger and the resolution of the LCD device becomes higher, the number of gate lines and pixels formed on the TFT substrate increases. Thus, as the gate 10 line and the number of pixels increase, the gate line is farther away from the gate driver, and the RC delay of the gate line is increased. The clock signal of the last gate line has a higher level than the clock signal of the first gate, and the former is large enough to cause distortion of the output signal. Therefore, it is not good quality. In addition, the power is generated between the wirings that are most transported away from the driver circuit and have a large line width. As such, the RC delay of the wiring increases. Therefore, a wiring structure is required in which the gate drive signal delay of the transmitted gate line is minimized. SUMMARY OF THE INVENTION The present invention is substantially free from the problems of the related art. A first feature of the present invention is to provide a driver circuit for driving an active matrix type drive display device for improving the display quality of a display device. A second feature of the present invention is to provide a display device having a driver circuit. 1293444 A third feature of the present invention is to provide a display device capable of providing a display structure having a higher display level and having a quality. In one aspect of the present invention, a driver circuit for driving an active matrix type drive display device is provided. The driver circuit includes a plurality of drive stages to the 5 and - dummy stages. The drive phases each include an output terminal and a control terminal. The output terminals of the current driving stage are coupled to control terminals that are to be cascaded to each other, and the drive stages each output a drive signal for controlling the switching device via the output terminals. The switching device is provided in an active matrix type drive display device. The dummy phase includes a dummy output terminal and a dummy control terminal 10. The dummy output terminal is coupled to the control terminal of the last drive stage of the plurality of drive stages, and outputs a dummy output signal for turning on or off the last drive stage. The dummy control terminal is lightly coupled to a dummy output terminal to be turned on or off by the dummy output signal. In another aspect of the invention, a liquid crystal display device is provided which includes a b-display portion and a gate driver. The display portion includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate has a plurality of gate lines connected to switching devices formed on a pixel, and the pixel lines are arranged in a matrix shape. The gate driver drives the switching device, and the gate driver includes a plurality of driving stages and a dummy stage. The drive phases each include an output terminal and a control terminal. At present, the output terminals of the driving phase are coupled to the desired/snap string, and the sorrowful control terminal. The drive phases each output a drive control signal to each of the brake lines via the output terminal for controlling the switching device. The dummy stage ^ includes a virtual readout terminal and a dummy control terminal. The dummy output terminal 1293444 is coupled to the control terminal of the last driving stage of the plurality of driving stages, and outputs a dummy output signal for turning on or off. The last driving stage is configured to be coupled to the dummy output signal. The dummy output terminal that is turned off by the turn-on. 5 10 15 In another aspect of the present invention, a liquid crystal display device includes a display portion, a data driver, and a gate driver. The display portion includes i) a first substrate having a pixel, a gate line and a data line, the pixel having a switching device coupled to the gate line and the data line, and ii) a second substrate Facing the first substrate; and a liquid crystal layer sandwiched between the first substrate and the second substrate. The data driver provides a data line with an image that is shaped adjacent to the display and coupled to the data line. The gate driver drives the switching device. The gate driver includes a -displacement register and a wiring portion. (4) Temporary storage ^ There are multiple stages of cascading each other. The displacement register is divided into the first group 5 3- 1/T' m τκ w~ force. The external signal is applied to each stage via the wiring portion, and the driving stages are each rotated via the -output terminal to drive the signal to the gate for controlling the switching device. The wiring portion includes a first-clock U-second pulse line, a third clock line, and a fourth: pulse line. A first clock signal is supplied to the first group via the first-clock line: a numbering phase. The phase of the second clock signal is different from the first clock signal by 18 〇 ^ and the priest is supplied to the No. 1 even number driving phase via the second clock line. The pulse signal is supplied to the second town via the third clock line and is driven by the odd number. The private second clock signal is supplied to the driving stage of the second group (four) via the fourth time street. 20 1293444 According to the present invention, the dummy output terminal of the dummy stage is connected to the control terminal ' of the last driving stage and is also connected to the dummy control terminal of the dummy stage. In addition, the wiring portion further includes third and fourth clock lines in addition to the first and second clock lines, and the first and second clocks CK and CKB are applied via the third and fourth clock lines. . LCD devices provide high display quality. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other features and advantages of the invention will be more apparent from the detailed description of the preferred embodiments. The liquid crystal display panel is not shown in Fig. 2, the block diagram shows the displacement register of the driving gate driver circuit of Fig. 1; the third figure shows the driving phase of the circuit diagram of Fig. 2; 15 Fig. 4 is a plan view showing Fig. 3 The layout of the driving stage; Figure 5 is a circuit diagram showing the dummy phase of Figure 2; Figure 6 is a layout showing the layout of the dummy phase of Figure 5; Figure 7 is a line diagram showing the output signal waveform of the dummy phase, the dummy phase has Figure 2 is the same circuit in the driving phase; 20 Figure 8 is a line diagram showing the output signal waveform of the dummy phase of Figure 5; Figure 9 is a circuit diagram showing the driving phase and the dummy phase according to the second embodiment of the present invention; 10 is a block diagram showing a displacement register for driving a gate driver circuit in accordance with a third embodiment of the present invention; 1293444 FIG. 11 is a line diagram showing the gate drive of FIG. The output signal waveform of the circuit; FIG. 12 is a layout diagram showing the third and fourth clock line configurations of the gate driver circuit of FIG. 10; 5 FIG. 13 is a layout diagram showing the first and second of the displacement register And another example of the connection between the fourth clock line; FIG. 14 is a layout diagram showing the wiring structure of the displacement register according to the fourth embodiment of the present invention; FIG. 15 is a layout diagram showing the fourth picture The displacement of the wiring structure is temporarily stored; and FIG. 16 is a layout diagram showing the wiring structure of the displacement register according to the fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 3 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a schematic view showing a liquid crystal display according to a first embodiment of the present invention. The panel 'and the brother 2' is a block diagram showing the displacement register of the driver circuit between the driver and the driver. 20, a liquid crystal display panel according to a first embodiment of the present invention includes a TFT substrate 100, a color filter substrate (not shown), and a liquid crystal layer (not shown) interposed therebetween. The TFT substrate 100 is interposed between the color filter substrate. The TFT substrate 100 has a display area (DA) and a peripheral area (PA). Complex 10 1293444 pixels are arranged in a matrix in the display area. Each of the pixels includes a thin film transistor (TFT) 110 and a pixel electrode 120 coupled to the TFT 110. The TFT 110 is connected by a data line (DL) and a gate line (GL). The data line extends in a first direction and the brake line extends in a second direction that is substantially perpendicular to the first direction. The resolution of the liquid crystal display panel 200 is determined according to the number of pixels. When the number of pixels is m*n, the resolution is m*n, and the TFT substrate 100 has m data lines (DL1, DL2, ..., DLm) and η gate lines (GL1, GL2, ..., GLn). The data driver circuit 140 is disposed in the first peripheral area (PA), wherein one of the data lines (DL1, DL2, ..., DLm) is disposed. A gate driver circuit 130 is disposed in the second peripheral region (PA), wherein one end of the gate lines (GL1, GL2, ..., GLn) is disposed. The gate driver circuit can be fabricated by the same method of pixel formation in the display area (DA) method. The gate driver circuit 13A includes a shift register. As shown in Fig. 2, the shift register 131 includes a plurality of stages (SRC1, ..., SRCn + Ι) which are cascaded to each other. In detail, the shift register 131 includes an η (even) drive phase (SRC1, ..., SRCn) and a dummy phase (SRCn + Ι). The η drive phase (SRC1,...,SRCn) sequentially outputs the gate drive signal to 20 11 gate lines (0[1,.", 01^). 11 drive stage (311 (:1,...,811 (:11) output terminals are each connected to the control terminal (CT) of the previous drive stage. Current-carrying terminals of the η drive stage (SRC1,...,SRCn) (CR) is each connected to the input terminal (IN) of the next drive stage. The start signal (ST) (instead of the output signal) is applied to the input terminal (IN) of the first drive phase (SRC1). 1293444 Dummy phase (SRCn+ l) The input terminal (IN) is connected to the current-carrying terminal (CR) of the nth drive phase (SRCn). The output terminal (OUT) of the dummy phase (SRCn+Ι) is connected to the nth drive phase (SRCn) The control terminal (CT), the dummy phase (SRCn+l) controls the nth drive phase (SRCn). The output terminal (OUT) of the dummy phase 5 (SRCn+1) is also connected to the control of the dummy phase (SRCn+1). Terminal (CT). Thus, the dummy phase (SRCn+1) is controlled by the output signal output from the dummy phase (SRCn+1). The wiring portion 132 is disposed adjacent to the shift register 131. The wiring portion 132 is temporarily stored. The device 131 provides a complex signal. In detail, the wiring portion 132 includes a start signal line (STL), a first power supply line (VDDL), and a first clock. a line (CKL), a second clock line (CKBL), and a second power line (VSSL). The start signal (ST) is supplied to the input terminal of the first driving stage (SRC1) via the start signal line (STL) ( IN) The start signal (ST) is a pulse signal synchronized with a vertical sync signal (Vsync) output from an external figure 15-shaped controller (not shown). The first power line (VDDL) is coupled to the η drive stage ( SRC1, ..., SRCn) and the dummy phase (SRCn+1), and a first power supply voltage signal (VDD) is applied to the η driving phase (SRC1, ..., SRCn) via the first power supply line (VDDL) and The dummy phase (SRCn+1). The second power supply 20 line (VSSL) is coupled to the η drive phase (SRC1, . . . , SRCn) and the dummy phase (SRCn+1), and a second power supply voltage signal ( VSS) is applied to the η driving phase (SRC1, . . . , SRCn) and the dummy P segment (SRCn+1) via the second power line (VSSL). The first clock signal (CK) is transmitted through the first time. The pulse line (CKL) is added to the 1293444 odd drive phase (SRCl, SRC3, ...) and the dummy phase (SRCn+1). The second clock signal (CKB) has 180 relative to the first clock signal (CK). Phase difference, the second clock signal (CKB) is applied to the even-numbered lines and a second driving phase via a clock line (CKBL) (SRC2, ..., SRCn). 5 In this way, since the output signals (OUT1, ..., OUTn) with the active period (high level period) are generated sequentially, during the activation of the output signals (OUT1, ..., OUTn), corresponding to the output signals (OUT1, ..., 〇UTn) The gate lines (GL1,..., GLn) are sequentially selected. Fig. 3 is a circuit diagram showing the driving phase of Fig. 2, and Fig. 4 is a plan view showing the layout of the driving phase of Fig. 103. The nth driving phase (SRCn) is shown in Figures 3 and 4, and the other driving phases (SRC1, ..., SRCn-Ι) have the same circuit of the nth driving phase (SRCn). Referring to Figures 3 and 4, the nth driving phase (SRCn) of the shift register 131 includes a rising portion 131a, a falling portion 131b, a rising driver portion 15 minute 131c, a falling driver portion 131d, and a current carrying current. The output portion 131e. The nth driving stage (SRCn) has an input terminal (in), an output terminal (OUT), a control terminal (CT), a clock terminal (CKT), a second power line terminal (VS ST), and a first Power line terminal (VDDT) and a current-carrying output terminal (CR). The rising portion 131a includes a first NMOS transistor (NT1). a clock signal (CK) is applied to the drain of the first NMOS transistor (valence 1), the gate of the first NMOS transistor (NT1) is coupled to a first node (N1), and the first NMOS is electrically The source of the crystal (NT1) is coupled to the output terminal (OUT). 13 1293444 The falling portion 131b includes a second NMOS transistor (NT2). a drain of the second NMOS transistor (NT2) is coupled to the output terminal (〇υτ), a gate of the second NMOS transistor (ΝΤ2) is coupled to a second node (Ν2), and the second NMOS The source of the transistor (ΝΤ2) is coupled to the second electrical 5 source line terminal (VSST). The boost driver portion 131c includes a capacitor (C), NMOS transistors (NT3, NT4, NT5, NT6, NT7, NT8, and NT9). The capacitor is coupled between the first input node (N1) and the output terminal (OUT). The drain of the third transistor (NT3) is coupled to the first power line terminal (VDDT), the gate of the third transistor (NT3) 10 is coupled to the input terminal (IN), and the third transistor (NT3) The source is coupled to the first input node (N1). The drain and the gate of the fourth transistor (NT 4) are commonly connected to the first power line terminal (VDDT), and the source of the fourth transistor (NT4) is coupled to the gate of the fourth transistor (NT5). . The drain of the fifth transistor (NT5) is coupled to the first power line terminal (VDDT), the gate of the fifth transistor (NT5) I5 is coupled to the source of the fourth transistor (NT4), and the fifth The source of the transistor (NT5) is coupled to the second node (NT2). The drain of the sixth transistor (1^6) is connected to the source of the third transistor (NT3), and the gate of the sixth transistor (NT6) is coupled to the second node (N2), the sixth transistor The source of (NT6) is connected to the second power line terminal (vsST). The twenty-seventh transistor (9) is the connection of the drain to the input terminal (IN), the gate of the seventh transistor (NT7) is connected to the second node (N2), and the source of the seventh transistor (NT7) Connect to the second power line terminal (VSST). The drain of the eighth transistor (NT8) is coupled to the second node (N2), the gate of the eighth transistor (NT8) is coupled to the input terminal (IN), and the source of the eighth transistor (NT8) Connect 14 1293444 to the second power line terminal (VSST). Although not shown in FIG. 3, the source of the eighth transistor (NT8) may be coupled to the third power line terminal, via which the third power supply voltage signal is supplied, which has a second power supply voltage signal (VSS) Lower power supply 5 level. The ninth transistor (?) is connected to the output terminal (in), the gate of the ninth transistor (NT9) is connected to the control terminal (CT), and the ninth transistor (NT9) The source is connected to the second power line (VSST). The drop driver section includes NMOS transistors (NT10, NT11, NT12, and NT13). In detail, the drain of the tenth transistor (>^10) is connected to the second 10 node (N2), and the gate of the tenth transistor (NT10) is connected to the first node (N1), and The source of the ten transistor (NT10) is connected to the second power line terminal (VSST). The eleventh transistor...the gate of the eleventh transistor is connected to the source of the fourth transistor (NT4), the gate of the eleventh transistor (NT11) is connected to the first node (N1), and the tenth The source of one transistor (NT11) is connected to the 15th power supply line (VSST). The drain of the twelfth transistor (NT12) is connected to the first node (N1), and the twelfth transistor (NT12) The gate is connected to the control terminal (CT), and the source of the twelfth transistor (NT12) is coupled to the second power line terminal (VSST). The current-carrying output portion 131e includes a fourteenth transistor (NT14). The tenth 20th transistor (NT14) has a drain connected to the clock terminal (CKT), and the fourteenth transistor (NT14) is connected to the first node (N1), and the fourteenth The source of the crystal (NT14) is coupled to the current-carrying output terminal (CR). Thus, the current-carrying output portion 131e transmits the clock signal (CK or CKB) to the input terminal (IN) of the next driving stage.

π repair (.more) replaces the mirror page 1293444 in the ηth drive phase (SRCn), the current-carrying signal (CR) output from the previous stage is input to the input terminal (IN) of the nth drive phase (SRCn), and the third The transistor (NT3) is turned on by the current carrying signal (CR). The first node (N1) potential is changed from the second supply voltage level (VSS) to the first supply voltage level (VDD). Then, when the potential of the fifth transistor (NT4), the fifth transistor (NT5), and the first node (N1) is raised, the tenth transistor (NT10) is turned on. When the tenth transistor (NT1〇) is turned on, the potential of the second node (N2) is changed to the second power supply voltage level (VSS). As such, the second transistor (NT2) is turned off.

When the potential of the first node (N1) rises, the first transistor (NT1) is turned on, and the clock signal (CK) having a high voltage level is transmitted to the output terminal (OUT). The output terminal (OUT) output voltage is charged to the boot capacitor (C), and the gate voltage of the first transistor (NT1) rises above the first supply voltage level. Thus, the first transistor (NT1) maintains an on state. When the output signal of the dummy phase (SRCn+Ι) having the high voltage level is output 15 to the control terminal (CT) of the nth driving phase, the twelfth transistor and the thirteenth transistor (ΝΤ12, ΝΤ13) are Turn on.

When the twelfth transistor (ΝΤ12) is turned on, the potential of the first node (Ν1) is changed from the first power supply voltage level (VDD) to the second power supply voltage level (VSS). Then the tenth transistor (ΝΤ10) is turned off. Thus, the second node (Ν2) 20 potential is changed to the first supply voltage level (VDD) by the second supply voltage level (VSS) by the fourth and fifth transistors (ΝΤ4, ΝΤ5). The dummy phase output signal outputted by the control terminal (CT) turns on the thirteenth transistor (ΝΤ13), and the thirteenth transistor (ΝΤ13) and the second transistor (ΝΤ2) output the second power supply voltage signal (VSS) to the output terminal. (OUT). 16 1293444

When the second power supply voltage signal (VSS) is output to the output terminal (OUT), the seventh transistor and the eighth transistor (NT7, NT8) are turned on, and applied to the nth driving stage input terminal (IN) (n_1) The drive stage output signal is changed to a high voltage level. 5 In particular, when the second power supply voltage signal (VSS) is output to the output terminal (OUT) and the high level output signal output by the (n-1)th drive stage is supplied to the input node (IN), the eighth transistor (ΝΤ8) ) is turned on. Thus, the output signal output from the (η-1) drive phase is discharged to the second power supply line terminal (VSST).

In addition, the ninth transistor (ΝΤ9) is turned on by the control terminal (CT) applied to the dummy 10 stage (SRCn+Ι) output signal, and the discharge is supplied to the high level of the (n_l) drive stage of the input node (IN). The output signal is quasi-output, thus preventing the first transistor (NT1) from being turned on.

Although the twelfth transistor (NT12) is turned off by 15 when the output signal potential of the dummy phase (SRCn+Ι) supplied from the control terminal (CT) is changed to the off voltage level, the second node (N2) borrows The fourth and fifth transistors (NT4, NT5) maintain the first supply voltage level. Thus, the second transistor (NT2) maintains an on state, and the second power signal (VSS) is output to the output terminal (OUT). Fig. 5 is a circuit diagram showing the dummy phase of Fig. 2, and Fig. 6 is a plan view showing the layout of the dummy P segments of Fig. 5. In the fifth and sixth figures, the same reference numerals indicate the same elements of the nth driving stage (SCRn) of Fig. 1, and thus the detailed description of the same elements will be deleted. Referring to Figures 5 and 6, the dummy phase (SRCn + Ι) includes a raised portion 131a, a falling portion 131b, a raised driver portion 131c, a falling driver portion 131d, and a current carrying output portion 131e. The control terminal of the dummy phase 17 1293444 (SRCn+1) is connected to the output terminal of the dummy phase (SRCn+1). Thus, the dummy phase (SRCn+Ι) is controlled by the output signal of the dummy phase (SRCn+Ι). The transistor size of the transistor (NT12,) 5 connected to the dummy terminal (SRCn+1) control terminal is changed from that of the transistor (NT12) in the ηth driving phase (SRCn), so that the dummy phase can be maintained (SRCn The output signal of +l) goes through a predetermined period of time. Hereinafter, the transistor size indicates the ratio (W/L) of the transistor channel width (W) to the transistor channel length (L). For example, the transistor of the dummy phase (S R C η +1) of the transistor (N T12 ') has a size larger than that of the transistor of the transistor (NT 12) of the nth driving phase (SRCn) by 10 times. Usually the transistor size is determined by the channel width (W). For example, the channel width (w,) of the transistor (NT12,) of the dummy phase (SRCn+1) is about 10 times smaller than the channel width (W) of the transistor (ΝΤ12) of the nth driving phase (SRCn). As shown in Figs. 4 15 and 6, the channel width (W,) of the transistor (NT12) of Fig. 6 is approximately 10 times smaller than the channel width (W) of the transistor (NT12) of Fig. 4. Although the high level output signal of the dummy phase (SRCn+l) is fed back to the control terminal (CT) of the dummy phase (SRCn+1), it depends on the transistor size of the transistor (NT12), after a predetermined period of time tenth The two transistors (NT12,) are turned 20 through. Thus, after the high level output signal of the dummy phase (SRCn+1) is fed back to the control terminal (CT) of the dummy phase (SRCn+1), the tenth transistor (NT10) is not turned off, so the second node (N2) The second supply voltage level (VSS) can be maintained for a predetermined period of time. Therefore, the output terminal of the dummy phase (SRCn+i) can maintain a high voltage level for a predetermined period of time. 1293444 After a predetermined period of time, when the twelfth transistor (NT12) is turned on, the tenth transistor (NT10) is turned off, and the second node (N2) potential is from the second power voltage level (vss). Change to the first supply voltage level (VDD). When the potential of the second node (N2) is changed to the first power supply voltage level (VDD), the transistor 5 (NT2) is turned on, so the second power supply voltage (VSS) is output to the dummy phase (SCRn+Ι). Output terminal (OUT). Further, the twelfth transistor (NT 13) connected to the gradation driving phase (sRCn) of the control terminal (CT) is removed in the dummy phase (SRCn + Ι). As shown in Fig. 6, the thirteenth transistor (NT13) of Fig. 4 is divided by 10 in the dummy phase (SRCn+1}. Thus, since only the second transistor (NT2) outputs the second power supply voltage ( Vss) to the output terminal (OUT), so after a predetermined delay, the second power supply voltage (VSS) is output to the output terminal (OUT). Figure 7 is a line diagram showing the dummy phase output of the same circuit with the driving phase of Figure 2. #5虎 waveform' Figure 8 is a line graph showing the output signal waveform of the dummy phase of Figure 5. The X axis represents time (differential) and the y axis represents voltage (volts). Refer to Figure 7 to sequence in the drive phase. The output signal (OUTn-1, OUTn) with high voltage level is output, and the output voltage (OUTn+Γ) is output during the dummy phase (SRCn+Ι) operation. In the seventh figure, the dummy phase (SRCn+Ι) has a drive. In the same circuit of the phase, the output terminal of the dummy phase (SRCn+Ι) is connected to the control terminal of the 2〇 dummy phase (SRCn+Ι). Once the signal is output from the output terminal of the dummy phase (sRCn+1) (0 UT η +1 ') when the potential is changed to a high voltage level via the output signal (OUTn) of the nth driving phase (SRCn), The voltage level output signal (OUTn+ Γ) is applied to the control terminal of the nth drive stage (SRCn) and the control terminal of the dummy stage (SRCn+1). 19 1293444 Output output by the output terminal of the dummy stage (SRCn+1) The signal (OUTn+Γ) potential is changed to the off voltage level (or low voltage level) by the output signal (OUTn+1 ') of the control terminal of the dummy stage (SRCn+Ι). Thus, the output signal (OUTn+1') does maintain the high voltage level through the 5 segment predetermined hold and drops to the turn-off voltage level. The maximum voltage level of the output signal (OUTn+1 ') is much smaller than the output signal (〇UTn) The maximum voltage level. However, when the dummy phase (SRCn+l) has the circuit of Figure 5, as shown in Figure 8, the output signal (OUTn+1) has a more stable output signal (OUTn+Γ). The waveform is set. After the output signal (OUTn-l, OUTn) with high voltage level is sequentially output in the driving phase, the dummy phase (SRCn+l) is operated to output the output signal (OUTn+1). The potential of the output signal (OUTn+1) output from the output terminal of SRCn+l) is output by the η drive stage (SRCn) When the number (OUTn) 15 is changed to the on voltage level (or the high voltage level), the output signal having the on voltage level (〇UTn+1) is applied to the control terminal of the nth driving stage (SRCn) and the control terminal Control terminal of the dummy phase (SRCn+1). Then, although the output signal (OUTn+1) is applied to the control terminal of the dummy phase (SRCn+1), the output output from the output terminal 20 of the dummy phase (SRCn+1) The signal (0UTn+l) is not instantaneously changed to the power-off level. Instead, the output signal (OUTn+1) output from the output terminal of the dummy stage (SRCn+1) is turned off after a predetermined period of time. quasi. Therefore, the output signal (0UTn+l) can maintain a high voltage level for a predetermined period of time. 20 1293444 produces an output signal (〇UTn+1) that has a voltage level that is almost equal to the output signal (〇UTn) _. Therefore, the nth driving phase (SRCn) can be stably driven by the output signal (?n+1) of the dummy phase (SRCn+Ι). < ER_ Figure 9 is a circuit diagram showing a -5 driving phase and a dummy phase in accordance with a second embodiment of the present invention. Referring to Fig. 9, the shift register 133 according to the second embodiment of the present invention includes an η driving phase (SRC1, ..., SRCn) and a dummy phase (SRCn + Ι). The nth driving stage (SRCn) includes a rising portion 133a, a falling portion 133b, a rising driver portion 133c, and a lowering driver portion 10 minutes 133d. The rising portion 133a includes a first NMOS transistor (NTla). . The clock signal (CK) is applied to the drain of the first NMOS transistor (1^1&), the gate of the first NMOS transistor (NTla) is coupled to the first node (Nla), and the first NMOS device The source of the crystal (NTla) is coupled to the output terminal 15 (OUTn). The falling portion 133b includes a second NMOS transistor (NT2a). The drain of the second NMOS transistor (?^2&) is coupled to the output terminal (OUTn), the gate of the second NMOS transistor (NT2a) is coupled to the second node (N2a), and the second NMOS The source of the transistor (NT2a) is coupled to the second power line 20 terminal (VSST). The boost driver portion 133c includes a capacitor (C), NMOS transistors (NT3a, NT4a, NT5a). The third transistor of the third transistor < D 3 & is connected to the first power line terminal (VDDT), the gate of the third transistor (NT3a) is coupled to the input terminal (IN), and the third transistor ( The source of NT3a) is linked to the 21st 1293444 node (Nla). The drain of the fourth transistor (NT4a) is connected to the first node (Nla). The gate of the fourth transistor (NT4a) is connected to the control terminal (ct), and the source of the fourth transistor (NT4a). It is connected to the second power line terminal (VSST). The immersion of the fifth transistor (NT5a) is connected to the first node 5 (Nla). The gate of the fifth transistor (NT5a) is connected to the second node (N2a), and the fifth transistor (NT5a) The source is connected to the second power line terminal (VSST). The transistor size of the third transistor (NT3a) is approximately twice the size of the transistor of the fifth transistor (NT5a). The drop driver portion 133d includes an NMOS transistor (NT6a, 10 NT7a). In detail, the drain and the gate of the sixth transistor (>〇^) are commonly connected to the second power line terminal (VDDT), and the source of the sixth transistor is connected to a second node (N2a). The gate of the seventh transistor (1^丁7&) is connected to the second node (N2a), and the gate of the seventh transistor (NT7a) is connected to the first node (N21) And the source of the seventh transistor (NT7a) is coupled to the second 15 power line terminal (VSST). The transistor size of the sixth transistor (NT6a) is about larger than the transistor size of the seventh transistor (NT7a). When the output signal of the (n-1)th drive phase (SRCn-Ι) is output to the input terminal (IN) of the nth drive phase (SRCn), the seventh transistor (NT7a) is turned on. When the seven transistor (NT7a) is turned on, the potential of the second node (N2a) is changed from the first power supply voltage level (VDD) to the second power supply voltage level (VSS). Then even the seventh transistor (NT7a) is turned on. Conduction, because the sixth transistor (NT6a) transistor size is about 6 times larger than the transistor size of the seventh transistor (NT7a), and the second node (N2a) still maintains the second power supply voltage level (VSs). High voltage bit When the output signal 22 1293444 (OUTn+1) of the dummy phase (SRCn+Ι) is recovered via the control terminal (CT) of the nth driving phase (SRCn), the seventh transistor (NT7a) is turned off. Thus, the second The node (N2a) potential is changed to the first power supply voltage level (VDD) by the second power supply voltage level (VSS) by the sixth transistor (NT6a). 5 Even when controlled via the ηth drive stage (SRCn) When the output signal potential of the dummy phase (SRCn+Ι) applied to the terminal (CT) is changed to the turn-off voltage level, and the fourth transistor (NT4a) is turned off, the second node is caused by the sixth transistor (NT6a). The first power supply voltage level (VDD) is maintained. Thus, the second transistor (NT2a) maintains an on state, and the output terminal (OUTT) has a second power supply voltage level (VSS). As shown in FIG. 9, dummy The stage (SRCn+Ι) includes a rising portion 133a, a falling portion 133b, a rising driver portion 133c and a lowering driver portion 133d. The control terminals of the dummy phase (SRCn+Ι) are connected to the dummy phase (SRCn+Ι) The output terminal. Thus, the dummy phase (SRCn+1) 15 is controlled by the output signal of the dummy phase (SRCn+Ι). The transistor size of the transistor to the control terminal of the dummy phase (SRCn+Ι) is changed from the transistor size of the transistor connected to the control terminal of the ηth driving stage (SRCn), so the dummy phase is maintained (SRCn+Ι) The output signal goes through a predetermined period of time. 20 For example, the transistor of the dummy phase (SRCn+1) has a transistor size approximately 10 times smaller than that of the transistor of the nth driving phase (SRCn) (NT4). Thus, shortly after the high level output signal of the dummy phase (SRCn+Ι) is fed back to the control terminal (CT) of the dummy phase (SRCn+Ι), since the fourth transistor (NT4') is not turned off, the first The seven transistors (9) are not immediately turned on. 23rd 1293444 The four node (N4) maintains the second supply voltage level (VSS) for a predetermined period of time. Therefore, the output terminal of the dummy phase (SRCn+Ι) maintains the high voltage level for a predetermined period of time. After a predetermined period of time, when the fourth transistor (NT4,) is turned on, the fifth seventh transistor (NT7a) is turned off, and the fourth node (N4) potential is changed by the second power supply voltage level (VSS). At the first supply voltage level (VDD). When the potential of the fourth node (N4) is changed to the first power supply voltage level (VDD), the second transistor (NT2a) is turned on, so the second power supply voltage level (VSS) is output to the dummy stage (SRCn). +Ι) Output terminal (OUT). 10 The control terminal (CT) of the dummy phase (SRCn+Ι) is connected to the output terminal (〇UTn+1) of the dummy phase (SRCn+1), so the dummy phase (SRCn+1) can maintain stable operation. In addition, the gate driver circuit does not require another external wiring, via which the control signal is applied to the control terminal (CT) of the dummy phase (SRCn + Ι). 15 This prevents the capacitance between the external wiring and the other wiring, and the signal applied to the gate driver circuit can be undelayed. 10 is a block diagram showing a displacement register for driving a gate driver circuit according to a third embodiment of the present invention, and a second diagram showing a waveform of an output signal of the gate driver circuit of FIG. . The following r i" 20 is an even number smaller than "η". Referring to Figure 1 , a gate driver circuit 150 in accordance with a third embodiment of the present invention includes a shift register 151. The shift register 151 is divided into a first group G1 and a second group G2. The first group and the second group G1 and G2 each comprise a plurality of stages. The wiring portion 152 is disposed adjacent to the displacement register 15ι. 24 1293444 The wiring portion 152 provides a plurality of signals to the shift register 151. In detail, the wiring portion 152 includes a start signal line (STL), a first power line (VDDL), a -th clock line (CKL1), a second clock line (ckbli), and a second power line. (VSSL), a third clock line (CKL2), and a fourth clock line 5 (CKBL2). A first clock signal (ck) is applied to the odd drive phase (SRC1, ..., SRC3) of the drive phase (SRC1, · "SRCi_1}) of the first group G1 via the first clock line (CKL1). The clock signal (CK) is applied to the odd-numbered driving phase (SRCi+1) of the driving phase (SRCi, ..., SRCn) of the second group G2 via the third clock line (CKL2). Relative to the first clock The signal (CK) has a second clock signal (CKB) with a phase difference of 18 degrees via the second clock line (CKBL丨), applied to the driving phase of the first group gi (SRC1, ..., sRCi-Di even drive stage ( SRC2, ...). The second clock signal (CKB) is added to the second group 02 drive phase (SRCi, ..., stage (f) even 15 drive stage (SRCi, via the fourth clock signal (CKBL2). Thus, SRCn). Some parts of the η-drive phase (SRC1, . . . , SRCn) are in response to the first and second day sigma h CK and CKB, the first and second clock signals CK and CKB The other portions of the η driving phase (SRC1, ..., driving phase ^, ..., 20 SRCn) are respectively applied to the first and second clock lines c KL 丨 and c κ BL 回应 in response to the first second The clock signal CK and CKB, the first and the second clock signal CK & CKB line and are applied to the n-th driving stage (SRCl via the third and the second clock line CKL2 and seasons CKBL2, ...,

SRCn). Therefore, the delay of the first and second clock signals CK and CKB 1293444 having the on-voltage level and sequentially applied to the first gate line, the first gate line, ..., the n-th gate line is minimized, thereby preventing Distortion of the output signal output at each stage. Since the third and fourth clock lines CKL2 and CKBL2 do not cross other wirings (VSSL, VDDL, STL, etc.), they are connected to the respective driving stages of the n driving stages (10), ..., 5 SRCn). The third and fourth clock lines CKL2 & CKBL2 are respectively connected to the ends of the first and second clock lines CKL1 & CKBL1, and the first and second clock lines CKL1 and CKBL1 are to be connected to the n-drive phase (SRC1, ..., SRCn) each drive stage. Specifically, the first end of the input first clock signal CK to the third clock line CKL2 10 is set to be adjacent, wherein the first clock signal CK is input to the first end of the first clock line CKL1. The first end of the second clock signal CKBL1 (in which the second clock signal CKB is input) is disposed adjacent to the first end of the fourth clock line CKBL2 (where the second clock signal CKB is input). In other words, the input terminals of the first, second, third, and fourth clock lines (CKL1, CKB1, CKL2, and ckbl are set to be adjacent to the first driving phase (SRC1). The first clock line CKL1 The two ends are in the vicinity of the dummy phase (SRCn+1) and are connected to the second end of the third clock line CKL2. The third and fourth clock lines CKL2 and CKBL2 are not directly connected to the displacement temporary storage 151' and are not the parent In addition, the first and second clock signals 20 CK and CKB can travel faster through the third and fourth clock lines CKL2 and CKBL2 than the first and second clock lines CKu and CKBL1. The narrower the wiring width, the closer the displacement register 151 is to the wiring. In particular, the start signal line STL is set to be closest to the displacement register 151, 26 1293444, and the first power line VDDL is set after the # line STL is started. After the power line VDDL, the first and second clock lines CK1 & CKBL1 are sequentially set. The second power line VSSL is disposed after the first clock line CKL1. After the second power line VSSL, the second clock line CKL2 is not set. The fourth clock line CKBL2 is set after the third clock line CKL2. The wiring of 2 is arranged in the foregoing order, so that the lcd device can provide higher display quality. The wiring arrangement is adjacent to the displacement register 151, the total contact area between the wirings is large, and the contact capacitance between the wirings is large. The wiring is less affected by the capacitance between the wirings, and the displacement temporary storage 151 sets the parent to be close to the wiring. Therefore, the LCD device can provide higher quality. Referring to FIG. 11, the first and second clock signals are provided. CK and CKB are supplied to the shift register 151 to the first group G1 via the first and second clock lines CKL1 and CKBL1. When the start signal ST is applied to the first drive stage 15 SRC1 of the first group, the first - The driving phase SRC1 outputs a first output signal oim having a high voltage level of the first first clock signal $CK in response to the start signal ST. Then, the second driving phase SRC2 is responsive to the first output of the first driving phase SRC1 The signal OUT1 outputs a second output signal 〇UT2 having a high voltage level of the second second clock signal CKB. 20 When the first and second clock signals CK and CKB are passed through the third and fourth clock lines CKL2 And CKBL2, supply displacement temporary storage 151 to the second group 〇2, the first driving phase SR C1, that is, the first driving phase of the second group G 2 , in response to the (i_i)th output signal 〇υτΜ of the (1-1) driving phase SRCi_1, And output (1) output ##OUTi, which has the high voltage level of the second clock signal CKB. 27 1293444 Then the '(i+l) drive stage SRCi+1 responds to the (i)th drive stage SRCi ( The signal OUTi is rotated and the (i+i)th output signal 〇UT+i is output, which has a high voltage level of the first clock signal CK. As explained above, the first, second, and (n)th output signals (0UT1, 5QUT2 '··_, 〇UTn) are sequentially output, and the output terminals outputted at the respective driving stages have a high voltage level.

Figure 12 is a layout diagram showing the third and fourth clock line configurations of the gate drive circuit of Figure 1, and Figure 13 is a layout diagram showing the first, third, second, and third of the displacement registers. Another example of a link between four clock lines. 10. Referring to Figure 12, the start signal line STL, the first power line VDDL, the first

The first and second clock lines CKL1 and CKBL1, the second power line VSSL, and the third and fourth clock lines CKL2 and CKBL2 are sequentially disposed beside the shift register 151. The narrower the width of each wiring, the closer the displacement register 151 is disposed adjacent to the wiring. In other words, the wiring width away from the displacement register 151 is not less than the wiring width of the proximity register 丨51. The closer the wiring arrangement is to the displacement register, the larger the total contact area between the wirings and the greater the capacitance between the wirings that are in contact with each other. Therefore, the wiring is less affected by the capacitance between the wirings, and the wiring arrangement is closer to the displacement register 151. Specifically, the start signal line STL is set closest to the shift register 151, and the first power supply line VDDL is set second after the start signal line STL. After the first power line VDDL, the first and second clock lines CK1 and CKBL1 are set. The second clock line (3) 1^1 is disposed closer to the displacement register 151 than the first clock line CKL1. The second power line VSSL is next set after the first clock line CKL1. Therefore, the signal delay caused by the capacitance between the wiring and the connecting line [to connect the wiring to each stage (SRC1, ... 28 1293444 SRCn+1)] can be reduced. The third and fourth clock lines CKL2 and CKBL2 are not connected to the other wirings (VSSL, VDDL, STL, etc.), and are connected to the shift register 151. Since the ends of the third and fourth clock lines CKL2 and CKBL2 are respectively connected to the ends of the first and fifth clock lines CKL1 and CKBL1 to be connected to the shift register, the third and fourth clock lines CKL2 and CKBL2 is set further away from the shift register than the second power line VSSL. In other words, the third and fourth clock lines CKL2 and CKBL2 are disposed outside the second power line VSSL. As shown in Fig. 12, the third and fourth clock lines CKL2 and CKBL2 are formed in the sealing line region (SA) of the TFT substrate 300. The TFT substrate 300 is divided into a display area (DA) and a peripheral area (PA) surrounding the display (DA). A gate line (not shown), a data line (not shown), and a pixel (not shown) are formed in the display area (DA). The peripheral area (PA) is divided into a gate drive area (GA) and a seal line area (SA). The shift register 151 and each wiring system are formed in a gate driving region (GA). A sealing agent (not shown) for bonding the TFT substrate and the color filter substrate (not shown) is formed in the sealing line region (SA). The partial seal line area (SA) and the partial gate drive area (GA) overlap each other. The seal line area (SA) is divided into a first zone and a second zone. The liquid crystal layer is formed in the first region of the seal line region (SA), and the liquid crystal layer is not formed in the second region of the seal line region (SA). The gate drive region (GA) includes 20 first regions. The third and fourth clock lines CKL2 and CKBL2 and a part of the second power supply line VSSL are formed on the sealing line (SA). The second power supply line VSSL, the first and second clock lines CKL1 and CKBL1, and other portions of the start signal line STL are formed in the gate driving region (GA). 29 1293444 Part of the second power line VSSL, the first and second clock lines CKL1 and CKBL1, the first power line VDDL, and the start signal line STL contact the partial connection line. As such, during the process, when the second power line VSSL, the first and second clock lines CKL1 and CKBL, the first power line VDDL, and the start signal line 5 STL are formed on the sealing line (SA), the TFT substrate 300 is formed. In the process of combining the color transfer substrate under high temperature and high pressure, contact failure may occur. The wiring of the contact portion connecting line is formed in the gate driving region (GA), and the wiring not contacting the connecting line is formed in the sealing line region (SA). Therefore, it is possible to prevent an increase in the overall size of the LCD device. In particular, since the second power line VSSL, the third and fourth fourth clock lines CKL2, and other portions of the CKBL2 are not in contact with the connecting line, the second power line VSSL and the third and fourth clock lines CKL2 and CKBL2 may be formed. In the sealing line area (SA). Even if the third and fourth clock lines CKL2 and CKBL2 are further formed in the peripheral area (PA), the overall size of the LCD device does not increase. In addition, since the third and fourth clock lines CKL2 and CKBL2 are formed in the sealing line region (SA, no liquid crystal layer is formed in the sealing line region, there is no third and fourth clock line CKL2. And the capacitance caused by CKBL2. Therefore, the delays of the first and second clock signals CK and CKB are much lower than the delays of the first and second clock lines CKU&CKBLi. 2〇#照第13图,第时The pulse line Cm-end is connected to the third clock line CKL2-terminal, and the third clock line CKBU is connected to the fourth clock line CKBL2- terminal at one end. Thus the 'first-clock signal (3) is via the third clock line (10)] The stages of the supply of the shift register and the second clock signal ck are supplied to the stages of the shift register via the fourth clock line CKBL2. 30 1293444 As shown in the figures 12 and 13, the third And the fourth clock lines CKL2 and CKBL2 are not directly connected to the shift register 151, and no other wiring is left. Thus, the first and second clock signals CK and CKB are relatively traveled through the first and second clock lines. CKL1 and CKBL1 can travel faster through the third and fourth clocks 5 lines CKL2 and CKBL2. Several stages (SRC1,...,SRCn+Ι) are borrowed. The first and second clock lines CKL1 and CKBL1 are applied to the first and second clock signals ck and CKB, and the other phases (SRC1, . . . , SRCn+1) are passed through the third and fourth clocks. The lines CKL2 and CKBL2 are applied to the first and second clock lines 10 CKL1 and CKBL1 to operate. Therefore, the high voltage level is applied to the first gate line, the first gate line, ... and the ηth gate line. The delays of the first and second clock signals CK and CKB can be minimized, so that the distortion of the round-out signal outputted by the stages of the shift register can be prevented. 15 Figure 14 is a layout diagram showing the fourth according to the present invention. The displacement register wiring structure of the specific embodiment, and Fig. 15 is a wiring diagram showing the displacement register having the wiring structure of Fig. 14. Referring to Figs. 14 and 15, the second power supply line VSSL is connected to each stage. The first connection line VS SLc is disposed between the second power line vs SL and the displacement register 20 (not shown). The parallel second power line VSSL and the first and second clock lines CKL1 and CKBL1 are set. Between the second power line VSSL and the displacement register. The first connection line VSSLc crosses the first and The second clock line ^^" and CKBL1. The first and second clock lines CKL1 and cKBLa have a first width 31 1293444 degrees W1 (the first connecting line VSSLc does not cross) the first part thereof, and have a width The second portion W2 is smaller than the first width W1. In particular, the first clock line CCL1 has a first recess C1 corresponding to the fifth A link line 乂 "1^ of its second part. The second clock line CKLB1 has a second recess C2 corresponding to the second portion where the first connecting line VSSLc intersects. The clock line CKL1 has first and second side walls "οι and 1402 extending in the longitudinal direction, and the second clock line CKBL1 has third and fourth side walls 1403 and 1404 extending in the longitudinal direction. The second clock line CKU is second. The side wall 14〇2·1〇 faces the third side wall 1403 of the second clock line CKLB1. The first recess is formed on the first side wall 1401, and the second recess C2 is formed on the fourth side wall 14〇4. And Fig. 15 shows that the first clock signal (cKL) for each stage is provided between the first clock line CKL1 and the displacement register 151. The second stage is provided for each stage. The second pulse line CKBLc of the clock signal (CLB) is disposed between the second clock line CKBL1 and the displacement register 151. The first clock line CKLc contacts the first clock line CKL1 at the first clock line. The second clock line CKBU is in contact with the second clock line CKBL1 in the vicinity of the third side wall 1403 of the second clock line CKBL1. For example, the first and second recesses (:: 1 and (: 2 is formed in the first and 20th clock lines CKL1 and CKBL1, in the first and second clock lines CKL1 and CKBL1 The overlap of the first and second clock lines cklc and CKBLc can reduce the capacitance generated by the first line and the second line of the VSSLc of the first line and the second line of the line CK1 and CKB1. Therefore, the first and second clock lines CKL1 can be reduced. And the delay of CKBL1 applied to the first and third time slots of the shift register, 1293444, pulse number CK and CKB. Furthermore, the delay of the second power supply voltage signal vss applied to the displacement register via the first connection line VSSLc can be reduced. Since the widths of the portions of the first and second clock lines CKL1 and CKBL1 are narrow (W2), the resistance generated by the first and second clock lines CK1 and CKB1 overlapping the first connected 5-line VSSLc is increased. Since the signal delay is more affected by the capacitance than by the resistance, the delay of the signal can be reduced. In the following, the RC delay as a function of resistance and capacitance is shown in the embodiment and the comparative example. In the embodiment, the first and second Each of the first and second clock lines ckl1 & ckbL1 10 has a first width (W2) of 45 μm. In the comparative example, the first and second clock lines First and second widths of CKL1 and CKBL1 (W1, Jia) 7 〇 micron 0 <Table 1> CKLl (CKBLl) W1 W2 CR Comparative Example 70 μm 70 μm 385 pF 457 Ω Example 70 μm 45 μm 344.5 pF 489 Ω As shown in Table 1, in the comparative example, first and second The first capacitance between the clock line (CKL1, 15 CKBL1) and the first connection line VSSLc is 385 pF. In the embodiment, the second capacitance between the first and second clock lines (CKL1, CKBL1) and the second connection line VSSLc is 344.5 pF. The second capacitance of the embodiment is reduced by about 10.5% from the first capacitance of the comparative example. In the comparative example, the first 20th resistance of the first and second clock lines (CKL1, CKBL1) is 457 ohms. In an embodiment, the second resistance of the first and second clock lines (CKL1, CKBL1) is 489 ohms. The second resistance of the example was increased by about 7% compared to the first resistance of the comparative example. However, since the increase ratio of the second capacitance is greater than the increase ratio of the second resistor of 33 1293444, the RC delay is reduced. Fig. 16 is a plan view showing the wiring structure of the displacement register in accordance with the fifth embodiment of the present invention. Referring to Figures 14 and 15, the first connection line VSSLc for connecting the second power line VSSL to each stage is disposed between the second power line VSSL and the shift register (not shown). The parallel second power line VSSL and the first and second clock lines CKL1 and CKBL1 are disposed between the second power line VSSL and the shift register. The first connection line VSSLc intersects the first and second clock lines CKL1 and CKBL1. The first connecting line VSSLc has a third recess C3 corresponding to the third portion where the first timely pulse line CKL1 intersects. The first connecting line has a fourth recess C4 corresponding to the fourth portion of the second clock line CKBL1. The first connecting line VSSLc has a third width W3 (the first and the first clock lines CKL1 and CKBL1 are not intersected), and has a 15th fourth width W4 (the first and second clock lines CKL1) And CKBL1 cross) another part of it. The fourth width W4 is smaller than the third width W3. Since the first connecting line VSSLc has a narrow width and corresponds to the first and second clock lines CKL1 and CKBL1, the first and second clock lines (CKL1, CKBL1) and the first connecting line VSSLc can be lowered. Capacitance between. As a result, the delays applied to the first and second clock lines CK and CKB of the shift register via the first and second clock lines CKL1 and CKBL can be reduced. Further, the delay of the second power source voltage signal VSS applied to the shift register via the first connection line VSSLc can be reduced. According to the gate driver circuit, the dummy terminal of the dummy phase (SRCn+1) is set to the control terminal of the last drive phase (SRCn), and is also connected to the dummy control terminal of the dummy phase (SRCn+Ι). Therefore, the delay of the signal applied to the gate driver circuit can be prevented. In addition, since the structure of the transistor 5 connected to the control terminal of the dummy phase (SRCn+Ι) is changed, the output signal of the dummy phase (SRCn+Ι) can be normally output, and the LCD device can provide higher display quality. In addition, the wiring portion further includes third and fourth clock lines in addition to the first and second clock lines, and the first and second clocks CK and CKB are applied via the clock line, so that the sequence is applied to the first The delays of the first and second clock signals CK and CKB of the first, second, ..., and the last gate 10 lines having high voltage levels can be minimized, and the LCD device can provide better display quality. Having described the specific embodiments of the present invention and the advantages thereof, it is to be understood that various changes, modifications and changes may be made herein without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a liquid crystal display panel according to a first embodiment of the present invention; FIG. 2 is a block diagram showing a displacement register of a driving gate driver circuit of FIG. 1; The figure shows the driving phase of the second figure in the circuit diagram; the fourth figure shows the layout of the driving phase of the third figure in plan view; the fifth figure shows the dummy phase of the second figure in the circuit diagram; and the dummy drawing in the fifth figure in the sixth figure Stage layout; Figure 7 is a line diagram showing the output signal waveform of the dummy stage. The dummy stage 1293444 has the same circuit as the driving stage of Figure 2; Figure 8 is the line diagram showing the output signal waveform of the dummy stage of Figure 5; The driving phase and the dummy phase according to the second embodiment of the present invention are shown in a circuit diagram; 5 is a block diagram showing a displacement register for driving a gate driver circuit according to a third embodiment of the present invention; For the line graph, the wheel semaphore waveform of the gate driver circuit of Fig. 10 is shown; the third, the first and the fourth 10 of the σ circuit are shown in Fig. 12, and the gate diagram of the first diagram is shown in the layout diagram. And a fourth clock line configuration; FIG. 13 is another example of the connection between the first clock lines of the layout map display displacement; and FIG. 14 is a layout diagram showing the fourth embodiment according to the present invention. The wiring structure of the displacement register; 苐15 is a layout diagram showing the 1 memory; and the displacement of the wiring structure of the Τ4chuan diagram is shown as a layout diagram showing the fifth displacement register according to the present invention. Wiring structure. e example l〇〇"_TFT substrate 110...film transistor 120···pixel electrode 130···gate driver circuit 131...displacement register [Figure 2 main component representative symbol table] 131a.·· The south portion 131b...the descending portion 131c···uplifting driver portion 131d···the descending driver portion 131e···the current-carrying output portion 36 1293444 132..the wiring portion 133a...the rising portion 133b...the falling portion 133c...rise driver portion 133d...drop driver portion 133e...carrier output portion 140...data driver circuit 150..gate driver circuit 151..displacement register 152.. wiring portion 200.. . LCD display panel DA... display area PA... peripheral area SA... sealing line area GA... gate drive area DL... data line GL... brake line CT.. Control terminal SRC... drive phase CR... current-carrying terminal IN... input terminal ST... start signal OUT... output terminal STL... start signal line VDDL... first power supply line CKL ...first clock line CKBL...second clock line VSSL...second power line VDD...first power supply voltage signal VSS...second power supply voltage signal CK...first time Pulse signal CKB... Second clock signal CKT...clock terminal VDDT...first power line terminal VSST...second power line terminal N...node NT...NMOS transistor G··· group

37

Claims (1)

1293444 Pickup, Patent Application Range: Application No. 92107914 Application Patent Revision No. 95. 11.01. 1· A driver circuit for driving an active matrix drive display device, the driver circuit comprising: 5 a plurality of drive stages, each drive stage including one The output terminal and the control terminal of the current driving stage are coupled to the control terminals of the state before the series connection, and each driving stage outputs a driving signal for controlling a switching device via the output terminal, the driving device And being disposed on the active matrix driving display device; and a dummy phase including a dummy output terminal and a dummy control terminal, the dummy output terminal being coupled to a control terminal of one of the plurality of driving stages and the last driving stage,俾 outputting a dummy output signal for turning on or off the last driving phase, and the dummy control terminal is coupled to the dummy output terminal 15 to be turned on or off by the dummy output signal. 2. The driver circuit of claim 1, wherein the dummy phase comprises: a rising portion that provides a turn-on voltage signal to the dummy output terminal, the signal having a voltage level high enough to conduct the switching device a lowering portion for providing the dummy output terminal with a turn-off voltage signal having a voltage level low enough to turn off the switching device; and a driver portion for driving the elevated portion and Next to the falling portion, the driver portion is driven by a turn-on voltage signal to turn on the high portion of the rise 38 1293444, turn off the drop portion, and maintain the voltage level of the turn-on voltage signal for a first predetermined time. 3. The driver circuit of claim 2, wherein the first transistor having a first transistor coupled to one of the dummy control terminals is less than 5 second transistor coupled to a control terminal of the last drive stage The second transistor size is such that the voltage level of the turn-on voltage signal outputted by the dummy phase is substantially equal to the maximum voltage level of the drive signal. 4. The driver circuit of claim 2, wherein the turn-on voltage signal maintains a voltage level substantially equal to a maximum voltage of the drive signal and the first predetermined time is experienced. 5. The driver circuit of claim 2, wherein the driver portion comprises: a raised driver portion for driving the elevated portion, the elevated driver portion coupled to one of the elevated portions of the first input The node, the return 15 should turn on the rising portion by an input signal outputted from one of the input terminals of the dummy phase, and after the second predetermined time, turn off the rising portion in response to the turn-on voltage signal outputted by the dummy control terminal. And a falling driver portion for driving the falling portion, the falling driver portion being coupled to the second input node of the falling portion, the back 20 being turned on by an input signal outputted by one of the input terminals of the dummy phase The falling portion, and after the third predetermined time, turns on the falling portion in response to the turn-off voltage signal outputted by the dummy control terminal. 6. The driver circuit of claim 5, wherein the boost driver portion comprises: 39 1293444 a capacitor coupled between the first input node and the dummy output terminal of the elevated portion, a first transistor The first drain is coupled to the high power line, a first gate is coupled to the input terminal, and a first source handle 5 is connected to the first input node of the elevated portion; The transistor includes a second drain and a second gate commonly coupled to the high power line; a third transistor including a third transistor coupled to the high power line and a third gate Extremely coupled to the second source 10 of the second transistor, and a third source is extremely coupled to the second input node of the falling portion; a fourth transistor including a fourth drain coupled thereto An input terminal, a fourth gate coupled to the second input node of the falling portion, and a fourth source shank coupled to a low power line; 15 a fifth transistor including a fifth drain coupled thereto Lower input portion of the second input node a fifth gate is coupled to the input terminal, and a fifth source is coupled to a low power line; a sixth transistor includes a sixth input terminal coupled to the first input node of the elevated portion, A sixth gate is coupled to the 20th input node of the falling portion, and a sixth source is coupled to a low power line. 7. The driver circuit of claim 6, wherein the boost driver portion further comprises a seventh transistor comprising a seventh drain coupled to the input terminal, a first gate coupled to the dummy control A terminal, and a seventh source are coupled to the low power line. 40 1293444. The driver circuit of claim 6, wherein the drop driver portion comprises: an eighth transistor comprising an eighth input terminal coupled to the falling portion of the second input node, an eighth gate a fifth input node coupled to the elevated portion, and an eighth source surface coupled to the low power line; a ninth transistor including a ninth drain coupled to the second transistor a second source, a ninth gate coupled to the first input node of the elevated portion, and a ninth source coupled to the low power line; a tenth transistor comprising a tenth drain coupled to The lower portion is divided into a first input node, a tenth gate is coupled to the dummy control terminal, and a tenth source is coupled to the low power line. 9. The driver circuit of claim 8, wherein the driving stages each comprise a same circuit as the driving circuit of the dummy stage, and the size ratio of the transistor 15 of the transistor corresponding to each driving stage of the tenth transistor of the dummy stage The crystal size of the tenth transistor is about 10 times larger. 10. A liquid crystal display device comprising: a display portion comprising: i) a first substrate having a plurality of gate lines coupled to one of switching devices formed in a pixel, the pixels being arranged in a matrix shape, ii) a second a substrate facing the first substrate, and iii) 20 a liquid crystal layer interposed between the first substrate and the second substrate; a gate driver for driving the switching device, the gate driver Including i) a plurality of driving stages, each of the driving stages includes an output terminal and a control terminal, and the output terminals of the current driving stage are coupled to the control terminals of each state before the cascade connection, and each driving stage passes the 41 1293444 output terminal. Outputting a driving signal to each of the gate lines for controlling the switching device, and ii) a dummy phase including a dummy output terminal and a dummy control terminal 'the dummy output terminal is coupled to one of the plurality of driving stages a control terminal of the stage, 俾 outputting a dummy output signal 5 for turning on or off the last driving phase, and the dummy control terminal is coupled to the desired The dummy dummy output signal is turned on or off of the output terminal. 11. The liquid crystal display device of claim 10, wherein the dummy phase comprises: a rising portion that provides a turn-on voltage signal to the dummy output terminal, the signal having a voltage level high enough to turn on the a switching device; a falling portion for providing the dummy output terminal with a turn-off voltage signal having a voltage level low enough to turn off the switching device; and a driver portion for driving the rising portion And the falling portion of the driver portion is driven by the turn-on voltage signal, turning on the rising portion, turning off the falling portion, and maintaining the voltage level of the turn-on voltage signal for a first predetermined time. 12. The liquid crystal display device of claim 1, wherein the gate driver further comprises a wiring portion through which a plurality of signals are supplied to the driving stages and the dummy stages. The liquid crystal display device of claim 12, wherein the driving stages are divided into a first group and a second group, and the wiring portion comprises: 42 1293444 a first clock line, via the first a clock line, the first clock signal is supplied to the odd-numbered driving phase of the first group; and a second clock line is supplied to the dummy phase and the first clock signal via the second clock line Two groups of odd-numbered driving stages; 5 a third clock line through which a second clock signal is supplied to the even-numbered driving phase of the first group, the second clock signal being relative to the first The clock signal has a phase difference of 180 degrees; a fourth clock line through which the second clock signal is supplied to the even numbered driving phase of the second group. A liquid crystal display device, comprising: a display portion, comprising: i) a first substrate having a pixel, a gate line and a data line, the pixel having a switching device coupled to the gate line and the data line, Ii) a second substrate facing the first substrate, and iii) a liquid crystal layer interposed between the first substrate and the second substrate; 15 a data driver for providing an image data to the data line The data driver is formed adjacent to the display portion and coupled to the data line; and a gate driver for driving the switching device, the gate driver including a displacement register and a wiring portion, the gate driver The shift register 20 has a plurality of stages connected in series with each other, the shift register is divided into a first group and a second group, and is formed adjacent to the display portion, and an external signal is applied to each stage via the wiring portion. And the driving phase is respectively outputting a driving signal via an output terminal for controlling the switching device, wherein the wiring portion comprises: 43 1293444 Japanese repair (more) positive replacement page 10 15 20 - the first - clock line 'via the first - clock line, - the first hour number is supplied to the odd-numbered phase of the first group; " - the second clock line, via the second clock line, - has The second clock signal of the phase-to-clock signal (10) degrees is supplied to the first group; the odd-numbered driving phase; the ° ^ - the third clock line, via which the first-clock signal is supplied to the second The odd-numbered driving phase; and the fourth clock line, via which the second clock signal is supplied to the even-numbered driving phase of the second group. The liquid crystal display device of claim 14, wherein the first, second, third, and fourth clock lines respectively include first, second, third, and fourth input terminals, and the first - The second, third and fourth wheel-in terminal arrangements are disposed adjacent to each other in a first zone, and the first stage is disposed in the first zone. 16. The liquid crystal display device of claim 15, wherein the first clock line is coupled to the third clock line in a second area, and the green shifting line is disposed in the second area, and The second clock line: the junction to the fourth clock in the second zone. 17. Please, please refer to the liquid crystal display device of item 14, wherein - the sealing element for the second substrate is formed on the display circumference = _, and the third and fine pulse line system is disposed on 18. The liquid crystal display part of claim 14 of the patent scope includes a first device in which the wiring power line, the second power line and the one open 44 1293444 an initial signal line, a first power signal is applied to the first power line, and a second power signal is applied to the second power line, and a start signal is applied to the start signal line, thereby supplying a plurality of stages a first phase; and the start signal line, the second power line, the first clock line, the 5th clock line, the first power line, the third clock line, and the fourth clock line are displaced by The order in which the scratchpads begin is arranged. 19. The liquid crystal display device of claim 18, wherein the wiring portion further comprises a connecting line for connecting the first power line to each stage, the first clock line having a first width that is not intersected by the connecting line a first portion thereof, and a second portion having a second width that does not intersect the connecting line, the second clock line having a third width that is not intersected by the third portion of the connecting line, the second portion The clock line has a fourth portion having a fourth width that is not intersected by the connecting line, the second width being less than the first width, and the fourth width being less than the fifth width. The liquid crystal display device of claim 18, wherein the wiring portion further comprises a connecting line for connecting the first power line to each stage, the first power line having a first width in the first and the The first portion of the second clock line that does not intersect, and the second portion having a second width that does not intersect the first and second clock lines, the second width being less than 20 of the first width. 45 1293444 柒, designated representative map: (1) The representative representative of the case is: (1). (2) The representative symbol of the representative figure is a simple description: 100.. . TFT substrate 110... Thin film transistor 120...Pixel electrode 130.. Gate driver circuit 140...Data driver circuit 200.. LCD display panel捌If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: