1292936 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種軟性晶片載體（flexible chip carrier)，特別係有關於一種内引腳接合捲帶及使用該捲帶 之捲帶承載封裝構造。 【先前技術】 在半導體封裝領域中，晶片載體之種類主要區分為硬 性與軟性，硬性晶片載體計有硬性印刷電路板、導線架、 陶瓷基板等，無法作捲帶式傳輸；軟性晶片載體則有内引 腳接合捲帶、金屬薄膜、覆晶薄膜等，能作捲帶式傳輸， 達到連續式封裝製程。一般而言，内引腳接合捲帶於每一 封裝單元係具有一元件孔（deviee h〇le)，孔内延伸有懸空 之内引腳，以供内引腳接合。 内引腳接合（Inner Lead Bonding，ILB)是一種既有的 晶片接合技術，當一内引腳接合捲帶移動至定點之後，以 咼熱壓合頭壓迫該内引腳接合捲帶之懸空引腳，使其 接〇至一晶片之複數個凸塊，通常所製成的半導體封裝產 稱之為捲帶承載封裝構造（Tape Carrier Paekage，TCP)。 隨著高密度發展，内引腳接合之對位日顯重要。以往的對 位方式是在内引腳接合捲帶額外增設有細長條狀之對位 弓I腳’其係為懸空狀並如同一般引腳是以蝕刻形成，容易 因飾刻不良與位移造成對位不正確。 本國專利證號1245396「引腳加強之捲帶承載封裝基 板J揭示一種内引腳接合捲帶，其係將部分之引腳設計成 1292936 迴圈引腳，用以加強引腳強度，然仍無法解決内引腳接合 時對位不正確之問題。 【發明内容】 本發明之主要目的係在於提供一種内引腳接合捲帶 以及使用該捲帶之捲帶承載封裝構造，在一具元件孔之可 撓性介電層上形成有複數個補強引腳（sfiffening lead)，以 增強該内引腳接合捲帶之扭曲變形抵抗性，又每一補強引 腳係具有一概呈十字或是T字形之對位標記，該些對位標 記係位於該兀件孔之外而貼附於該可撓性介電層，以協助 内引腳接合時對位且容易製作成形。 本發明之次一目的係在於提供一種内引腳接合捲帶 以及使用該捲帶之捲帶承載封裝構造，其中該可撓性介電 層之元件孔之四邊角隅係為弧角，而每一對位標記係具有 複數個對應於該些角隅之弧形f曲條，以增強抗扭曲抵抗 性。 本發明之再一目的係在於提供一種内引腳接合捲帶 以及使用該捲帶之捲帶承载封裝構造，其中在該可撓性介 電層之一防焊層係具有一開孔，其尺寸係略大於該元件 孔，而使該些對位標記係位於該開孔之内而為顯露狀，以 利電鍍形成一亮面層，以利辨識。 本發明之再一目的係在於提供一種使用該内引腳接 合捲帶之捲帶承載封裝構造，其中該㈣體更包覆該些補 強引腳之對位標記，可以增進該些引腳在該晶片角隅處之 抗斷裂特性。 •1292936 依據本發明，一種内引腳接合捲帶係主要包含一具有 兀件孔之可撓性介電層、複數個引腳以及複數個補強引 腳。每一引腳係具有一懸空於該元件孔内之接合部，以接 合至一晶片。每一補強引腳係具有一概呈十字或是τ字形 之對位10己，該些對位標記係位於該元件孔之外而貼附於 該可撓性介電層，具有協助内引腳接合對位、容易製作成 形以及增進該捲帶之抗扭曲變形能力之功效。 【實施方式】 鲁 &據本發明之—具體實施例，帛1圖m繪示者係為- 種内引腳接合捲帶之俯視示意圖，第2圖所繪示者係為該 内引腳接合捲帶於補強引腳之局部放大圖，第3圖所繪示 者係為該内引腳接合捲帶沿其中一補強引腳之剖切示意 圖。 清參閱第1、2及3圖，該内引腳接合捲帶1〇〇係主 要包έ 一具有元件孔111 (device hole)之可撓性介電層 % 11 0、複數個引腳120以及複數個補強引腳1 30。該可撓性 介電層11 0係為一種電絕緣性薄膜，例如PI(聚醯亞胺）， 其厚度約在8〜40微米並具有任意彎曲之可撓性，以利捲 帶式輸送。並且，該可撓性介電層11〇之該元件孔U1其 尺寸大致對應於一凸塊化晶片21〇(如第1圖所示），以供 内引腳120接合（inner Lead Bonding，ILB)。在本實施例 中，該元件孔111之形狀係概呈矩形。 該些引腳120與該些補強引腳130係形成於該可撓性 介電層110上。較佳地，該些補強引腳13〇與該些引腳12〇 7 1292936 係可為同層結構’可藉由同一光罩圖案化蝕刻同一銅箔以 成形，以使該些補強引腳1 3 0與該些引腳1 2 0之間隔位置 為固定。每一引腳1 2 0係具有一往内延伸之接合部i 2 1， 其係懸空於該元件孔111内，以接合至該晶片2 1 〇之複數 個凸塊211(如第1與4圖所示），以電性傳輸該晶片21〇 之輸入端與輸出端。 如第2及3圖所示，每一補強引腳130係具有一概呈 十字或是T字形之對位標記131，該些對位標記13ι係位 於該元件孔111之外而貼附於該可撓性介電層丨丨〇，可在 内引腳120接合時被一攝影裝置（圖未繪出）捕捉其座標位 置’故上述具有對位標記丨3 1之補強引腳丨3 〇係具有協助 内引腳120接合對位、容易製作成形以及增進該捲帶之抗 扭曲變形能力之功效。在本實施例中，該些對位標記i 3 i 係為近似十字形，其一端係微突入該元件孔丨丨丨。通常該 些對位標記1 3 1可位於該元件孔丨丨丨之角隅處，以避開該 些引腳120之設計空間。較佳地，該元件孔U1之四邊角 隅係為弧角，而每一對位標記131係具有複數個對應於該 些角隅之弧形彎曲條132(如第2圖所示），以避免該元件 孔111之角隅處成為應力集中區而易於翹曲。 再如第2及3圖所示，該内引腳接合捲帶ι〇〇係另包 合有一防焊層140，如液態感光性銲罩層（Hquid photomagable solder mask，或稱Lpi)或感光性覆蓋層 (photoimagable coveiMayer，或稱 PIC)、亦可為一般非感 1電材質之非導電油墨或覆蓋層（c〇ver layer)，以局 1292936 部覆蓋該些引腳120與該些補強引腳13〇。該防焊層14〇 係具有一開孔14 1，其尺寸係略大於該元件孔i丨丨，而使 該些對位標記1 3 1係位於該開孔丨41之内而為顯露狀，而 該些補強引腳130之其餘部位係被該防焊層所覆蓋， 以增強該些對位標記131的固著性。此外，該内引腳接合 捲帶100係可另包含有複數個虛設引腳l5〇(dummy lead)。該些虛設引腳150係位於該元件孔lu之其中一較 短邊，以增進該内引腳接合捲帶1〇〇之結構補強效果。 再如第3圖所示，該些對位標記丨3 i在顯露於該防焊 層140之外之表面係形成有一亮面層133，例如電鍍形成 且具有光亮金屬表面之鎳-金層、錫層、銀層等等，以利被 攝影裝置辨識。 如第1及4圖所示，本發明更進一步揭示使用上述内 引腳接合捲帶1〇〇之捲帶承載封裝構造（Tape Package，TCP),其利用該内引腳接合捲帶1〇〇作為晶片載 體，更包含一晶片210與一封膠體22〇。該晶片21〇係具 有複數個凸塊211，例如金凸塊或其它導電凸塊，作為該 曰曰片2 1 0對外輸出/輸入端。利用該些補強引腳丨3 〇，可防 止孩内引腳接合捲帶1 〇〇之該元件孔i丨丨於角隅或其它應 力集中處發生杻曲變形。並且，利用該些補強引腳13〇之 4些對位標記13 1，在内引腳i 2〇接合時，該晶片2丨〇能 對準於該可撓性介電層丨丨〇之該元件孔丨丨丨，且該些引腳 120之該些接合部121係能準確接合至該些凸塊。而該封 膠體220係可使用塗膠方式形成於該元件孔1丨丨内再固化 9 1292936 成形，以密封該些引腳120之該些接合部i 2丨與該些凸塊 2Π。較佳地，該封膠體220更包覆該些補強引腳13〇之 對位標記131，可以增進該些引腳12〇在該晶片21〇角隅 處之抗斷裂特性。 此外’本發明之内引腳接合捲帶除了運用在TCP封裝 領域之外，亦可等效性運用在薄膜覆晶（c〇F，chip 〇n_fUm) 封裝。如第5圖所示，一種内引腳接合捲帶3〇〇係主要包 含一可撓性介電層3 10、複數個引腳32〇以及複數個補強 引腳330。可在該可撓性介電層31〇之晶片接合處定義一 覆曰b接合區311，而不需要元件孔。該些引腳32〇係形成 於該可撓性介電層310上，每一引腳32〇係具有一延伸至 該覆晶接合區311内之接合部321，以接合至一晶片之凸 塊。該些補強引腳330亦係形成於該可撓性介電層31〇 上，每一補強引腳330係具有一概呈十字或是τ字形之對 位標記331，該些對位標記331係位於該覆晶接合區3ιι 之外並貼附於該可撓性介電層31〇,具有協助内引腳接合 對位、谷易製作成形以及增進該捲帶之抗扭曲變形能力之 功效。在本實施例中，該覆晶接合區3丨丨係概呈矩形，其 尺寸大小對應於一晶片主動面，該些對位標記33丨係位於 4覆0B接合區311之角隅處。此外，該内引腳接合捲帶3⑽ 可另包含有一防焊層340，以局部覆蓋該些引腳32〇與該 些補強引腳330。該防焊層34〇係具有一開孔341，其尺 寸係大於該覆晶接合區311，而使該些對位標記33丨係位 於該開孔341之内而為顯露狀，以利對位辨識。 10 * a^2936 以上所述，僅是太I ηα 發明作任何形式上的限制：較佳實施例而已，並非對本 露如 雖然本發明已以較佳實施例揭 如上，然而並非用^ 者， 限疋本發明，任何熟悉本項技術 不脫離本毛明之申請專利範圍内，所作的任何簡單 r κ等效陡I化與修飾，皆涵蓋於本發明的技術範圍内。 【圖式簡單說明】 第1圖：依據本發明之_目Μ ^ 具體實施例，一種内引腳接合捲BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a flexible chip carrier, and more particularly to an inner lead-bonded tape and a tape-receiving package structure using the same. . [Prior Art] In the field of semiconductor packaging, the types of wafer carriers are mainly classified into hard and soft. Hard wafer carriers include rigid printed circuit boards, lead frames, ceramic substrates, etc., which cannot be used for tape and roll transfer; soft wafer carriers have The inner lead-bonded tape, metal film, flip chip, etc. can be used for tape and reel transfer to achieve a continuous packaging process. In general, the inner pin bond reel has a component hole in each package unit, and a floating inner pin extends in the hole for the inner pin to be engaged. Inner Lead Bonding (ILB) is an existing wafer bonding technique. When an inner pin engages the tape and moves to a fixed point, the inner pin is pressed by the heat sealing head to press the tape. The foot is connected to a plurality of bumps of a wafer, and the semiconductor package usually produced is called a Tape Carrier Paekage (TCP). With the development of high density, the alignment of the internal pin bonding is becoming increasingly important. In the past, the alignment method was that the inner pin-bonded tape was additionally provided with a slender strip-shaped alignment bow, which was suspended and shaped like a general pin, which was easily caused by poor decoration and displacement. The bit is incorrect. National Patent No. 1245396 "Pin-Enhanced Tape-Receiving Package Substrate J discloses an internal pin-bonded tape that is designed to have a part of the pin as a 1292936 loop pin to enhance the pin strength, but still not The invention solves the problem of incorrect alignment when the inner pins are engaged. SUMMARY OF THE INVENTION The main object of the present invention is to provide an inner lead-bonding tape and a tape-receiving package structure using the tape, in a component hole A plurality of sfiffening leads are formed on the flexible dielectric layer to enhance the distortion resistance of the inner lead-bonded tape, and each reinforcing pin has a cross or a T-shape. The alignment marks are attached to the flexible dielectric layer outside the element holes to assist in the alignment of the inner pins when they are joined and are easily formed. The second object of the present invention is The invention provides an inner lead-bonding tape and a tape-receiving package structure using the tape, wherein the four corners of the component holes of the flexible dielectric layer are arc angles, and each of the alignment marks has a plurality of Corresponding The curved corners of the corners are curved to enhance the resistance to twisting. A further object of the present invention is to provide an inner lead-bonding tape and a tape-receiving package structure using the tape, wherein A solder resist layer of the flexible dielectric layer has an opening, the size of which is slightly larger than the hole of the component, and the alignment marks are located inside the opening to be exposed, so as to form a bright plate. A further object of the present invention is to provide a tape carrier package structure using the inner lead to bond a tape, wherein the (four) body further covers the alignment marks of the reinforcing pins, Enhancing the fracture resistance of the pins at the corners of the wafer. 1292936 According to the present invention, an inner pin bond tape system mainly comprises a flexible dielectric layer having a mesh hole, a plurality of pins, and a plurality of reinforcing pins, each of which has a joint suspended in the hole of the element for bonding to a wafer. Each reinforcing pin has a cross or a τ-shaped alignment 10 Some of the alignment marks are located in the component hole Externally attached to the flexible dielectric layer, it has the function of assisting the inner pin to be engaged, facilitating the forming and improving the twisting resistance of the tape. [Embodiment] Lu & In a specific embodiment, FIG. 1 is a top view of the inner lead-bonded tape, and FIG. 2 is a partial enlarged view of the inner lead-bonded tape on the reinforcing pin. Figure 3 is a cross-sectional view of the inner pin-bonded tape along one of the reinforcing pins. Refer to Figures 1, 2 and 3 for the inner pin-bonded tape 1 package. A flexible dielectric layer % 11 0 having a device hole 111, a plurality of pins 120, and a plurality of reinforcing pins 1 30. The flexible dielectric layer 110 is an electrical insulating property. Films, such as PI (polyimine), have a thickness of about 8 to 40 microns and have any flexural flexibility for tape and reel transport. Moreover, the component hole U1 of the flexible dielectric layer 11 is substantially corresponding in size to a bumped wafer 21 (as shown in FIG. 1) for inner lead bonding (ILB). ). In this embodiment, the shape of the element hole 111 is substantially rectangular. The pins 120 and the reinforcing pins 130 are formed on the flexible dielectric layer 110. Preferably, the reinforcing pins 13A and the pins 12〇7 1292936 can be in the same layer structure. The same copper foil can be patterned by etching the same mask to form the reinforcing pins 1 . The position of the 0 0 and the pins 1 2 0 is fixed. Each of the pins 120 has an inwardly extending joint i 2 1 suspended in the element hole 111 to be bonded to the plurality of bumps 211 of the wafer 2 1 (eg, 1 and 4) The figure shows that the input and output terminals of the wafer 21 are electrically transferred. As shown in FIGS. 2 and 3, each of the reinforcing pins 130 has a cross or T-shaped alignment mark 131, and the alignment marks 13o are located outside the element hole 111 and attached thereto. The flexible dielectric layer 捕捉 can be captured by a photographic device (not shown) when the inner lead 120 is joined. Therefore, the reinforced pin 丨3 having the alignment mark 丨3 1 has It assists the inner pin 120 in engaging the alignment, is easy to shape, and enhances the anti-twist ability of the tape. In this embodiment, the alignment marks i 3 i are approximately cross-shaped, and one end thereof is slightly protruded into the element aperture. Usually, the alignment marks 1 3 1 may be located at the corners of the element apertures to avoid the design space of the pins 120. Preferably, the four corners of the element hole U1 are arc angles, and each of the alignment marks 131 has a plurality of curved curved strips 132 corresponding to the corners (as shown in FIG. 2), It is avoided that the corners of the element hole 111 become stress concentration regions and are easily warped. As shown in FIGS. 2 and 3, the inner lead-bonding tape 〇〇 is additionally provided with a solder resist layer 140, such as a liquid photo-sensitive solder mask (Lpi) or photosensitive. A cover layer (photoimagable coveiMayer, or PIC), or a non-conductive ink or a cover layer (c〇ver layer) of a general non-inductive material, covering the pins 120 and the reinforcing pins with a portion of 1292936 13〇. The solder resist layer 14 has an opening 14 1 which is slightly larger than the hole 丨丨 of the component, so that the alignment marks 133 are located inside the opening 丨 41 and are exposed. The remaining portions of the reinforcing pins 130 are covered by the solder resist layer to enhance the adhesion of the alignment marks 131. In addition, the inner pin bond reel 100 can additionally include a plurality of dummy leads. The dummy pins 150 are located on one of the shorter sides of the component hole lu to enhance the structural reinforcement effect of the inner pin bonding tape 1 . As further shown in FIG. 3, the alignment marks 丨3 i are formed on the surface exposed outside the solder resist layer 140 to form a bright surface layer 133, such as a nickel-gold layer formed by electroplating and having a bright metal surface. Tin layer, silver layer, etc., to facilitate identification by the photographic device. As shown in FIGS. 1 and 4, the present invention further discloses a tape carrier package structure (Tape Package, TCP) using the above-described inner pin bond tape 1 ,, which utilizes the inner pin to bond the tape 1 〇〇 As the wafer carrier, a wafer 210 and a gel 22 〇 are further included. The wafer 21 has a plurality of bumps 211, such as gold bumps or other conductive bumps, as the outer output/input of the die 210. By using these reinforcing pins 丨3 〇, it is possible to prevent the component hole of the child's pin-bonding tape 1 杻 from being distorted at a corner or other stress concentration. Moreover, by using the four alignment marks 13 1 of the reinforcing pins 13 〇, the wafer 2 丨〇 can be aligned with the flexible dielectric layer when the inner pins i 2 〇 are bonded. The component holes are formed, and the joint portions 121 of the pins 120 are accurately bonded to the bumps. The encapsulant 220 can be formed by being glued in the hole 1 of the element and then formed by curing 12 1292936 to seal the joints i 2 该 of the pins 120 and the bumps 2 . Preferably, the encapsulant 220 further covers the alignment marks 131 of the reinforcing pins 13 , to improve the fracture resistance of the pins 12 at the corners of the wafer 21 . Further, the pin-bonded tape of the present invention can be equally applied to a film flip chip (c〇F, chip 〇n_fUm) package in addition to the use of the TCP package. As shown in FIG. 5, an inner pin bond tape 3 is mainly composed of a flexible dielectric layer 3 10, a plurality of pins 32 〇, and a plurality of reinforcing pins 330. A cover b-bonding region 311 can be defined at the wafer junction of the flexible dielectric layer 31 without the need for component holes. The leads 32 are formed on the flexible dielectric layer 310, and each of the leads 32 has a bonding portion 321 extending into the flip chip bonding region 311 to be bonded to a bump of a wafer. . The reinforcing pins 330 are also formed on the flexible dielectric layer 31, and each of the reinforcing pins 330 has an alignment mark 331 which is substantially cross or τ-shaped, and the alignment marks 331 are located. The flip-chip bonding region 3 ιι is attached to the flexible dielectric layer 31 〇, and has the function of assisting the inner pin to be aligned, the valley to be easily formed, and the tape to be resistant to distortion. In this embodiment, the flip-chip bonding region 3 is substantially rectangular in shape and corresponds to a wafer active surface, and the alignment marks 33 are located at corners of the 4B bonding region 311. In addition, the inner lead bond tape 3 (10) may further include a solder resist layer 340 to partially cover the pins 32 and the reinforcing pins 330. The solder resist layer 34 has an opening 341 which is larger than the flip-chip bonding region 311, and the alignment marks 33 are located inside the opening 341 to be exposed to facilitate alignment. Identification. 10 * a^2936 As described above, the invention is only limited to any form of the invention: the preferred embodiment is not intended to be the same as the preferred embodiment of the present invention. It is to be understood that any simple r κ equivalent steepness and modification made by the present invention within the scope of the patent application of the present invention is within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of an embodiment of the present invention.
帶之俯視示意圖。 第2圖·依據本發明之_具體實施例，該内引腳接合捲帶 於補強引腳之局部俯視示意圖。 第3圖·依據本發明之一具體實施例，沿第2圖3_3線之 剖切不意圖。 第4圖·依據本發明之一具體實施例，一種使用該内引腳 接合捲帶之捲帶承載封裝構造之截面示意圖。 第5圖：依據本發明之另一具體實施例，另一種内引腳接 合捲帶之俯視示意圖。 【主要元件符號說明】 100内引腳接合捲帶 11 0可撓性介電層 111元件孔 120引腳 121接合部 130補強引腳 131對位標記 U2弧形彎曲條 133亮面層 140防銲層 141開孔 1 5 0虛設引腳 ,1292936 210晶片 211 ’ 220封膠體 300内引腳接合捲帶 310可撓性介電層 311 320引腳 321 330補強引腳 331 340防銲層 341 凸塊 覆晶接合區 接合部 對位標記 開孔A schematic view of the belt. Figure 2 is a partial top plan view of the reinforcing pin in accordance with a particular embodiment of the present invention. Fig. 3 is a cross-sectional view taken along line 3-3 of Fig. 2, in accordance with an embodiment of the present invention. Fig. 4 is a cross-sectional view showing a tape-receiving package structure in which the inner lead is used to bond a tape according to an embodiment of the present invention. Figure 5 is a top plan view of another inner pin-engaging tape in accordance with another embodiment of the present invention. [Main component symbol description] 100 inner pin bond tape 11 0 flexible dielectric layer 111 component hole 120 pin 121 joint portion 130 reinforcing pin 131 alignment mark U2 curved bent bar 133 bright surface layer 140 solderproof Layer 141 opening 1 50 dummy pin, 1292936 210 wafer 211 '220 sealing body 300 pin bonding tape 310 flexible dielectric layer 311 320 pin 321 330 reinforcing pin 331 340 solder mask 341 bump Flip joint junction joint alignment mark opening
1212