TWI290766B - High-voltage lateral double-diffused MOS having a cutoff resistance - Google Patents

Abstract

The present invention provides a high-voltage lateral double-diffused MOS structure having a cutoff resistance. This MOS structure uses a common gate with two source areas to form a semiconductor device structure having a high-voltage lateral double-diffused MOS structure and a resistor structure. The resistor part can lower the initial current of the device and restrict the inner voltage so as to avoid damaging the inner device when the device is operated at high voltage. Using the common gate to add the resistor can avoid oversized circuit dimensions in the device and simplify the manufacturing process.

Description

1290766 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a high voltage laterally diffused metal oxide semiconductor, and more particularly to a high voltage laterally diffused metal oxide semiconductor having a turn-off resistance.疋[Prior Art] • One of the important trends in the development of AC power and (4) loops in single-chip development, with the aim of environmental protection, saving a lot of energy loss' and integrating external components On a single wafer. However, in order to achieve this goal, it is necessary to withstand components of hundreds of volts or more. Lateral double-dif & sed metal oxide semiconduct 〇r, referred to as high breakdown (VDtage) and better high frequency performance, and its structure is easy to integrate into complementary MOS (CM) In the process of 〇s) or double-carrier complementary MOS (5) CMOS), it is possible to achieve acceleration control, transfer or power _ cake in a single wafer, so it is widely used for power generation. In addition, resistors are often used in integrated circuits to limit the current between the contacts of the semiconductor device k at the applied voltage. LDMOS basically has three contacts, which are closed-pole (_), source (S-picture) and drain (d_). The middle pole is difficult to make current from the drain to the source. LDM0S Low on-resistance must be provided at high switching speeds. Low on-resistance can help reduce power consumption and reduce component size. = The development of a technique to reduce the surface electric field (resurf) is combined with the method of reducing the thickness of a half-day cat day or N well to achieve low conduction at high voltage. 5 1290766 [Embodiment] In order to make the private hair _ purpose, structure, characteristics, and Wei Weijin step, the sensation example is explained in detail below. The above description of the present invention is intended to demonstrate and explain the principles of the present invention, and to provide a more advanced explanation of the scope of the present invention. For details, please refer to the "1st map", "1st map" and "1st map" for the first example of this month. As shown in FIG. 1A, the structure of the first embodiment includes a p-type substrate ιο, a 汲-type drain region U, an N-type drift region i2, an n-type source region 13, and an N-type resistor. The source region 14, the drain electrode 21, the source electrode 22, the interlayer electrode 23, and the resistance source electrode 24. The drain region n is formed on the substrate 1 by means of implanted ions (the W (four) 12 and the implanted N-type ions are formed on the substrate and connected to the non-polar region 11'), and the drift region 12 has the extension portion 12a. The pole region 13 is formed on the substrate ω by the N-faced surface and is separated from the drift region ^ (refer to "1B"). The gate _23 is located in the channel 15 (please refer to "1B" Fig.) and the extension portion 12a (please refer to "the ic diagram") above, and the first insulating layer 3G is spaced apart from the board 1G (not shown in "1A", please refer to "Different 1B diagram" or " 1C"). The electrode 21 is not connected to the pole region 11. The source electrode 22 is connected to the source region 13. The resistor source region 14 is formed in the extension portion by means of implanting ions. The resistor source electrode 24 is connected to the resistor source. Zone 14. When the P-type conductive state is changed to the N-type in the first embodiment, and the _conducting state is changed to the p-type, the desired structure can also be formed. The inter-electrode 23, the source region 13 and the k-plane n are mutually In conjunction with the function of providing LDMOS, the gate electrode 23 and the resistor source region 14 cooperate with the wire region 1290766 to provide a resistor function. Then, the structure is __23, and the "picture" is "the first picture: the middle part of the block." The P plate 1G has the same p-type insect layer heart p-type substrate ίο The resistivity of the layer 10a is 5 〇 to ohm-cm (〇hm-cm). In the part of the worm layer, a high concentration p-type P well (10) is mixed in the worm layer. In the worm layer 10a and p well A part of the area is mixed with a high concentration of N-type ions to form a n-electrode region of the drain region 13. Around the drain region u (4) a low concentration of N-type ions forms a drift 2, and the drift region 12 extends as long as : Micro is not (μπ〇. Therefore, the source region of the N-type ticket shift region 12 is shaped into a P-type channel 15 1 The transfer region 12 is formed with the first insulating layer 30, and the first insulating layer above the pass region A gate electrode 23 is formed on 30. Then, a second insulating layer 31' is formed, and a first source plate layer melon of the source electrode 22 and a second drain plate layer melon having no electrode η are formed, and then a third insulating layer is formed. Finally, the second source plate layer 22b and the second drain plate layer are formed. The source electrode η and the dead electrode (4) are layered structures, and are respectively connected to the source region 13 and the recording region u. The floating electrode 12 is used to reduce the gate electrode by using the drift region 12, the first source plate layer 2h, the second source plate layer, the first electrode plate layer and the second drain plate layer 21b. 23. The field effect concentration between the drift region 12 and the junction of the non-polar region i 明 高 高 高 电压 , , , , , , , , 第 第 第 第 第 第 第 第 第 第 第 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来The resistance structure formed by the gate electrode 23, the resistor source 9 1290766 region 14 and the drain region η will be described in detail, and the "ic diagram" is a cross-sectional view at the π-π indicated in the "recognition map". The P-type substrate 1 has a p-type stray crystal. In the worm layer, the aforementioned phoenix 12 is formed (including an extension portion). A portion of the extension portion 12a is doped with a high concentration of N-face to form a resistance source 1 U. On the resistance source region 14 The resistor source electrode % is connected. Further, the extension portion 12 has a first insulating layer 3, the first layer 3G has a gate electrode 23, and the gate electrode 23 has a second insulating layer 31, and a second The first layer of the insulating layer 3 ι has a third insulating layer 32 on the first source plate layer, and the second insulating layer 32 has a second source plate layer 22b. The drift region 12 (including the extending portion 12a) The conductive energy sample is N-type 'and p-type wormhole layer (4) opposite, and the drift region 12 (including the N-type ion of the extension part called the N-type ion is more resistant than the N-type ion of the resistive source region 汲 and the bungee region U The concentration is low. At this time, the gate electrode Μ, the resistance source region Μ and the drain region form a resistance structure. The button electrode 21 is connected to a high voltage, and the voltage of the electrode 高于 is higher than the starting voltage. The drift region I between the region 14 and the bungee region U is shaped by the __ domain stop (pinehedGff), because the cutoff margin (pi. ',) and the cutoff voltage of the cutoff resistor (Pinched volta) Ge) can be designed to purchase volts to provide optimum performance under high operating conditions. - Bu Lai Ming sees the circuit diagram of Figure 2 to illustrate the applicability of the present invention. The voltage input terminal HV is connected to the drain contact d, and the gate contact is M〇s (indicated at % in the figure) and the resistor is shared, and the source contact is connected to the P circuit 200 as the output terminal. In addition, the gate contact ^ can be connected via the control bath source contact A, and can directly control the resistor R. Therefore, 10 1290766 resistor source contact A, gate contact G, source contact S, the internal circuit 200 and the control circuit 100 are the low voltage portion LV. Therefore, the LDM 〇s having the resistance R (Fig.; indicating IV [where] can be used as the starting or inductive loop under high voltage use conditions. The resistance R is the gate The off-resistance of the gate contact G control, the current flowing through the resistor R can be limited or cut off by the gate contact G. In addition, the voltage of the resistor source contact a can also be limited, so that the sense resistor source contact A can be sensed. The high voltage of the drain contact D provides a small initial current and can be sensed at the resistor source contact When the voltage is too high, the current is cut off, so that the internal components are not damaged under high voltage operation at the input end. In addition, the structure of the present invention can be improved according to the needs or uses of the process. Please refer to "3rd picture" as the basis. According to a second embodiment of the invention, as shown in Fig. 3, the p-type substrate 10 has a P well region 10b, and an N-type drain region n and a drift region 12 are formed. The p-type stray layer is on the p-type substrate, which simplifies the recording process. The correction region 13 includes high doping and low doping region 13b 'the high doping of the positive doping 13a is high. In the low doped region 13b, the low doped region 13b can reduce the field effect concentration between the source region 13 and the channel 15 junction to help increase the return voltage, and can be adapted for use under higher electrical components. Further, the 'thick electrode 21 and the source _22 on the second insulating layer 31, and only a single-layer flat structure' can also simplify the process steps. The layered structure ' of the tantalum electrode 21 and the source electrode 22' may be a single layer or a plurality of layers, depending on the requirements of the use of the element, and the more the number of layers of the layered layer, the more difficult the electric field is. , effectively reduce the field effect concentration and increase the breakdown voltage. Furthermore, the electrode 21 of the present invention can be used as a wire bonding interface (code ~_), 11 1290766 for wiring. Please refer to Fig. 4 for a detailed description of the third embodiment of the present invention. As shown in the figure, the first-polar plate layer and the second plateless layer 2ib are connected to the drain region n. Between the first-drain plate layer 21a and the drain region n, there is a second insulating layer 31 having a first insulating layer 32 between the first drain plate layer 21a and the second drain plate layer. The second insulating layer is layered to form a thin insulating layer %, so that the surface exposed by the -2 dipole plate layer 21b can be used as a wire bonding junction. In the conventional technology φ, the wire connection is additionally connected to adapt to the high-voltage use condition, but if the drain is connected to the internal circuit by a metal wire, a local high electric field effect is caused, and the LDMOS whirl is greatly reduced. Therefore, the present invention is used as a wire bonding interface, which not only solves the above-mentioned _, but also does not require space to connect additional wire bonding surfaces, thereby reducing the component size. In addition, as shown in Fig. 1A, the circular semiconductor structure is shown to reduce the size of the center bungee region. Please refer to the "figure $" for the fourth embodiment of the present invention. As shown in the figure, the distance between the first dipole plate layer 2ia and the contact region of the non-polar region u is determined as 'a large towel_such as a bungee area u. area. Combined with the second non-polar plate layer, "Shen Xin can be the same as the outside of the wire joint, so that the overall size of the semiconductor component can be greatly reduced. It is easy to mass-produce the process of the CM0S process, which is the same as the CM0S process of diffusing metal oxide semiconductors. The production method can be roughly described at the same time as the "1B map" and the "1c map". Prior to the p-type substrate 10 (or the unpatterned layer 1Ga), the micro-well (μ) μ μ sub-implant is used to form the p-well region, the drain region η (five), and the source region 1290766.

(n+). Next, a first insulating layer 30 is formed over the drift region 12, and the first insulating layer 3 is a field oxide layer formed by a region of Lithium oxide (L〇c〇s). Then, a gate electrode is formed on the surface of the insulating layer % over the via 15 and the extension portion 12a, and the gate electrode 23 is a polysilicon layer, which is patterned by an exposure lithography process to define a pattern. . In addition, the source region 13 may first form a low doped region (4) to form a high mismatch region 13a (n+). Alternatively, the first/baginal layer 31' may be formed on the substrate including the gate electrode 23^p type substrate (7) and formed on the second insulating layer by the exposure lithography and the engraving process, respectively, and the source region 13 and the drain region n The first source plate layer 22a, the first-drain plate layer 21a and the resistance source electrode % are connected to the electric-electrode region. The first _ w slab 22a and the slab layer 仏 are metal layers, and both of them can be defined by the exposure lithography process on the second insulating layer. The source of the resistor source is made of metal and extends outward to the control loop (see "Figure 2"). Next, a first source plate layer 22a and a first 第二t second source plate layer 22b and a second bottom plate layer are respectively formed on the first source plate layer and the first plate electrode layer 32 of the 匕s. 2.

5L substrate 10 is 幵v into a second insulating layer, and is exposed on the third insulating layer 32 by using the exposure lithography and the side spear; a second source connected to the pole plate layer 21a; the second source plate The layer 22b and the three insulating layer 32 are extended, and the structure can also be made as a single layer or multiple layers, and only needs to be controlled.

The layered layer of the layered gentleman and the metal layer of the tantalum electrode 21 may be 22. According to "Figure 2"). 13 1290766 Finally, a fourth insulating layer 33 is formed, and an exposure lithography process is used to match the surface of the second drain plate layer 21b to expose the surface of the second drain plate layer 21b. Which one? The portion of the conductivity type can be replaced by the N-type and the portion having the N-type conductivity can be replaced with the P-type, which can also form the structure required for the present invention. The LDM0S having a resistor of the present invention forms a resistor structure by using a gate, a source and a drain to form an LDMOS structure. Let the LDM0S with resistance be used as the starting or inductive loop under high voltage use conditions, and the resistance is controlled by the job, which can limit or cut off the current flowing through the resistor. This resistor can sense the height of the drain and provide a smaller The starting current, and the current can be cut off when the excessively high dragon is sensed, so that the components under high voltage operation are prevented from being damaged. The drifting dragon, the layered knot, the secret layer, the green shot is reduced _, the area and the bungee are connected to the field. Make: Yu Xuer tear, magnetic _ surface ^ shared idle pole no connection line to the secret 汲 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And this general CMOS process is convenient for industrial mass production. The present invention is disclosed in the foregoing embodiments. It is intended to limit the patent bribes of the present invention without departing from the spirit and scope of the invention. _本发骑衫 ^ The scope of the patent application attached. Further reference to the reference 14 1290766 [Simplified description of the drawings] Figs. 1A to 1C are diagrams of the first embodiment of the present invention; Fig. 2 is a schematic diagram of the application of the circuit of the present invention; Fig. 4 is a view showing a third embodiment of the present invention; and Fig. 5 is a view showing a fourth embodiment of the present invention. [Main component symbol description]

10 ........................P-type substrate 10a..................... . Insect layer 10b......................P well area 11........................ ..... bungee area 12 ..................······Drift area 12a.............. ........Extension 13 ........................Source Zone 13a........... ...........Highly doped region 13b......................low doped region 14 ....... .................Resistor source region 15........................Channel 21 .. ......................; and electrodes 21a......................first Bungee plate layer 21b......................2nd bungee plate layer 22 ................ ........source electrode 15 1290766 22a......................first source plate layer 22b........ ..............Second source plate layer 23........................gate electrode 24 .. ......................resistance source electrode ........................ First insulating layer 31........................second insulating layer 32 ................ ........the third insulation layer

33 ........................ Fourth insulation layer HV................... .. high voltage input terminal LV..................................... low voltage part D.. .......................汲 contact G...................... ...gate contact S..........................source contact A........... ..............Resistor source contact

Μ........................Horizontal Diffusion Metal Oxide Semiconductor (LDMOS) R............... ..........resistance 100......................Control circuit 200............ .........internal circuit 16

Claims (1)

K Year 8: Month&gt;&gt; Japanese Repair (more) Original 1290766 X. Patent Application Range: A rolling laterally diffused metal oxide semiconductor transistor having a cut-off resistance, comprising: a first conductive state a substrate; a drain region having a second conductive state, the drain region being formed on the US; 1 - drift region, the drift region having the same electrical property as the second waveguide, wherein the drift region is formed The substrate is connected to the button (4), and the milk ticket transfer region has an extension portion; the source region 'the source region is electrically identical to the second conductive state, wherein the source region is formed on the substrate and The drift region is separated by a channel; an electrode is located above the channel and the extension portion, wherein the dummy electrode and the substrate have an insulating layer; a drain electrode is connected to the drain region; and a source electrode is connected to the source a resistor source region, the residual source surface is formed on the extension portion, and the resistor source region is electrically identical to the second conductive state; and a resistor source electrode is coupled to the resistor source region. The high-voltage laterally diffused metal-emulsion semiconductor transistor having a cut-off resistance as described in the above-mentioned claim, wherein the substrate is a substrate of a worm-in-situ layer, and the conductive layer of the county layer and the first-conducting state The same. For example, the application of paste _ i refers to the high-pressure lateral diffusion 17 1290766 metal oxide semiconductor transistor 'where the polar region, the drift region, the source region and the resistance source region are lithography process and Formed by ion implantation. 4. The high voltage laterally diffused metal oxide semiconductor transistor having a turn-off resistance according to claim 3, wherein the source region comprises a high doped region and a low doped region. The concentration of Zhirenxuan is higher than that of the low-handed area. 5. The high-voltage laterally diffused metal-oxide-semiconductor (OLED) transistor having a resistance resistor according to the above-mentioned patent application, wherein the substrate has a well region, and the electrical region of the well region is the same as the first conductive state The domain impurity region is formed in the well area. 6. If the material is surrounded by a high-pressure lateral diffusion metal oxide semiconductor f crystal, which has a layered structure, the layered structure extends above the drift region. 7. A high-pressure laterally diffused metal-oxide-semiconductor transistor according to the sixth aspect of the invention, which is characterized in that it has a two-insulation layer between the layered structure and the substrate. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; ^ Flat panel = = The material of the mechanical resistor of the eighth aspect is a transverse metal emulsion semiconductor transistor in which each of the flat layers has an insulating sound. 10. If the application has a cut-off resistance as described in the above paragraph, the metal oxide is completely 峨__layer = expansion = the layered structure extends above the drift region. The high-voltage laterally diffused metal oxide semiconductor transistor having a cut-off resistance according to claim 10, wherein the layered structure and the substrate have an insulating layer. 12. The high voltage laterally diffused metal oxide semiconductor transistor having a turn-off resistance according to claim 10, wherein the layered structure has at least one flat plate 13. The cutoff as described in claim 12 The high voltage laterally diffused metal oxide semiconductor transistor of the resistor has an insulating layer between each of the flat layers. 14. The high voltage laterally diffused metal oxide semiconductor transistor having a turn-off resistance according to claim 1, wherein the first conductive state is a P type and the second conductive state is an N type. 15. The high voltage laterally diffused metal oxide semiconductor transistor having a turn-off resistance according to claim 1, wherein the first conductive state is an N-type and the second conductive state is a P-type. 16. The high voltage laterally diffused metal oxide semiconductor transistor having a turn-off resistance according to claim 1, wherein the surface of the germanium electrode is a wire bonding interface. 19