1289931 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種非揮發性記憶體 於一種邊際場誘發區域載子捕獲变記憶 Induced Localized Charge Trapping Memory) ° 【先前技術】 半導體製程之趨勢不斷朝向致力於縮 小使得積集度提昇，因此元件之設計便不 間之觀念演進。目前元件之尺寸已被縮小 更小的範圍。隨著半導體的演進，非4 (nonvolatile memory)也不例夕卜。非揮發性 亦隨著趨勢縮小元件尺寸或提升其單位之 非揮發性記憶體包含不同型式的元件，例 程唯讀記憶體），EEPROM (電子式可抹除 憶體），快閃記憶體，不同型式元件之趨勢 久性及南速度之需求方面發展。各種之非 結構已陸續提出。非揮發性記憶體包含一 的機制，如懸浮閘極（指快閃記憶體而言） 控制單元。非揮發性記憶體可以應用在電 出入系統（BIOS)，高密度非揮發性記憶體 ’特別是有關 體（Fringing Field 小各元件之大 斷朝向節省空 至奈米等級或 ^發性記憶體 記憶體的製造 記憶胞數量。 b PROM(可編 可編程唯讀記 均朝向於高持 揮發性記憶體 可以儲存電荷 以及電荷出入 _的基本輸 的應用範圍則 5 1289931 個 例 動 能 中 體 須 存 壓 極 穿 供 極 厚 之 控 極 閘 電 匕5可搞式設備中的大容量記憶裝置、固態相機以及 人電腦的界面卡等。非揮發性記憶體具有許多優點， 如决速存取時間、低功率損耗且耐用。為了迎合在機 十機系統中的應用需求，低電功率及快速存取的功 成為非揮發性記憶體的設計趨向。在傳統的技術領域 已發展出許多種不同形式的非揮發性記憶 Uonvolatile memo j)。非揮發性記憶體的資訊儲存必 依賴將電荷長時間留存於懸浮閘中，因此用以隔離儲 機制結構的介電層必須具有良好的特性。目前的低電 陕閃δ己憶體通常在3到5伏特的操作電壓下對浮動閘 (以快閃記憶體為例）進行充電或放電動作。由於電子 隧是洋動閘極充 — 應電壓的趨勢下，為了達到高電子穿隧效率，浮動 與基板間的介電層厚度必須予以縮減。然而當介電 度縮減至lOnm以下時，其可靠度也隨之降低。習 快閃記憶體欲進行程式化動作之操作方式之一，係 制閘極上施加高電壓，電子卽你访貧十 包土电卞即k矽基底之源極穿過 氧化層進入浮動閘極。欲進行技昤 疋仃诼除動作時，係於控 極上施加低電壓或不施電壓，扃 ^在♦基底之汲極施加 壓，電子即穿過閘極氧化層回到之源極。 望具有快速可寫以 現今 SOC(system on chip)技術期 1289931 及可讀之非揮發性記憶體製作於同一晶片之上。而單層 多晶石夕製程（single polysilicon processing)可以與其他元 件如電晶體製程整合。非揮發性記憶體除傳統利用雙層 多晶石夕製程（double polysilicon processing)的堆疊閘極 型記憶體（stack gate memories)之外，尚有所謂之電荷捕 獲型記憶體（charge trapping memories) ’其係利用〇N〇 或ON之結構來取代穿隧氧化層/浮動閘極之功能，利用 載子捕獲於0N0結構中之氮化矽層與否以定義數位狀 態。在0Ν0之結構之上方則配置控制閘極。此外，近似 之架構係有採用將儲存載子之膜層配置於控制閘極之底 側，如美國專利號US Patent No· 4,881，108、美國專利 號 U.S. Patent No, 5,768,192 ，發明人為 Eitan Β·，發明名稱 ’•Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping”，申請日為16 June，1998。有關電荷捕獲型記憶體之 先前技術可以參閱如美國專利號 USPatentNo· 6,335,554，發明人為Yoshikawau以及Kuniyoshi，發明名稱為 Semiconductor Memory，申請曰為3，7，2000·，上述專利揭露 具有ΟΝΟ結構之記憶體以儲存位元資訊。另外，相關文 獻可參閱 Chan，Τ·Υ· et al，’’A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,M IEEE Electron Device Letters, vol. EDL-8. No. 3, Mar. 1987 1289931 除此之外，近年又有所謂之鰭式電晶體（FinFET)型 態之非揮發性記憶體之提出。FinFET其通道形式類似鰭 狀故一般稱作鰭式電晶體（FinFET)。汲極、源極以及通 道區域主要位於一介電層上之單晶矽層中。閘極氧化層 形成於碎層表面，閘極則環繞包覆通道區域且形成雙閘 結構。故’鰭式電晶體（FinFET)之通道寬度也因此較大 而產生較傳統場效電晶體高之驅動電流。如美國專利號 US Patent No. 6,800,910，發明人為 Lin; Ming-Ren，申 請人為 Advanced Micro Devices，Inc·，發明名稱” FinFET device incorporating strained silicon in the channel region ' 申請日為December 31，2002。另可參閱美國 專利號 US Patent No· 6,770,516，，申請人為 Taiwan1289931 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory in a marginal field-induced region-induced localized charge Trapping Memory) [Prior Art] Trends in semiconductor manufacturing Constantly moving towards shrinking and increasing the degree of integration, the design of components is no longer evolving. The size of the current component has been reduced to a smaller range. With the evolution of semiconductors, nonvolatile memory is no exception. Non-volatile also scales down the component size or increases its unit of non-volatile memory containing different types of components, routine read-only memory), EEPROM (electronic erasable memory), flash memory, The trend of different types of components and the demand for south speed. Various non-structures have been proposed. Non-volatile memory contains a mechanism, such as a floating gate (referred to as flash memory) control unit. Non-volatile memory can be used in the electrical access system (BIOS), high-density non-volatile memory 'especially related to the body (Fringing Field small components of the large break towards saving to nanoscale or ^ memory memory The number of memory cells produced by the body. b PROM (programmable read-only memory is oriented towards high-volume volatile memory, which can store charge and charge input and exit. The basic application range of the load is 5 1289931. It is equipped with a large-capacity memory device, a solid-state camera, and a user interface card for a very thick control gate. The non-volatile memory has many advantages, such as speed-dependent access time and low speed. Power loss and durability. In order to meet the application requirements in the ten-machine system, low electric power and fast access work become the design trend of non-volatile memory. Many different forms of non-volatile have been developed in the traditional technical field. Uon volatile memo j). The information storage of non-volatile memory must rely on the retention of charge in the levitation gate for a long time, so it is used to separate The dielectric layer of the storage mechanism structure must have good characteristics. The current low-powered sigma-delta recalls usually charge or discharge the floating gate (for example, flash memory) at an operating voltage of 3 to 5 volts. In the trend that the electron tunnel is the charge of the oceanic gate, in order to achieve high electron tunneling efficiency, the thickness of the dielectric layer between the floating and the substrate must be reduced. However, when the dielectric is reduced to less than lOnm, The reliability is also reduced. One of the ways in which the flash memory is to be programmed to operate is to apply a high voltage to the gate, and the electrons are used to visit the poor ten-pack earth, that is, the source of the substrate. The oxide layer enters the floating gate. When the technology is removed, a low voltage or no voltage is applied to the gate, and the voltage is applied to the drain of the substrate, and the electron passes through the gate oxide layer. To the source. It is expected to be fast-writable with the current SOC (system on chip) technology period 1289931 and readable non-volatile memory fabricated on the same wafer. Single-layer polycrystalline silicon processing (single polysilicon processing) can Integrated with other components such as transistor processes. Non-volatile memory has a so-called charge in addition to the stacked gate gate memories that are traditionally used in double polysilicon processing. Charge trapping memories 'Use the structure of 〇N〇 or ON to replace the function of tunneling oxide/floating gate, and use the carrier to capture the layer of tantalum nitride in the 0N0 structure or not to define Digital status. The control gate is placed above the structure of 0Ν0. In addition, the approximate architecture is to use a film layer for storing carriers on the bottom side of the control gate. For example, U.S. Patent No. 4,881,108, U.S. Patent No. 5,768,192, the inventor is Eitan Β· The invention name is 'Non-volatile semiconductor memory cell utilizing a symmetric charge trapping', and the filing date is 16 June, 1998. The prior art regarding the charge trap type memory can be referred to, for example, U.S. Patent No. 6, Patent No. 6,335,554, the inventors are Yoshikawau and Kuniyoshi. The invention is entitled Semiconductor Memory, and the application is 3,7,2000. The above patent discloses a memory having a ΟΝΟ structure for storing bit information. Further, related documents can be found in Chan, Τ·Υ· et al, ''A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device, M IEEE Electron Device Letters, vol. EDL-8. No. 3, Mar. 1987 1289931 In addition, in recent years, there is a so-called fin-type transistor (FinFET) type. The introduction of non-volatile memory. FinFET has a channel form similar to fins and is generally called a fin transistor. The pole, source and channel regions are mainly located in a single crystal germanium layer on a dielectric layer. The gate oxide layer is formed on the surface of the fracture layer, and the gate surrounds the cladding channel region and forms a double gate structure. The channel width of the crystal (FinFET) is also large to produce a higher driving current than conventional field effect transistors. For example, U.S. Patent No. 6,800,910, the inventor is Lin; Ming-Ren, applicant is Advanced Micro Devices, Inc. The name of the invention "FinFET device incorporating strained silicon in the channel region ' application date is December 31, 2002. See also US Patent No. US Patent No. 6,770,516, Applicant is Taiwan
Semiconductor Manufacturing Company，發明名稱’’ Method of forming an N channel and P channel FINFET device on the same semiconductor substrate 丨’， 中請曰為Semiconductor Manufacturing Company, the invention name ''Method of forming an N channel and P channel FINFET device on the same semiconductor substrate 丨',
September 5，2002 〇 鑑於上述之說明’本發明提出邊際場誘發區域載子 捕獲型記憶體（^ηβίη§ Field Induced Localized Charge TrappingSeptember 5, 2002 〇 In view of the above description, the present invention proposes a marginal field-induced region carrier-captured memory (^ηβίη§ Field Induced Localized Charge Trapping)
Memory) 0 1289931 【發明内容】 ' 有鑑於此，本發明之目的在於提供一種邊際場誘發 區域載子捕獲型記憶體（Fringing Field Induced Localized ChargeMemory) 0 1289931 [Description of the Invention] In view of the above, an object of the present invention is to provide a Fringing Field Induced Localized Charge (Fringing Field Induced Localized Charge)
Trapping Memory) o 本發明之閘極結構與汲極離子摻雜區域形成非重疊 離子佈植（NOI)結構，且閘極結構側壁與矽層大致上形成 正交配置。邊際場誘發通道（Fringing-field-inducedchannel(FFIC)) 位於正交場誘發通道（Normal-field-induced channel (NFIC))以及 汲極側之間，即閘極結構與沒極離子摻雜區域間形成之 非重疊離子佈值（Gate-to-DrainNon-〇verlapped Implantation，NOI)，當 編程時載子自正交場誘發通道經由邊際場誘發通道流向 沒極。其中載子穿随發生於邊際場誘發通道下側。L型 介電層之垂直部係做為載子阻隔層，用以防止被捕獲之 載子自載子捕獲介電層脫逃。其中L型介電層之水平部 與垂直部可同步形成或各別形成。 根據上述目的，本發明提供一種邊際場誘發區域載 子捕獲型記憶體包含半導或絕緣底材，其底材可包含 SOI半導體底材。一半導體層，形成於上述底材之上， 離子摻雜區域，位於半導體層之部分區域做為汲極/源極 區域。閘極介電層，形成在上述半導體層上，鄰近該離 子摻雜區域，上述閘極介電層包含二氧化矽或是二氧化 9 1289931 :。閘極結構，形成在上述閘極介電層上。其中上述閘 電:構側壁與該半導體層大致上形成正交配置。L型介 層’形成於該閘極結構及部分該半導體層之上，該l 51介電層之水平部俜 11乐马戟千穿隧層，該L·型介電層之垂 I部係做為載子p # ^ ^Trapping Memory) o The gate structure of the present invention forms a non-overlapping ion implantation (NOI) structure with the drain-ion doped region, and the sidewalls of the gate structure and the germanium layer are substantially orthogonally arranged. The Fringing-field-induced channel (FFIC) is located between the normal-field-induced channel (NFIC) and the drain side, that is, between the gate structure and the electrodeless ion doping region. A non-overlapping ion implantation value (NOI) is formed. When programming, the carrier flows from the orthogonal field-induced channel to the immersion via the marginal field evoked channel. The carrier wear occurs on the lower side of the marginal field induced channel. The vertical portion of the L-type dielectric layer serves as a carrier barrier to prevent the captured carrier from escaping from the carrier-trapping dielectric layer. The horizontal portion and the vertical portion of the L-type dielectric layer may be formed simultaneously or separately. In accordance with the above objects, the present invention provides a marginal field induced region carrier-capable memory comprising a semiconducting or insulating substrate, the substrate of which may comprise a SOI semiconductor substrate. A semiconductor layer is formed over the substrate, and the ion doped region is located in a portion of the semiconductor layer as a drain/source region. A gate dielectric layer is formed on the semiconductor layer adjacent to the ion doped region, and the gate dielectric layer comprises cerium oxide or oxidized 9 1289931 :. A gate structure is formed on the gate dielectric layer. Wherein the gate: the sidewall is substantially orthogonal to the semiconductor layer. An L-type dielectric layer is formed on the gate structure and a portion of the semiconductor layer, and the horizontal portion of the dielectric layer 俜11 is a tunnel layer, and the vertical portion of the L-type dielectric layer As a carrier p # ^ ^
戰十阻隔層。載子捕獲介電層，配置於該L 型介^電夕 、 上用以形成可捕獲載子之機制以利於儲存 :、乂疋義數位訊號。閘極結構與汲極離子摻雜區域間 形成非重最Μ 2 & 且離子佈植（Gate-to-Drain Non-0verlapped implamati〇n， 冓…、中更包含口袋離子佈植區域鄰近該汲/源極 離子摻雜區域之_，且與該沒/源極離子摻雜區域之摻雜 子電II相反。另一實施例中，可包含輕微摻雜汲極位 原、極離子摻雜區域之側，其中該輕微摻雜的介面 夕雜之及/源極離子摻雜區域介面較淺且靠近該閘 極下之通道。同理，於其他實施例中可以包含雙摻雜汲 極在該汲/源極離子摻雜區之側，其中輕微摻雜的介面比 濃摻雜之該汲/源極離子摻雜區介面較深且靠近該閘極 γ之通道。 所述之邊際場誘發區域載子捕獲型記憶體之載子捕 擭介電層材質為気化矽或能隙小於6電子伏特之材質。 於其他貫&例中’可包含第一側壁間隙位於該載子捕獲 介電層之側’該第一側壁間隙為氧化矽或是能隙約大於 10 1289931 7電子伏特之材質。再者，其中更包含第二側壁間隙位 於第一側壁間隙之側，第二側壁間隙為氧化石夕或氣化 矽。上述閘極包含矽化金屬形成於閘極及該汲/源極離子 摻雜區域之上，矽化金屬之材質可包含TiSi2、CoSi2以 及N i S i。此外，上述閘極結構包含複晶矽層/矽化金屬層 /絕緣層。 【實施方式】 為使本發明之上述和其他目的、特徵、和優點能更 明顯易懂，本文舉較佳實施例，並配合所附圖式作詳細 說明如下，然下述各實施例只做一說明非用以限定本發 明。本發明之結構配置請先參閱第一圖到第三圖記憶單 體之三維以及戴面示意圖。本發明結構特徵包含閘極汲 極非重登離子佈植（gate-to_drain non-overlapped implantation (NOI))， 此結構得以健存兩位元之資訊。請先行參閱第一圖，在 此記憶體結構中顯示載子流朝向汲極流動。位於閘極旁 之截面L狀穿隧氧化層1 〇水平部分之區域形成一邊際場 誘發區域（Fringing Field Induced Region)，本發明之可包含平面 或非平面通道（例如Double-gate或Tri-gate of Fin FET)位於SOI底材之上。邊際場誘發通道2f位於一正交 場誘發通道2η(位於閘極6/閘極介電層4正下方）與汲極 1 4之間。熱載子在邊際場影響之下將經過穿隧氧化層μ 1289931 注入以及被捕獲且陷於載子捕獲介電材質' 1 2中，本例為 側壁間隙（sidewall spacer)。第二圖以及第三圖分別為本 發明之三維示意，其中顯示載子流動方向2 0以及邊際場 誘發通道之區域。閘極結構6與該離子摻雜區域1 4形成 非重疊離子佈植（NOI)結構，且閘極結構側壁與該半導體 層大致上形成正父配置。邊際場誘發通道 (Fringing-field-induced channel (FFIC))位於正交場誘發通道 (Normal-field-inducedchannel(NFIC))以及汲極側之間，當編程時 載子自正交場誘發通道經由邊際場誘發通道流向汲極。 其中熱載子穿隧發生於該邊際場誘發通道中。上述L型 介電層10之垂直部係做為載子阻隔層，用以防止被捕獲 之載子自載子捕獲介電層脫逃。其中該^型介電層1〇 之水平部與垂直部可同步形成或各別形成。本發明記憶 祖閘極"電層厚度約為7 nm，採用25〇nm N型複晶矽層 為閘極。側壁間隙以氣化石夕組成長度約為8〇nm，穿随氧 化層之厚度約為“m。其結構細部請參閱以下說明。其 中配置做為通道以及間極之半導體層之佈局約莫成正交 配置A閘極半導體層橫跨做為通道之碎層，如第二圖 所丁帛一圖之二維不意圖包含絕緣介電層覆蓋閘極之 側土表面’以及部分之做為通道區域之半導體層上，側 壁間隙配置於問極之側面，且座落於上述介電層之上， 12 1289931 詳細說明請參閱以下各實施例。 , 第四圖至第十三圖係本發明不同之實施例，載面分 別取自第二圖之ζ_γ以及平面。本發明包含半導體 底材2 ’在一實施例中以S〇I (sUiC0n on insulator)基底 做。兄明，然非用以限定本發明。一般在半導體層2中 可以利用淺溝渠絕緣技術製作隔離區域，例如 (shallow trench is〇Uti〇n)，但其非本發明重點故不賢 述閘極6/閘極介電層4分別位於上述半導體層2上。 離子摻雜區域（汲極/源極）丨4為於上述底材2之上且於 閘極6/閘極介電層4之側。—般通道位於閘極約莫正下 方之/及極/源極間。值得注意的是閘極與汲極非重疊離子 佈植（gate-to-drain non-overiapped implantation (NOI))，此結構得以使 得本結構儲存多位元之資訊。由圖二可了解，上述之閘 極6以及通道區域、汲極/源極1 4係採用矽層組成。利 用沉積以及微影製作通道圖案。上述閘極介電層4可由 二氧化矽、氧化锆或二氧化铪組成形成於通道區域之表 面。上述氧化矽薄膜一般可以在攝氏溫度約700至1 1 〇〇 度之下於氧環境中以熱氧化法長成。此外，也可以採用 其他方法如化學氣相沈積法（Chemical Vapor Deposition， CVD)形成。摻雜的複晶矽層6沈積於介電層4之上作為 閘極。此複晶矽層6的製作可以採用PH3為離子源，以 1289931 推雜法或是同步推雜法將峨離子捧入而成。再使用微影 技術定義控制開極之圖案。在此強調，本發明之控制問 極結構與'極間之非重叠離子佈植_)。介電絕緣層10 由Z載面觀之成L形之結構配置於閘極側壁之上，水 平部則位於製作汲極…上。其材質可以採用二氧化 石夕或二氧化給等之氧化物’或是能隙約大於7電子伏特 之材貝。側壁間&丨2配置於閘極之側壁上，並位於L 形；I電層之上。其中上述之水平部係做為穿隧介電層。 上述L形介電層1〇與側壁間隙12形成〇N結構可作為 捕獲載子機制以利於儲存載子以定義數位訊號。側壁間 隙1 2之材質可以為氮化矽或是或是能隙約小於ό電子伏 特之材質。側壁間隙12之製作方式可以採用形成一絕緣 層，接著對絕緣層進行非等向性蝕刻，以利於在控制閘 極6之側壁上形成一間隙壁12 ’且同步形成[形之結 構’側壁間隙之製作係習知技術。其中，非等向性蝕刻 可採用反應性離子姓刻法（reactive ion etching，RIE)或 是電漿蝕刻（plasma etching)。上述之絕緣層可以採用如 低壓化學氣相沈積法（Low Pressure CVD，LPCVD)或是 電聚增強式化學氣相沈積法（Plasma Enhanced CVD， PECVD)等任何適當的方法，沈積一氮化矽（SiNx)層。在 一具體實施例中，此氮化矽層可選擇SiH4、NH3、N2、 14 1289931 n2o作為反應氣體，於溫 N2〇 或是 SiH4Cl2 ' Nti3、、 度攝氏300至goo度之下形成 源/汲極區1 4位於閘極側下方兩側。其中可具有矽 化金屬16形成於閘極6以及該源/汲極區域μ之上。在 此方向可以觀察到此結構之氮化物側壁間.隙1 2可以分 別儲存兩個位元，圖號Μ做為被捕獲（trapped)載子之 7Γ w圖。其中該源/汲極區包含矽化金屬形成於其上，側 壁間隙12可以分別儲存第一位元以及第二位元，其數位 訊號狀態例如可為（0,0)、（1，〇)、（〇，1)'(1，1)。此方向 觀察之間隙壁兩者為一對稱之結構，左邊位元於抹除或 編程時與右邊位元執行相同功能時，其所對應之源、汲 極區剛好係為相反。因此該源/汲極區可以分別作為左、 元之源/及極區域，而構成幾近對稱之相反結構。 石夕化金4 16之材質可包含TiSi2、c〇Si2以及Nisi。製 作矽化金屬可以提昇導電性。以一實施例，在控制閘極、 源汲極區S/D之表面形成金屬，以利後續矽化製程。其 中，金屬可以採用鈦金屬或其他均等功能之金屬。之後， 塗佈一光阻層於預定之區域，以定義欲製作矽化金屬之 區域。之後，採用蝕刻技術去除未被光阻層所覆蓋之區 域。提供熱能源，如採用熱處理技術使得與矽基底接觸 金屬層與石夕產生石夕化反應形成碎化金屬層於閘極、源 15 1289931 汲極區S/D之上。在其他例子中，亦可以 作為矽化金屬。 接近S/D介面之電場十分顯著主要 中顯著之P-N介面形成。NOI誘發之熱 側壁間隙1 2之正下方，以及所產生之妖 邊際場影響下可被注入於氮化矽側壁 面’當汲極源極延伸部（source/drain extensi lightly doped drain，LDD)之摻雜量降低 構可增加介於寫入模式之熱載子電流， 入速度。爲調整其寫入速度特性，可以 構。基於沒極介面形成於氮化石夕側壁間 熱載子可以預期將在汲極介面邊緣產生 矽側壁間隙1 2中。 請參閱第五圖，本發明之第二實施 大致相仿，相同或近似之構造則採用相 說明。本實施例與第一實施例相異者包 上不包含矽化金屬丨6。控制閘極係由三 複晶矽層6a、矽化金屬6b、介電層6c 属6b包含WSi、TiSi2。介電層6c組成 氧化矽或是氮化矽/氧化矽之組合。 採、用矽化鎳（NiSi) 導因於N〇I製程 載子效應發生於 載子於閘極誘發 3隙12。另一方 1 implantation 或稱為 或省略時，此結 而且達到較大寫 1接省略L D D、结 隙1 2之下，通道 ’而注入至氮化 例與第一實施例 同之標波以利方^ 含源/沒極區 1 4 層結構組成包含 所組成。矽化金 可包含氮化發、 16 1289931 -參’第/、圖’本發明之第三實施例與第一實施例 相仿@理相同標號代表相同結構。本實施例與第 •實％例相異者包含具有-σ袋離子佈植區域（pocket n lmplantatl〇n)18位於源/汲極區14之側，鄰近上述 NOI區域下’且與源/汲極區μ之摻雜離子電性相反， 可抑制短通道效應，且可增進熱載子注入側壁間隙的效 率。第七圖則與本發明之第二實施例大致相仿，其亦包 含-口袋離子佈植區域18位於源/沒極區14之側且與源 /汲極區14之摻雜離子電性相反。 第八圖及第九圖分別對應於第六圖及第七圖，第八 及第九實葩例係採用輕微摻雜之汲極區域 drain) 14a。上述輕微摻雜之源/汲極區域之離子電性與 源/汲極區1 4之摻雜離子電性相同，但輕微摻雜區域之 介面比濃摻雜源/沒極區域之介面淺且靠近問極下之通 道。第十及第十一實施例係採用雙掺雜之源/汲極區域 (doubie diffused drain，DDD) Mb可以控制介面崩潰效應 (junction breakdown)。上述雙摻雜之汲極區域Mb之離 子電性與源/汲極區之摻雜離子電性相同，且靠近閘極下 之通道。 1289931 請參閱第十二及第十三圖，其與上述實施例大 同’唯在本例中，在介電層10外包含一介電層U 其上，接續一側壁間隙1 2位於其外側。換言之，除 層1 〇外’主要之差異在於採用雙側壁間隙結構1 1， 介電層1 1可為氮化矽材質，側壁間隙1 2係採用氧十 而利用氮化矽材質以利於載子陷入（trapped)其中， 储存載子之機制用以定義數位狀態。同理，第十四 十九圖與上述各實施例大部分相同，其中相對應之 亦在於採用氮化矽介電層1 1以及氧化物側壁間隙 代原先之單一氮化物側壁間隙。上述介電層1 〇、雙 間隙結構U，1 2形成ΟΝΟ結構。 第一十圖至第一十七圖之實施例係對前述之實 做—微幅變化，除介電層1 〇外，主要之差異在於採 層側壁間隙結構1 1，1 2，1 3。於原先介電層1 〇外側 序包含気化物之第一側壁間隙Π、第二側壁間隙1 及第三側壁間隙i 3，則形成在第二側壁間隙1 2之外 其材質為氧化物。因此，上述架構形成ΟΝΟ結構。 由本發明之實施例可知，側壁載子捕獲結構可 儲存數位訊號，因此，本結構可以儲存多位元之邏 號。而絕緣層配合側壁間隙之組成態樣可構成類似 致相 形成 介電 12 〇 ：*物， 做為 到第 差異 2取 側壁 施例 用三 ，依 2以 側， 分別 輯訊 ΟΝΟ 18 可以儲存載子 於氮化物材 1289931 或ON之結構 中。 可將汲極端定義為第一位元，源極端為 反之亦然。編程係藉由汲極端之電子穿隧效 藉由反相1於源極端加壓以及維持汲極端接 發明之N〇I n-M0SFETs時，讀取時通道電流基 極端被捕獲而產生而位於高電場側則不顯著 沒極與源極間之反向讀取電流方向之機制， 得知編程區域之狀態。一實施例中，於讀取£ 源極偏壓1V/0V，兩位元之起始電位差可高g 基於有一大非重疊區（NOI)介於閘極與s/D 較於傳統SONOS，誘發邊際電場變的十分低 n-MOSFETs之低邊際電場以及低汲極電流導致 產品哥命期。 以上所述僅為本發明之較佳實施例而已 限定本發明之申請專利範圍，凡其它未脫離 示之精神下所完成之等效改變或修飾，均應 之申請專利範圍内。 —之側壁間隙 第二位元， 應。讀取係 地。操作本 於載子於汲 。藉由改變 便可以感測 丨寺，當〉及極/ I 1 · 2伏特。 ‘面之間，相 ，因此，NOI 具有較長之 ，並非用以 本發明所揭 包含在下述 19 1289931 【圖式簡單說明】 ^ 第一圖係顯示本發明戴面示意圖。 第二圖係顯示本發明三閘場效通道及載子流動之三維示 意圖。 第三圖係顯示本發明三閘三維載面示意圖。 第四圖係顯示本發明第一實施例示意圖。 第五圖係顯示本發明第二實施例示意圖。 第六圖係顯示本發明第三實施例示意圖。 第七圖係顯示本發明第四實施例示意圖。 第八圖係顯示本發明第五實施例示意圖。 第九圖係顯示本發明第六實施例示意圖。 第十圖係顯示本發明第七實施例示意圖。 第十一圖係顯示本發明第八實施例示意圖。 第十二圖係顯示本發明第九實施例示意圖。 第十三圖係顯示本發明第十實施例示意圖。 第十四圖係顯示本發明第十一實施例示意圖。 第十五圖係顯示本發明第十二實施例示意圖。 第十六圖係顯示本發明第十三實施例示意圖。 第十七圖係顯示本發明第十四實施例示意圖。 第十八圖係顯示本發明第十五實施例示意圖。 第十九圖係顯示本發明第十六實施例示意圖。 20 1289931 第二十圖係顯示本j發明第十七實施例示意'圖。 第二十一圖係顯示本發明第十八實施例示意圖。 第二十二圖係顯示本發明第十九實施例示意圖。 第二十三圖係顯示本發明第二十實施例示意圖。 第二十四圖係顯示本發明第二十一實施例示意圖。 第二十五圖係顯示本發明第二十二實施例示意圖。 第二十六圖係顯示本發明第二十三實施例示意圖。 第二十七圖係顯示本發明第二十四實施例示意圖。 【主要元件符號說明】 半導體層2， 正交場誘發通道2n， 邊際場誘發通道2 f， 閘極介電層4， 閘極或摻雜的複晶矽層6， 載子捕獲儲存區8， 阻隔介電層或介電絕緣層1 〇， 第一側壁間隙壁Π， 第二側壁間隙1 2， 第三側壁間隙壁1 3， 源/ >及極區1 4， 1289931 矽化金屬1 6， ' 閘極結構：複晶矽層6 a、矽化金屬6b'介電結構層 輕微摻雜之沒極區域（lightly doped drain)14a， 雙摻雜之及極區域（double diffused drain)14b， 口袋離子佈植區域1 8， 載子流動方向20。 22Battle ten barriers. The carrier captures the dielectric layer and is disposed on the L-type dielectric to form a mechanism for capturing the carrier to facilitate storage: a digital signal. The gate structure and the doped ion doping region form a non-heavy Μ 2 & and the ion implant (Gate-to-Drain Non-0verlapped implamati〇n, 冓..., and the pocket ion implantation region is adjacent to the 汲/ source ion doped region _, and opposite to the doping / source ion doping region of the dopant II. In another embodiment, may include a slightly doped bismuth source, polar ion doped region a side, wherein the lightly doped interface/source ion doped region interface is shallow and close to the channel under the gate. Similarly, in other embodiments, a double doped drain may be included a side of the 汲/source ion doped region, wherein the slightly doped interface is deeper than the heavily doped 汲/source ion doped region interface and is adjacent to the gate of the gate γ. The carrier-trapping dielectric layer of the carrier-trapping memory is made of bismuth telluride or a material having an energy gap of less than 6 electron volts. In other examples, the first sidewall gap may be included in the carrier-trapping dielectric layer. The side of the first sidewall gap is yttrium oxide or the energy gap is greater than 10 1289931 7 electron volts material. Further, the second sidewall gap is located on the side of the first sidewall gap, and the second sidewall gap is oxidized or vaporized ruthenium. The gate includes a bismuth metal formed on the gate and the 侧壁Above the source ion doping region, the material of the deuterated metal may include TiSi2, CoSi2, and N i S i. Further, the gate structure includes a polysilicon layer/deuterated metal layer/insulating layer. The above and other objects, features, and advantages of the present invention will become more apparent and understood. The present invention relates to the structure configuration of the present invention. Please refer to the three-dimensional and three-dimensional schematic diagrams of the memory cells of the first to third figures. The structural features of the present invention include gate-to-drain non-overlapped Implantation (NOI)), this structure can store two-digit information. Please refer to the first figure first, in this memory structure, the carrier flow is shown to flow toward the dipole. The cross-section L-shaped tunnel is located next to the gate. The region of the horizontal portion of the layer 1 forms a Fringing Field Induced Region, and the present invention may include a planar or non-planar channel (eg, a Double-gate or Tri-gate of Fin FET) located above the SOI substrate. The marginal field induced channel 2f is located between an orthogonal field induced channel 2η (located directly below the gate 6/gate dielectric layer 4) and the drain electrode 14. The hot carrier will undergo tunneling under the influence of the marginal field. The oxide layer μ 1289931 is implanted and trapped and trapped in the carrier capture dielectric material '12, which is a sidewall spacer. The second and third figures are respectively three-dimensional representations of the invention, showing the carrier flow direction 20 and the area of the marginal field induced channel. The gate structure 6 forms a non-overlapping ion implantation (NOI) structure with the ion doped region 14, and the sidewalls of the gate structure and the semiconductor layer form a substantially positive parent configuration. The Fringing-field-induced channel (FFIC) is located between the normal-field-induced channel (NFIC) and the drain side. When programming, the carrier is induced from the orthogonal field via the orthogonal field. The marginal field induces a flow to the drain. The hot carrier tunneling occurs in the marginal field induced channel. The vertical portion of the L-type dielectric layer 10 acts as a carrier barrier to prevent the captured carrier from escaping from the carrier-trapping dielectric layer. The horizontal portion and the vertical portion of the dielectric layer 1〇 may be formed simultaneously or separately. The memory gate electrode of the present invention has an electric layer thickness of about 7 nm, and a 25 〇 nm N-type polysilicon layer is used as a gate. The sidewall gap has a length of about 8 〇 nm for gasification, and the thickness of the oxide layer is about “m. For details of the structure, please refer to the following description. The layout of the semiconductor layer configured as the channel and the interpole is about orthogonal. The A-gate semiconductor layer is disposed as a fragment of the channel. The second dimension of the second figure is not intended to include the insulating dielectric layer covering the lateral surface of the gate and the portion as the channel region. On the semiconductor layer, the sidewall gap is disposed on the side of the gate and is located on the dielectric layer. 12 1289931 For details, please refer to the following embodiments. The fourth to thirteenth drawings are different embodiments of the present invention. The carrier surface is taken from ζγ and plane of the second figure, respectively. The present invention comprises a semiconductor substrate 2' which is made of a substrate of S〇I (sUiC0on on insulator) in an embodiment, which is not intended to limit the invention. In the semiconductor layer 2, an isolation region can be formed by using shallow trench isolation technology, for example, (shallow trench is 〇Uti〇n), but it is not the focus of the present invention, so the gate 6/gate dielectric layer 4 is located above. semiconductor 2. The ion doped region (drain/source) 丨4 is above the substrate 2 and on the side of the gate 6/gate dielectric layer 4. The channel is located just below the gate. Between the pole and the source, it is worth noting that the gate-to-drain non-overiated implant (NOI) allows the structure to store information on multiple bits. As can be seen from Fig. 2, the above-mentioned gate 6 and the channel region and the drain/source 14 are composed of a germanium layer. The channel pattern is formed by deposition and lithography. The gate dielectric layer 4 can be made of cerium oxide or zirconium oxide. Or the ruthenium dioxide composition is formed on the surface of the channel region. The above ruthenium oxide film can be grown by thermal oxidation in an oxygen atmosphere at a temperature of about 700 to 11 degrees Celsius. In addition, other methods such as Formed by Chemical Vapor Deposition (CVD). The doped polysilicon layer 6 is deposited on the dielectric layer 4 as a gate. The polysilicon layer 6 can be fabricated by using PH3 as an ion source. 1289931 Push-mix method or synchronous push-mix method to bring 峨 ions into The lithography technique is then used to define the pattern of the control opening. Here, the control gate structure of the present invention and the non-overlapping ion implantation between the electrodes are emphasized. The dielectric insulating layer 10 is formed by the Z-load surface. The L-shaped structure is arranged on the sidewall of the gate, and the horizontal portion is located on the fabrication of the drain. The material can be made of oxide or the like of the dioxide or the oxidation of the oxide or the energy gap of more than 7 electron volts. The sidewalls & 丨 2 are disposed on the sidewall of the gate and are located on the L-shaped; I electrical layer, wherein the horizontal portion is used as a tunneling dielectric layer. The above-mentioned L-shaped dielectric layer 1 The sidewall gap 12 forms a 〇N structure that acts as a capture carrier mechanism to facilitate storage of the carriers to define digital signals. The material of the sidewall gap 1 2 may be tantalum nitride or a material having a gap of less than about ό electron volts. The sidewall gap 12 can be formed by forming an insulating layer, and then anisotropically etching the insulating layer to facilitate forming a spacer 12 ′ on the sidewall of the control gate 6 and simultaneously forming a [shaped structure sidewall gap]. The production is based on conventional technology. Among them, the anisotropic etching may be a reactive ion etching (RIE) or a plasma etching. The above insulating layer may be deposited by any suitable method such as low pressure chemical vapor deposition (LPCVD) or electropolymerization enhanced chemical vapor deposition (PECVD). SiNx) layer. In a specific embodiment, the tantalum nitride layer may be selected from SiH4, NH3, N2, and 14 1289931 n2o as a reaction gas to form a source/汲 under temperature N2〇 or SiH4Cl2 'Nti3, and a degree of Celsius 300 to goo. The pole region 14 is located on the lower side of the gate side. There may be a metallization 16 formed on the gate 6 and the source/drain region μ. In this direction, the nitride sidewall between the structures can be observed. The gap 1 2 can store two bits separately, and the figure Μ is taken as the 7Γ w map of the trapped carrier. The source/drain region includes a deuterated metal formed thereon, and the sidewall gap 12 can store the first bit and the second bit, respectively, and the digital signal state thereof can be, for example, (0, 0), (1, 〇), (〇, 1) '(1,1). The gaps observed in this direction are a symmetrical structure. When the left bit performs the same function as the right bit when erasing or programming, the corresponding source and drain regions are just opposite. Therefore, the source/drain regions can be used as the left/element source/pole region, respectively, to form a nearly symmetrical opposite structure. The material of Shi Xihua Gold 4 16 may include TiSi2, c〇Si2, and Nisi. The production of bismuth metal can improve conductivity. In one embodiment, a metal is formed on the surface of the control gate and source drain region S/D to facilitate subsequent deuteration processes. Among them, the metal can be made of titanium or other metal of equal function. Thereafter, a photoresist layer is applied over a predetermined area to define an area in which the metallized metal is to be formed. Thereafter, an etching technique is used to remove regions not covered by the photoresist layer. Provide thermal energy, such as the use of heat treatment technology to make contact with the ruthenium substrate. The metal layer and Shi Xi will produce a lithochemical reaction to form a shredded metal layer on the gate, source 15 1289931 bungee zone S / D. In other cases, it can also be used as a deuterated metal. The electric field close to the S/D interface is very significant, mainly in the formation of a significant P-N interface. The NOI-induced hot sidewall gap is directly below the surface, and the generated demon marginal field can be injected into the tantalum nitride sidewall surface's source/drain extensi lightly doped drain (LDD). The doping amount reduction structure can increase the hot carrier current and input speed in the write mode. In order to adjust its writing speed characteristics, it can be constructed. Based on the immersion interface formed between the sidewalls of the nitride, it is expected that a thermal carrier will be generated in the sidewall spacer 12 at the edge of the drain interface. Referring to Figure 5, the second embodiment of the present invention is substantially similar, and the same or similar configurations are illustrated. The present embodiment differs from the first embodiment in that it does not contain a deuterated metal crucible 6. The control gate includes WSi and TiSi2 from the triple germanium layer 6a, the germanium metal 6b, and the dielectric layer 6c. The dielectric layer 6c constitutes a combination of yttrium oxide or tantalum nitride/yttria. The use of nickel-doped nickel (NiSi) is caused by the N〇I process. The carrier effect occurs when the carrier induces a gap of 12 in the gate. When the other side 1 is implanted or called or omitted, the junction reaches a larger write 1 to omit the LDD, the junction gap 1 2, and the channel 'is injected into the nitridation example and the same as the first embodiment. The source/dimpole region consists of a four-layer structure consisting of components. The bismuth gold may include a nitrided hair, 16 1289931 - a reference to a third embodiment of the present invention. The third embodiment of the present invention is identical to the first embodiment. The present embodiment differs from the first embodiment in that the ion implantation region (pocket n lmplantatl〇n) 18 is located on the side of the source/drain region 14 adjacent to the NOI region and is connected to the source/汲The doping ion polarity of the polar region μ is opposite, which can suppress the short channel effect and improve the efficiency of the hot carrier injection into the sidewall gap. The seventh embodiment is substantially similar to the second embodiment of the present invention, which also includes a pocket-ion implant region 18 on the side of the source/no-polar region 14 and opposite to the doping ion polarity of the source/drain region 14. The eighth and ninth figures correspond to the sixth and seventh figures, respectively, and the eighth and ninth embodiments use a slightly doped drain region drain 14a. The ion conductivity of the lightly doped source/drain region is the same as that of the source/drain region 14 but the interface of the lightly doped region is shallower than the interface of the rich dopant/drain region. Close to the channel under the question. The tenth and eleventh embodiments employ a double doped source/dubie diffused drain (DDD) Mb to control interface breakdown. The ion conductivity of the double doped drain region Mb is the same as that of the source/drain region, and is close to the channel under the gate. 1289931 Please refer to the twelfth and thirteenth drawings, which are the same as the above embodiment. In this example, a dielectric layer U is disposed on the outside of the dielectric layer 10, and a sidewall gap 12 is located on the outer side. In other words, except for the layer 1 ', the main difference is that the double-wall gap structure 1 1 is used, and the dielectric layer 1 1 can be made of tantalum nitride. The sidewall gap 12 is made of oxygen and the tantalum nitride material is used to facilitate the carrier. Trapped in, the mechanism for storing carriers is used to define the state of the digits. Similarly, the fourteenth and nineteenth figures are mostly the same as the above embodiments, and the corresponding one is that the tantalum nitride dielectric layer 11 and the oxide sidewall spacers are used to replace the original single nitride sidewall gap. The dielectric layer 1 〇 and the double gap structure U, 1 2 form a ΟΝΟ structure. The embodiments of the tenth to the seventeenth embodiments are for the foregoing - a slight change, except for the dielectric layer 1 ,, the main difference being the sidewall spacer structure 1, 1, 2, and 13. The first sidewall gap 気, the second sidewall gap 1 and the third sidewall gap i 3 of the original dielectric layer 1 are formed outside the second sidewall gap 1 2 and are made of an oxide. Therefore, the above architecture forms a ΟΝΟ structure. It can be seen from the embodiment of the present invention that the sidewall carrier capture structure can store digital signals, and therefore, the structure can store multi-bit logic. The composition of the insulating layer and the sidewall gap can form a similar phase to form a dielectric 12 〇:*, as a difference to the second side of the sidewall application, three, according to the side of the 2, respectively, ΟΝΟ 18 can be stored In the structure of nitride material 1289931 or ON. The 汲 extreme can be defined as the first bit, and the source extreme is vice versa. The programming is based on the extreme electron tunneling effect by inverting 1 at the source terminal and maintaining the 汲 terminal in the N〇I n-M0SFETs of the invention. The channel current base is captured during reading and is located at a high level. On the electric field side, there is no significant mechanism for reading the direction of the current in the opposite direction between the dipole and the source, and the state of the programming area is known. In one embodiment, after reading the source bias voltage of 1V/0V, the initial potential difference of the two-element can be high g based on having a large non-overlapping region (NOI) between the gate and the s/D compared to the conventional SONOS. The marginal electric field becomes very low. The low marginal electric field of the n-MOSFETs and the low buckling current lead to the product's life. The above is only the preferred embodiment of the present invention, and the scope of the invention is defined by the scope of the invention, and the equivalent changes or modifications made by the invention are not included in the scope of the invention. - the sidewall gap second bit, should. Read the ground. The operation is based on the carrier. By changing, you can sense the temple, when it is > and the pole / I 1 · 2 volts. Between the faces, the phase, therefore, the NOI has a longer length and is not included in the present invention. The following is included in the following description. 19 1289931 [Simplified description of the drawings] ^ The first figure shows a schematic view of the wearing of the present invention. The second figure shows a three-dimensional representation of the three-gate field effect channel and carrier flow of the present invention. The third figure shows a schematic diagram of the three-dimensional three-dimensional loading surface of the present invention. The fourth figure shows a schematic view of a first embodiment of the present invention. The fifth figure shows a schematic view of a second embodiment of the present invention. Figure 6 is a schematic view showing a third embodiment of the present invention. The seventh figure shows a schematic view of a fourth embodiment of the present invention. The eighth figure shows a schematic view of a fifth embodiment of the present invention. The ninth drawing shows a schematic view of a sixth embodiment of the present invention. The tenth drawing shows a schematic view of a seventh embodiment of the present invention. The eleventh drawing shows a schematic view of an eighth embodiment of the present invention. Figure 12 is a schematic view showing a ninth embodiment of the present invention. Figure 13 is a schematic view showing a tenth embodiment of the present invention. Fig. 14 is a view showing the eleventh embodiment of the present invention. The fifteenth diagram shows a schematic view of a twelfth embodiment of the present invention. Fig. 16 is a view showing a thirteenth embodiment of the present invention. Figure 17 is a view showing a fourteenth embodiment of the present invention. Figure 18 is a schematic view showing a fifteenth embodiment of the present invention. Fig. 19 is a view showing a sixteenth embodiment of the present invention. 20 1289931 Fig. 20 is a schematic view showing the seventeenth embodiment of the present invention. The twenty-first embodiment shows a schematic view of an eighteenth embodiment of the present invention. The twenty-second figure shows a schematic view of a nineteenth embodiment of the present invention. A twenty-third figure is a schematic view showing a twentieth embodiment of the present invention. The twenty-fourth embodiment is a schematic view showing a twenty-first embodiment of the present invention. The twenty-fifth diagram shows a schematic view of a twenty-second embodiment of the present invention. The twenty-sixth embodiment shows a schematic view of a twenty-third embodiment of the present invention. The twenty-seventh embodiment shows a schematic view of a twenty-fourth embodiment of the present invention. [Major component symbol description] Semiconductor layer 2, orthogonal field induced channel 2n, marginal field induced channel 2 f, gate dielectric layer 4, gate or doped polysilicon layer 6, carrier capture storage region 8, Barrier dielectric layer or dielectric insulating layer 1 〇, first sidewall spacer wall 第二, second sidewall spacer 1 2, third sidewall spacer 1 3, source / > and polar region 1 4, 1289931 bismuth metal 1 6, 'Gate structure: polycrystalline germanium layer 6 a, deuterated metal 6b' dielectric structure layer lightly doped drained 14a, double diffused drain 14b, pocket ion Planting area 18, carrier flow direction 20. twenty two