1286765 九、發明說明： [相關申請案之交互參考] 本申請案主張2004年5月20日申請之韓國專利申請案第 P2004-36148號之優先權，該案之内容以全文引用的方式併 入本文中用於所有目的。 【發明所屬之技術領域】 本發明一般而言係關於半導體裝置之場，更具體而言， 係關於半導體記憶裝置中經改良之鏡像模式運作。 【先前技術】 圖1係一圖解闡釋一具有數個記憶體模組之傳統記憶體 系統100之方塊圖。記憶體系統100包括兩個記憶體模組105 及110。每一記憶體模組1〇5、11〇皆包括數個動態隨機存取 記憶體（DRAM)裝置120及一控制/位址（C/Α)缓衝器125。 DRAM裝置120及C/A緩衝器125係安裝於一模組板上。每一 記憶體模組105、110上之DRAM裝置120及C/Α緩衝器皆可 經由安裝在該母板/模組板上之一插座/連接器（未顯示）接 收自一控制器115傳輸之信號。該母板上之一資料（DQ)匯流 排及一時鐘（CLK)匯流排係共同與每一記憶體模組1 〇5、11 〇 上之DRAM裝置相連接。DRAM裝置120係該等DQ及CLK匯 流排之短接線負載，由此圖1中所示組態有時被稱作一，，短 接線-匯流排"組態。儘管圖1中僅顯示記憶體模組1〇5、u〇 之一侧’但在另一侧上可安裝有其它DRAM裝置120及/或 C/Α緩衝器125。於此情形下，記憶體模組105、u〇被統稱 為雙同軸記憶體模組（DIMMs)。 102051.doc 1286765 20-2、…、20-η 〇 每一記憶體裝置10-1、…、10-n、20·1、…、20-n可自一 記憶體控制器接收通用電力信號（p0wer)、通用命令信號 (com)、通用位址信號（add)、非共用命令信號（ncomi、 ncom2)、及通用資料信號（data)。一般而言，電力信號可包 括一供電信號（VCC)及一接地電位信號（VSS)。該等命令信 號（com)可包括若干信號，例如一時鐘信號（CK)、一列位址 選通信號（RASB)、一行位址信號（CASB)、一寫啟用信號 _ (WEB)、一時鐘啟用信號（CKE)等。 此外，該記憶體模組之前側1 〇上之記憶體裝置丨〇_丨、…、 10-n之每一個皆接收一”非共用，，命令信號nc〇in2。同樣地， _ 該記憶體模組之後側20上之記憶體裝置之每一個皆接收一 ， ”非共用”命令信號ncomi。換言之，通常將非共用命令信號 ncomi施加至該記憶體模組後側20上之所有記憶體裝置而 將非共用命令信號ncom2施加至該記憶體模組之前側1〇上 之所有記憶體裝置。出於本揭示之目的，以最寬廣之含義 解釋術語M非共用”以闡述該記憶體模組上所有記憶體裝置 之間通常不能共用之任何信號。 該等電力信號（power)接腳 '命令信號（com)接腳、位址信 號接腳（add)及資料信號接腳（data)通常連接至安裝在該模 組板上之所有記憶體裝置。然而，由於該等記憶體裝置之 - 每一個皆組態於一常態接腳佈置中，故與該記憶體模組之 後側2 0上之接腳佈置相比，該記憶體模組之前側1 〇上之接 腳佈置呈不對稱排列。鑒於此，必須在該模組板上分開共 102051.doc 1286765 之輸入L號为別轉換成内部命令信號（inc〇ine、丨c〇m)及内部 位址信號（iadd)而非轉變成其它内部信號。在常態模式中， 該等資料彳§號銲墊（PDATA)之輸入信號亦被分別轉換成若 干相應之内部資料信號（idata)。 為以上述鏡像或常態模式運作傳統記憶體裝置6〇〇，往往 必須增加裝置之大小以容納額外之任選銲墊（例如6〇〇_ 1、 600-2)或接腳。此將轉變成一製造成本之增加。 本發明之實施例將解決傳統技術中之此等及其它缺點。 • 【發明内容】 根據本發明之某些實施例，一種系統包括：一記憶體模 組’該記憶體模組具有一第一記憶體裝置、一第二記憶體 ~ 裝置及一模組板；及一記憶體控制器；該第一記憶體裝置 ♦ 經構造以回應分別經由一第一共用信號線及一第一非共用 信號線自該記憶體控制器所接收之一第一共用信號及一第 一非共用信號而運作於一鏡像模式或一常態模式中，該第 ^ 二記憶體裝置經構造以回應分別經由該第一共用信號線及 一第二非共用信號線自該記憶體控制器所接收之該第一共 用信號及一第二非共用信號而運作於一鏡像模式或一常態 模式中。 根據本發明之某些實施例，該第一共用信號係一晶片重 :置信號。 根據本發明之某些實施例，該第一非共用信號及該第二 非共用信號係晶片選擇信號。 根據本發明之某些實施例，該第一非共用信號及該第二 102051.doc 1286765 非共用信號係時鐘啟用信號。 根據本發明之某些實施例，該第一非共用信號及該第二 非共用信號係晶粒上終端信號。 根據本發明之某些實施例，該記憶體模組包括一 DIMM， 該DIMM之第一記憶體裝置佈置在該模組板之前側上一與 佈置在該模組板之後側上之第二記憶體裝置對應之位置。 根據本發明之某些實施例，該第一記憶體裝置包括··一 第一控制電路，其經構造以回應該第一共用信號及該第一 非共用信號而產生一第一控制信號；及一第一開關電路， 其經構造以回應該第一控制信號將一第二共用信號（其係 該第一記憶體裝置之一輸入）投送至該第一記憶體裝置之 一經選擇内部電路。 根據本發明之某些實施例，該第二記憶體裝置包括：一 第二控制電路，其經構造以回應該第一共用信號及該第二 非共用信號而產生一第二控制信號；及一第二開關電路， 其經構造以回應該第二控制信號將該第二共用信號（其係 該第二記憶體裝置之輸入）投送至該第二記憶體裝置之一 經選擇内部電路。 根據本發明之某些實施例，一種半導體記憶裝置包括： 一控制電路，其經構造以回應一第一命令信號及一第二命 令h號而產生一控制信號；及一開關電路，其經構造以回 應該控制信號將該半導體記憶裝置之一輸入投送至一經選 擇内部電路。 根據本發明之某些實施例，該控制電路包括：一第一緩 102051.doc 1286765 衝器，其經構造以回應該第一命令信號而產生一第一内部 4號；一第二緩衝器’其經構造以回應該第二命令信號而 產生一第二内部信號；及一正反器，其經構造以回應該第 内部信號及該第二内部信號而產生該控制信號。 根據某些實施例，該控制電路進一步包括耦合在該第一 緩衝器與該正反器之間及在該第二緩衝器與該第一緩衝器 之間的一延遲元件，該延遲元件經構造以減小流過該第一 緩衝器之電流。 馨 根據某些實施例’該第一命令信號包括來自一記憶體控 制器之一晶片選擇信號且該第二命令信號包括來自該記憶 體控制器之一晶片重置信號。 • 根據某些實施例，該第一命令信號包括來自一記憶體控 • 制器之一時鐘啟用信號且該第二命令信號包括來自該記憶 體控制器之一晶片重置信號。 根據某些實施例，該第一命令信號包括來自一記憶體控 _ 制器之一晶粒上終端信號而該第二命令信號包括來自該記 憶體控制器之一晶片重置信號。 根據某些實施例。該開關電路包括：一第一開關元件， 其經構造以回應該控制信號將該輸入投送至一第一内部電 路，及一第二開關元件，其經構造以回應該控制信號將該 輸入投送至一第二内部電路。 根據本發明之再其它實施例，一種方法包括：回應一共 用信號及一第一非共用信號（其係該第一記憶體裝置之輸 入），以一常態模式運作一第一記憶體裝置；及相對於該第 102051.doc -12- 1286765 一記憶體裝置，回應該共用信號及一第二非共用信號（其係 該第二記憶體裝置之輸入），以一鏡像模式運作一坌- ^ 一纟己憶 體裝置。 根據某些實施例，運作該第一記憶體裝置包括回應該共 用信號及該第^一非共用l號而產生一第一内部信號，今第 一内部信號經組態以控制一第一開關電路以將該第一纪惊 體裝置之一輸入投送至該第一記憶體裝置之至少兩個輸出 中之^一個。 根據某些實施例’運作該第二記憶體裝置包括回應該共 用信號及該第一非共用"is號而產生一第二内部信穿，今第 .二内部信號經組態以控制一第二開關電路以將該第二記憶 體裝置之一輸入投送至該第二記憶體裝置之至少兩個輸出 中之一個。 根據某些實施例，該共用信號包括接收自一記憶體控制 器之一晶片重置信號。 根據某些實施例，該第一非共用信號及該第二非共用信 號係選自由一晶片選擇信號、一時鐘啟用信號及一晶粒上 終端信號組成之群組中。 【實施方式】 圖6係-圖解閣釋一可與本發明實施例相容之DIMM之接 腳：置之示意圖。該_包括安裝至一模組板之前侧3〇 之右裝置3(M、···、3(^及安裝至—模組板之後側 40之若干記憶體裝置40-1、...、4〇_n。 與圖5中所示傳、统_Μ相比，圖艸所示麵％通常將一 102051.doc -13- 1286765 來自該記憶體控制器（未顯示）之重置信號（reset)施加至該 記憶體模組之前側30上之記憶體裝置30-1、…、30-n並施加 至該記憶體模組之後側40上之記憶體裝置40-1、…、40-n。 由此，該記憶體裝置具有一經組態以接收該重置信號之額 外接腳。該重置信號可用來初始化記憶體裝置30-1、...、 30-n 、 40-1 、…、40-n 〇 記憶體裝置30-1、…、30-n、40-1、…、40-n可包括（例如） 與DDR3 DRAM相容之若干高頻DRAM裝置。在可實施常態 DRAM運作之前，可使用該重置信號週期性地初始化該等 DDR3 DRAM裝置。 圖7係一圖解闡釋根據本發明之某些實施例之一能夠具 有鏡像模式功能之記憶體裝置800之示意圖。記憶體裝置 800可相當於圖6中所示之個別記憶體裝置30-1、…、30_n、 40-1 、…、40_n 〇 裝置800在外部接腳處接收若干外部信號，例如：電力信 號（VCC、VREF、GND)、非共用命令信號（NCOM)、命令信 號（COM)、位址信號（ADD)及資料信號（DATA)。上述外部 信號出現在相應之銲墊PVCC、PVREF、PGND、PNCOM、 PCOM、PADD及PDATA處。此外，記憶體裝置800亦具有一 重置接腳以接收自一記憶體控制器至一重置銲墊PRESET 之初始化信號（RESET)。記憶體裝置800可回應該重置信號 (RESET)而初始化，此通常以一相對低之頻率運作。 記憶體裝置800包括一開關電路810，該開關電路810具有 將該等外部施加之信號施加至各種内部電路之能力。開關 102051.doc 14- 1286765 電路810受控於一鏡像模式控制電路82〇，該鏡像模式控制 電路回應該重置信號（RESET)及該等非共用命令信號之一 而產生鏡像控制信號（con)。於本發明之替代實施例中，鏡 像模式控制電路820可響應於該重置信號（RESET)及一個以 上該等非共用命令信號（NCOM)。 根據本發明之某些實施例，當該鏡像控制信號（com)係在 一”高”位準時，記憶體裝置8〇0可運作於鏡像模式中。於此 情形下，開關電路810可將施加至該等命令及位址銲墊 (PNCOM、PCOM、及PADD)之輸入信號轉換成若干相應之 内邛 > 料信號（idata)。而該等資料信號銲墊（PDATA)之輸入 信號可被轉換成若干相應之内部命令及位址信號，例如 income、icom 〇 • 相反地，當該控制信號（c〇n)係在一，，低，，位準時，記憶體 裝置80G運作於_常態模式中。於此情形下，開關電路8 ^ 〇 將該等命令及位址銲墊（pncom、PC0M及PADD)之輸入信 ⑩號施加至若干相應之内部命令信號（income、⑹叫及内部位 唬（iadd)，且亦將該等資料信號銲墊（ρ〇ΑτΑ)之輸入信 號施加至若干相應之内部資料信號（idata)。 或者，應瞭解，該記憶體裝置可在該鏡像模式控制信號 與圖5中所示傳統記憶體裝置相比，</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> This article is used for all purposes. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the field of semiconductor devices and, more particularly, to an improved mirror mode operation in semiconductor memory devices. [Prior Art] FIG. 1 is a block diagram illustrating a conventional memory system 100 having a plurality of memory modules. The memory system 100 includes two memory modules 105 and 110. Each of the memory modules 1 〇 5, 11 包括 includes a plurality of dynamic random access memory (DRAM) devices 120 and a control/address (C/Α) buffer 125. The DRAM device 120 and the C/A buffer 125 are mounted on a module board. The DRAM device 120 and the C/Α buffer on each of the memory modules 105, 110 can be received from a controller 115 via a socket/connector (not shown) mounted on the motherboard/module board. Signal. A data (DQ) bus and a clock (CLK) bus on the motherboard are commonly connected to the DRAM devices on each of the memory modules 1 〇 5, 11 。. The DRAM device 120 is a short-wired load of the DQ and CLK busses, whereby the configuration shown in Figure 1 is sometimes referred to as a short-bus-bus configuration. Although only one side of the memory modules 1〇5, u〇 is shown in Fig. 1, other DRAM devices 120 and/or C/Α buffers 125 may be mounted on the other side. In this case, the memory modules 105 and u are collectively referred to as dual coaxial memory modules (DIMMs). 102051.doc 1286765 20-2, ..., 20-η 〇 Each memory device 10-1, ..., 10-n, 20·1, ..., 20-n can receive a universal power signal from a memory controller ( P0wer), general command signal (com), general address signal (add), non-common command signal (ncomi, ncom2), and general data signal (data). In general, the power signal can include a power supply signal (VCC) and a ground potential signal (VSS). The command signals (com) may include a plurality of signals, such as a clock signal (CK), a column address strobe signal (RASB), a row address signal (CASB), a write enable signal (WEB), and a clock enable. Signal (CKE), etc. In addition, each of the memory devices 丨〇_丨, . . . , 10-n on the front side of the memory module receives a “non-shared, command signal nc〇in2. Similarly, _ the memory Each of the memory devices on the rear side 20 of the module receives a "non-shared" command signal ncomi. In other words, a non-common command signal ncomi is typically applied to all of the memory devices on the back side 20 of the memory module. The non-common command signal ncom2 is applied to all memory devices on the front side of the memory module. For the purposes of this disclosure, the term M is not shared in the broadest sense to describe the memory module. Any signal that is normally not shared between all memory devices. The power signal pins 'command signal (com) pins, address signal pins (add), and data signal pins are typically connected to all of the memory devices mounted on the module board. However, since each of the memory devices is configured in a normal pin arrangement, the front side of the memory module is 1 compared to the pin arrangement on the rear side of the memory module 20 The pin arrangements on the cymbal are arranged asymmetrically. In view of this, the input L number of 102051.doc 1286765 must be separated on the module board to be converted into internal command signals (inc〇ine, 丨c〇m) and internal address signals (iadd) instead of being converted into other Internal signal. In the normal mode, the input signals of the data pads (PDATA) are also converted into corresponding internal data signals (idata). In order to operate the conventional memory device 6 in the above mirror or normal mode, it is often necessary to increase the size of the device to accommodate additional optional pads (e.g., 6 〇〇 1 , 600-2) or pins. This will translate into an increase in manufacturing costs. Embodiments of the present invention will address these and other shortcomings in the conventional art. According to some embodiments of the present invention, a system includes: a memory module having a first memory device, a second memory device, and a module board; And a memory controller ???the first memory device ♦ is configured to respond to one of the first common signals and one received from the memory controller via a first common signal line and a first non-shared signal line, respectively The first non-shared signal operates in a mirror mode or a normal mode, and the second memory device is configured to respond to the memory controller via the first common signal line and a second non-shared signal line, respectively. The received first common signal and a second unshared signal operate in a mirror mode or a normal mode. According to some embodiments of the invention, the first common signal is a wafer weight: set signal. According to some embodiments of the invention, the first unshared signal and the second unshared signal are wafer select signals. According to some embodiments of the invention, the first unshared signal and the second 102051.doc 1286765 non-shared signal are clock enable signals. According to some embodiments of the invention, the first unshared signal and the second unshared signal are terminal signals on the die. According to some embodiments of the present invention, the memory module includes a DIMM, and the first memory device of the DIMM is disposed on a front side of the module board and a second memory disposed on a rear side of the module board The location of the body device. According to some embodiments of the present invention, the first memory device includes a first control circuit configured to generate a first control signal in response to the first common signal and the first unshared signal; A first switching circuit configured to return a second common signal (which is input to one of the first memory devices) to a selected internal circuit of the first memory device in response to the first control signal. According to some embodiments of the present invention, the second memory device includes: a second control circuit configured to generate a second control signal in response to the first common signal and the second unshared signal; and A second switching circuit configured to post the second common signal (which is an input to the second memory device) to a selected internal circuit of the second memory device in response to the second control signal. According to some embodiments of the present invention, a semiconductor memory device includes: a control circuit configured to generate a control signal in response to a first command signal and a second command h number; and a switch circuit configured The input of one of the semiconductor memory devices is routed to a selected internal circuit in response to the control signal. According to some embodiments of the present invention, the control circuit includes: a first buffer 102051.doc 1286765 punch configured to generate a first internal number 4 in response to the first command signal; a second buffer ' It is configured to generate a second internal signal in response to the second command signal; and a flip-flop configured to generate the control signal in response to the internal signal and the second internal signal. According to some embodiments, the control circuit further includes a delay element coupled between the first buffer and the flip flop and between the second buffer and the first buffer, the delay element being constructed To reduce the current flowing through the first buffer. According to some embodiments, the first command signal includes a wafer select signal from a memory controller and the second command signal includes a wafer reset signal from the memory controller. • According to some embodiments, the first command signal includes a clock enable signal from a memory controller and the second command signal includes a wafer reset signal from the memory controller. In accordance with some embodiments, the first command signal includes a die-on-end signal from a memory controller and the second command signal includes a wafer reset signal from the memory controller. According to some embodiments. The switching circuit includes: a first switching element configured to feed the input to a first internal circuit in response to a control signal, and a second switching element configured to respond to the control signal to input the input Send to a second internal circuit. According to still other embodiments of the present invention, a method includes: operating a first memory device in a normal mode in response to a common signal and a first unshared signal (which is an input to the first memory device); In contrast to the 102051.doc -12-1228665 memory device, the common signal and a second unshared signal (which is the input of the second memory device) are operated in a mirror mode.纟 忆 忆 忆 。 。. According to some embodiments, operating the first memory device includes responding to the common signal and the first unshared number to generate a first internal signal, and the first internal signal is configured to control a first switching circuit Inputting one of the first-stage stun devices to at least one of the at least two outputs of the first memory device. According to some embodiments, the operation of the second memory device includes a response to the common signal and the first non-shared "is number to generate a second internal signal, and the second internal signal is configured to control a first The second switching circuit delivers one of the inputs of the second memory device to one of the at least two outputs of the second memory device. According to some embodiments, the common signal comprises a wafer reset signal received from a memory controller. According to some embodiments, the first unshared signal and the second unshared signal are selected from the group consisting of a chip select signal, a clock enable signal, and a die up terminal signal. [Embodiment] FIG. 6 is a schematic diagram of a pin of a DIMM that can be compatible with an embodiment of the present invention. The _ includes a right device 3 (M, . . . , 3 (^ and a plurality of memory devices 40-1, ... mounted to the rear side 40 of the module board) mounted to the front side of a module board. 4〇_n. Compared with the transmission shown in Fig. 5, the face % shown in Fig. 5 usually has a reset signal from the memory controller (not shown) of 102051.doc -13 - 1286765 ( The memory devices 30-1, ..., 30-n applied to the front side 30 of the memory module and applied to the memory devices 40-1, ..., 40 on the back side 40 of the memory module. Thus, the memory device has an additional pin configured to receive the reset signal. The reset signal can be used to initialize the memory devices 30-1, ..., 30-n, 40-1, ..., 40-n 〇 memory devices 30-1, ..., 30-n, 40-1, ..., 40-n may include, for example, a number of high frequency DRAM devices compatible with DDR3 DRAM. The reset signal can be used to periodically initialize the DDR3 DRAM devices prior to operation. Figure 7 is a diagram illustrating a memory device 80 capable of having a mirror mode function in accordance with some embodiments of the present invention. The memory device 800 can be equivalent to the individual memory devices 30-1, ..., 30_n, 40-1, ..., 40_n shown in Figure 6, and the device 800 receives a number of external signals at the external pins, for example : power signal (VCC, VREF, GND), non-common command signal (NCOM), command signal (COM), address signal (ADD), and data signal (DATA). The above external signals appear in the corresponding pads PVCC, PVREF , PGND, PNCOM, PCOM, PADD, and PDATA. In addition, the memory device 800 also has a reset pin to receive an initialization signal (RESET) from a memory controller to a reset pad PRESET. 800 can be initialized back to the reset signal (RESET), which typically operates at a relatively low frequency. The memory device 800 includes a switch circuit 810 having the externally applied signals applied to various internal circuits. Capabilities 102051.doc 14-1286765 Circuit 810 is controlled by a mirror mode control circuit 82, which is generated by a reset signal (RESET) and one of the non-shared command signals Mirroring control signal (con). In an alternate embodiment of the invention, mirror mode control circuit 820 can be responsive to the reset signal (RESET) and one or more of the non-shared command signals (NCOM). In an embodiment, when the mirror control signal (com) is at a "high" level, the memory device 8O0 can operate in the mirror mode. In this case, switch circuit 810 can convert the input signals applied to the command and address pads (PNCOM, PCOM, and PADD) into a number of corresponding enthalpy > material signals (idata). The input signals of the data signal pads (PDATA) can be converted into a number of corresponding internal command and address signals, such as income, icom 〇 • conversely, when the control signal (c〇n) is tied to one, The low, on-time, memory device 80G operates in the _normal mode. In this case, the switch circuit 8^ applies the command and the input pads of the address pads (pncom, PC0M, and PADD) to a number of corresponding internal command signals (income, (6), and internal bits (iadd). And, the input signals of the data signal pads (ρ〇ΑτΑ) are also applied to a plurality of corresponding internal data signals (idata). Alternatively, it should be understood that the memory device can control signals in the mirror mode and FIG. Compared to the traditional memory device shown in
102051.doc (_)在-"低”位料以—鏡像模式運作，而在該控制信號 (―在—”高"位準時以—常態模式運作。 比’記憶體裝置800無需 [模式控制信號及常態模 “運作如何，一諸如DDR3 ③ -15- 1286765 DRAM之高頻記憶體裝置基本上具有一用於初始化記憶體 裝置之重置信號。因此，根據本發明實施例之記憶體裝置 可使用現有重置信號及另一現有共用命令信號，來控制該 裝置於鏡像模式及常態模式中之運作。作為一結果，與上 述傳統記憶體裝置相比，根據本發明實施例之記憶體裝置 之大小可減小。 此外，由於記憶體裝置800可以鏡像模式運作，故一納含 若干記憶體裝置800之DIMM(例如圖6中所示之DIMM)可在 無短接線之反射及信號降級之情形下運作。 圖8係一圖解闡釋根據本發明之某些實施例之一鏡像模 式控制電路900之示意圖。鏡像模式控制電路900回應一自 重置銲墊（PRESET)所輸入之重置信號及回應一自晶片選擇 銲墊（PCSB)所輸入之晶片選擇信號（CSB)，而產生一鏡像控 制信號（con)。如圖7中所示，該晶片選擇信號（cSB)係一非 共用命令信號（NC0M)之實例。該晶片選擇信號（CSB)被輸 入至一為一正反器930產生一内部晶片選擇信號的晶片選 擇緩衝器910。該重置信號（RESET)被輸入至一為正反器930 產生一内部重置信號的重置緩衝器920。正反器930被鎖存 至來自晶片選擇緩衝器910之該内部晶片選擇信號，且回應 重置緩衝器920所產生之内部重置信號而產生該模式控制 信號（con)。 圖9係一圖解闡釋根據本發明之其它實施例之一鏡像模 式控制電路1000之示意圖。鏡像模式控制電路1000回應一 自重置銲塾（PRESET)所輸入之重置信號且回應一自晶片選 102051.doc -16- 1286765 擇鋒塾（PCSB)所輸入之晶片選擇信號（CSB)，而產生一鏡像 控制信號（con)。如圖7中所示，該晶片選擇信號（CSB)係一 非共用命令信號（NCOM)之實例。該晶片選擇信號（CSB)被 輸入至一為一正反器1040產生一内部晶片選擇信號的晶片 選擇緩衝器1010。該重置信號（RESET)被輸入至一為正反器 1040產生内部重置信號的重置緩衝器1020。正反器1040被 鎖存至來自晶片選擇緩衝器10 10之該内部晶片選擇信號， 且回應重置緩衝器1020所產生之内部重置信號而產生該鏡 像控制信號（con)。 另外，鏡像控制電路1000包括一經組態以減少流經晶片 選擇緩衝器1010之電流之延遲元件1030。亦即，晶片選擇 緩衝器1010回應一由延遲元件1030延遲之内部重置信號而 被啟用，並為正反器1040產生一内部晶片選擇信號。 圖10係一圖解闡釋根據本發明之再其它實施例之一鏡像 模式控制電路1100之示意圖。鏡像模式控制電路11 〇〇回應 一自重置銲墊（PRESET)所輸入之重置信號且回應一自時鐘 啟用銲墊（PCKE)所輸入之時鐘啟用信號（CKE)，而產生一 鏡像控制信號（con)。如圖7中所示，該時鐘啟用信號（CKE) 係一非共用命令信號（NCOM)之實例。該時鐘啟用信號 (CKE)被輸入至一為一正反器1130產生一内部時鐘啟用信 號的時鐘啟用緩衝器mo。該重置信號（RESET)被輸入至一 為正反器113 0產生一内部重置信號的重置緩衝器1120。正 反器1130被鎖存至來自時鐘啟用緩衝器mo之該内部晶片 選擇信號並回應重置緩衝器1120所產生之該内部重置信號 102051.doc -17- 1286765 而產生該模式控制信號（con)。 儘管圖10中未顯示，但在替代實施例中，鏡像模式控制 電路1100亦可包括一延遲元件。於此情形下，可採用與圖9 中延遲元件1030之相同方式將該延遲元件連接至該鏡像模 式控制電路。 圖11係一圖解閣釋根據本發明之某些其它實施例之一鏡 像模式控制電路1200之示意圖。鏡像模式控制電路12〇〇回 應一自重置銲墊（PRESET)所輸入之重置信號且回應一自晶 粒上終端銲墊（on_die termination pad ; POTC)所輸入之晶粒 上終端信號（on-die termination signal ; OTC)，而產生一鏡 像控制信號（con)。如圖7中所示，該晶粒上終端信號（〇tc) 係一非共用命令信號（NCOM)之實例。該晶粒上終端信號 (OTC)被輸入至一為正反器123〇產生一内部晶粒上終端信 號之晶粒上終端緩衝器1210。該重置信號（RESET)被輸入至 一為正反器1230產生一内部重置信號之重置緩衝器122〇。 正反器1230被鎖存至來自晶粒上終端緩衝器121〇之該内部 晶粒上終端信號，並回應重置緩衝器1220所產生之該内部 重置#號而產生該鏡像控制信號（con)。 儘管圖11中未顯示，但在替代實施例中，鏡像模式控制 電路1200亦可包括一延遲元件。於此情形下，可採用與圖9 中延遲元件1030相同之方法將該延遲元件連接至該鏡像模 式控制電路。 根據圖8-11中所示本發明之實施例，一鏡像控制電路回 應自一‘記憶體控制器所傳輸之一重置信號及一非共用命令 102051.doc •18- 1286765 信號產而生一控制信號。如上所述，該非共用命令信號可 包括：一晶片選擇信號（CSB)、一時鐘啟用信號（CKE)或一 晶粒上終端信號（OTC)。 圖12係一圖解闡釋可觸發與圖8及9所示實施例一致之鏡 像模式運作之信號位準之時序圖。當該鏡像控制信號（con) 具有一”高”位準時，該記憶體裝置以一鏡像模式運作。該 鏡像控制信號（con)回應位於一”高"位準之經緩衝晶片選擇 信號（SCSB)及經緩衝晶片選擇信號（SRESET)之一下降邊 緣而變遷至一 ”高，’位準。除該經緩衝晶片選擇信號（scSB) 由另一非共用命令信號（即，一經緩衝時鐘啟用信號（SCKE) 或一經緩衝晶粒上終端信號（SOTC))所替代之事實外，圖10 及11中之實施例可具有類似之時序圖。 圖13係一圖解闡釋可觸發與圖8及9中所示實施例一致之 常態模式運作之信號位準之時序圖。當該鏡像控制信號 (con)具有一 ”低”位準時，該記憶體裝置以一常態模式運 作。該鏡像控制信號（con)回應位於一，，低，，位準之經緩衝晶 片選擇信號（SCSB)且回應該經緩衝重置信號（sreset)之 一下降邊緣而具有一"低"位準。除該經緩衝晶片選擇信號 (SCSB)由另一非共用命令信號（即，一經緩衝時鐘啟用信號 (SCKE)或一經緩衝晶粒上終端信號（SOTC))所替代之事實 外’圖10及11中之實施例可具有類似之時序圖。 圖14係一圖解闡釋根據本發明之某些實施例之開關電路 1500之示意圖。開關電路1500適合用作（例如）圖7中之開關 電路810。 102051.doc -19- 1286765 開關電路15 00包括一第一選擇電路151〇及一第二選擇電 路1520。圖7中所示所有外部信號（RESET、nc〇M、COM、 ADD、DATA)皆被施加至第一及第二選擇電路151〇、152〇 中之每一個。來自該鏡像模式控制電路（未顯示）之鏡像控制 k號（con)亦被施加至第一及第二選擇電路151〇、152〇中之 每一個。 端視該鏡像控制信號（con)之邏輯狀態，第一及第二選擇 電路15 10、1520運作於鏡像模式或常態模式中。於鏡像模 式中’該等來自銲墊PRESET、PNCOM、PCOM及PADD之 外部信號皆被施加至相應數量之内部資料信號（idata)。同 樣地，該等來自銲墊pDATA之外部信號皆被施加至相應數 量之内部命令及位址信號（ireset、ine〇in、icom、iadd)。102051.doc (_) operates in the -&#;low" bit in mirror mode, and operates in the normal mode when the control signal ("in" high" is used. The control signal and the normal mode "how to operate, a high frequency memory device such as DDR3 3 -15 - 1286765 DRAM basically has a reset signal for initializing the memory device. Therefore, the memory device according to an embodiment of the present invention The existing reset signal and another existing common command signal can be used to control the operation of the device in the mirror mode and the normal mode. As a result, the memory device according to the embodiment of the present invention is compared with the above conventional memory device. In addition, since the memory device 800 can operate in a mirror mode, a DIMM containing a plurality of memory devices 800 (such as the DIMM shown in FIG. 6) can be reflected and signal-degraded without short wiring. Figure 8 is a schematic diagram illustrating a mirror mode control circuit 900 in accordance with some embodiments of the present invention. The mirror mode control circuit 900 responds with a self reset. A reset signal input by the pad (PRESET) and a wafer select signal (CSB) input from the chip select pad (PCSB) to generate a mirror control signal (con). As shown in FIG. The wafer select signal (cSB) is an example of a non-common command signal (NC0M) which is input to a wafer select buffer 910 which generates an internal wafer select signal for a flip-flop 930. The reset signal (RESET) is input to a reset buffer 920 which generates an internal reset signal for the flip-flop 930. The flip-flop 930 is latched to the internal wafer select signal from the wafer select buffer 910, and the response The mode control signal (con) is generated by resetting the internal reset signal generated by the buffer 920. Figure 9 is a schematic diagram illustrating one of the mirror mode control circuits 1000 in accordance with other embodiments of the present invention. Respond to a reset signal input from the reset pad (PRESET) and respond to a wafer select signal (CSB) input from the chip select 102051.doc -16-1286365 Selective Front (PCSB) to generate a mirror control Signal (con). The wafer select signal (CSB) is an example of a non-common command signal (NCOM) as shown in Figure 7. The wafer select signal (CSB) is input to a flip-flop 1040 to generate a The wafer select buffer 1010 of the internal wafer select signal. The reset signal (RESET) is input to a reset buffer 1020 that generates an internal reset signal for the flip-flop 1040. The flip-flop 1040 is latched to select from the wafer. The internal wafer select signal of buffer 10 10 and the mirror control signal (con) is generated in response to an internal reset signal generated by reset buffer 1020. Additionally, mirror control circuit 1000 includes a delay element 1030 configured to reduce current flow through wafer select buffer 1010. That is, the wafer select buffer 1010 is enabled in response to an internal reset signal delayed by the delay element 1030 and generates an internal wafer select signal for the flip-flop 1040. Figure 10 is a schematic diagram illustrating a mirror mode control circuit 1100 in accordance with still other embodiments of the present invention. The mirror mode control circuit 11 generates a mirror control signal in response to a reset signal input from the reset pad (PRESET) and in response to a clock enable signal (CKE) input from a clock enable pad (PCKE). (con). As shown in Figure 7, the clock enable signal (CKE) is an example of a non-common command signal (NCOM). The clock enable signal (CKE) is input to a clock enable buffer mo which generates an internal clock enable signal for a flip-flop 1130. The reset signal (RESET) is input to a reset buffer 1120 which generates an internal reset signal for the flip-flop 113 0 . The flip-flop 1130 is latched to the internal chip select signal from the clock enable buffer mo and generates the mode control signal (con) in response to the internal reset signal 102051.doc -17-1286765 generated by the reset buffer 1120. ). Although not shown in FIG. 10, in an alternate embodiment, mirror mode control circuit 1100 can also include a delay element. In this case, the delay element can be connected to the mirror mode control circuit in the same manner as the delay element 1030 of FIG. Figure 11 is a schematic illustration of a mirror mode control circuit 1200 in accordance with some other embodiments of the present invention. The mirror mode control circuit 12 responds to a reset signal input from the reset pad (PRESET) and responds to a die-on terminal signal input from an on-die termination pad (POTC). -die termination signal; OTC), producing a mirrored control signal (con). As shown in Figure 7, the on-die termination signal (〇tc) is an example of a non-common command signal (NCOM). The on-die termination signal (OTC) is input to a die-on-terminal buffer 1210 which is a flip-flop 123 generating an internal die-on terminal signal. The reset signal (RESET) is input to a reset buffer 122 that generates an internal reset signal for the flip-flop 1230. The flip-flop 1230 is latched to the internal die-on terminal signal from the on-die termination buffer 121 and generates the mirrored control signal in response to the internal reset # of the reset buffer 1220. ). Although not shown in Figure 11, in an alternate embodiment, mirror mode control circuit 1200 can also include a delay element. In this case, the delay element can be connected to the mirror mode control circuit in the same manner as the delay element 1030 of Fig. 9. According to the embodiment of the present invention shown in Figures 8-11, a mirror control circuit responds to a reset signal transmitted from a 'memory controller and a non-common command 102051.doc • 18-1286765 signal control signal. As described above, the non-common command signal may include a chip select signal (CSB), a clock enable signal (CKE), or an on-die termination signal (OTC). Figure 12 is a timing diagram illustrating the signal levels that can trigger the operation of the mirror mode consistent with the embodiment of Figures 8 and 9. When the mirrored control signal (con) has a "high" level, the memory device operates in a mirror mode. The image control signal (con) transitions to a "high" level in response to a falling edge of a "high" level buffered wafer select signal (SCSB) and a buffered wafer select signal (SRESET). Figures 10 and 11 except for the fact that the buffered wafer select signal (scSB) is replaced by another non-common command signal (i.e., a buffered clock enable signal (SCKE) or a buffered die terminal signal (SOTC)). Embodiments in the example can have similar timing diagrams. Figure 13 is a timing diagram illustrating the signal levels that can trigger normal mode operation consistent with the embodiment shown in Figures 8 and 9. When the mirrored control signal (con) has a "low" level, the memory device operates in a normal mode. The mirrored control signal (con) is responsive to a buffered wafer select signal (SCSB) at one, low, and level and back to the falling edge of one of the buffered reset signals (sreset) with a "low" bit quasi. In addition to the fact that the buffered wafer select signal (SCSB) is replaced by another non-common command signal (ie, a buffered clock enable signal (SCKE) or a buffered die terminal signal (SOTC)), Figures 10 and 11 Embodiments in the example can have similar timing diagrams. Figure 14 is a schematic diagram illustrating a switching circuit 1500 in accordance with some embodiments of the present invention. Switching circuit 1500 is suitable for use as, for example, switching circuit 810 in FIG. 102051.doc -19- 1286765 The switch circuit 15 00 includes a first selection circuit 151A and a second selection circuit 1520. All of the external signals (RESET, nc 〇 M, COM, ADD, DATA) shown in Fig. 7 are applied to each of the first and second selection circuits 151, 152, 。. A mirror control k number (con) from the mirror mode control circuit (not shown) is also applied to each of the first and second selection circuits 151, 152. Looking at the logic state of the mirrored control signal (con), the first and second selection circuits 15 10, 1520 operate in a mirror mode or a normal mode. In the mirror mode, the external signals from pads PRESET, PNCOM, PCOM, and PADD are applied to the corresponding number of internal data signals (idata). Similarly, these external signals from the pad pDATA are applied to the corresponding number of internal commands and address signals (ireset, ine, in, icom, iadd).
當以常態模式運作時，該記憶體裝置將該等外部信號直 接傳遞至相應之内部電路而無需再指配。例如，可將來自 PDATA銲墊之外部信號指配至相應數量之内部資料信號 (idata)。同樣地，可將來自 preSET、PNCOM、PCOM、PADD 及PDATA銲塾之外部信號指配至相應數量之内部命令及位 址"is 5虎（ireset、income、icom、iadd) 〇 可以多種方式實踐本發明。以上說明係對本發明實施例 之實例性而非限制性說明。 儘管在多個實例性實施例中闡述及圖解說明瞭本發明之 原理，但應瞭解，本發明並非僅限於此等所述具體實施例。 反之’可在佈置及細節方面對該等實例性實施例進行修改 且此並不背離本發明之原理。吾人請求所有修改及改變皆 102051.doc -20 -When operating in the normal mode, the memory device passes the external signals directly to the corresponding internal circuitry without re-assignment. For example, an external signal from a PDATA pad can be assigned to a corresponding number of internal data signals (idata). Similarly, external signals from preSET, PNCOM, PCOM, PADD, and PDATA soldering can be assigned to the corresponding number of internal commands and addresses "is 5 tigers (ireset, income, icom, iadd) 〇 can be practiced in a variety of ways this invention. The above description is illustrative and not restrictive of the embodiments of the invention. Although the principles of the invention have been illustrated and described in the various exemplary embodiments, it is understood that the invention is not limited to the specific embodiments. The exemplification of the exemplary embodiments may be modified in a manner that does not depart from the principles of the invention. We request all modifications and changes 102051.doc -20 -
1286765 涵蓋於隨附令請專利範圍之精神及範圍内。 【圖式簡單說明】 圖1係一圖解闡釋具有數個記憶體模組之傳統記憶體系 統之方塊圖。 圖2係一圖解闡釋一傳統鏡像配對佈置中兩個積體電路 之示意圖。 圖3係一 _闡釋一根據傳統技術耗合至一配對组態中1286765 is covered by the spirit and scope of the patent scope of the accompanying order. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a conventional memory system having a plurality of memory modules. Figure 2 is a schematic illustration of two integrated circuits in a conventional mirrored pairing arrangement. Figure 3 is a _ explanation 1 according to the conventional technology is consumed into a paired configuration
之-常態封裝及一鏡像封裝之記憶體控制器之示意圖。 圖4係圖解闡釋一在模組板上安裝有若干記憶體裝置 之傳統DIMM之接腳佈置之示意圖。 能之傳統記憶體 圖5係一圖解闡釋能夠具有鏡像模式功 裝置之示意圖。 圖6係一圖解闡釋根據本發明之某歧 一員她例之一 DIMM之 接腳佈置之示意圖。 圖7係-圖解_根據本發明之某些實施例之—能夠具 有鏡像模式功能之記憶體裝置之示意圖。 圖8係一圖解闡釋根據本發明之某 一耳轭例之一鏡像模 式控制電路之示意圖。 圖9係一圖解闡釋根據本發明之其 ^ , 、匕貫施例之一鏡像模 式控制電路之示意圖。 圖10係一圖解闡釋根據本發明之再 ^ ^ 匕貫施例之一鏡像 杈式控制電路之示意圖。 圖11係一圖解閣釋根據本發明之某 你b、、 卞—具它實施例之一鏡 像模式控制電路之示意圖。 102051.doc • 21 · 1286765 圖12係一圖解闡釋 鏡像模式運作之信號位準之時、:圖9及1〇所示實施例 圖13係一圖解閣釋可觸發與圖9及職示實施例 常態模式運作之㈣位準之時序圖。 圖14係-圖解闡釋根據本發明之某些實施例之一 路之示意圖。 致之 致之 關電A schematic diagram of a memory controller in a normal package and a mirror package. Figure 4 is a schematic diagram illustrating the arrangement of pins of a conventional DIMM having a plurality of memory devices mounted on a module board. Traditional Memory Figure 5 is a schematic diagram illustrating the ability to have a mirror mode power device. Fig. 6 is a schematic view showing the arrangement of the pins of one of the DIMMs according to a certain example of the present invention. Figure 7 is a schematic diagram of a memory device capable of having a mirror mode function in accordance with some embodiments of the present invention. Fig. 8 is a view schematically showing a mirror mode control circuit of an ear yoke according to the present invention. Fig. 9 is a view schematically showing a mirror mode control circuit according to the present invention. Figure 10 is a schematic illustration of a mirrored 控制 control circuit in accordance with a further embodiment of the present invention. Figure 11 is a schematic illustration of a mirror mode control circuit of one of its embodiments in accordance with the present invention. 102051.doc • 21 · 1286765 Figure 12 is a diagram illustrating the signal level of the mirror mode operation, the embodiment shown in Figures 9 and 1 Figure 13 is a schematic diagram triggering and Figure 9 and the embodiment of the job The timing chart of the (four) level of normal mode operation. Figure 14 is a schematic diagrammatic illustration of one of the embodiments of the present invention. To the cause
【主要元件符號說明】 10 前側 10-1 記憶體裝置 10-2 記憶體裝置 10-n 記憶體裝置 20 後側 20-1 記憶體裝置 20-2 記憶體裝置 20-n 記憶體裝置 30 前側 30-1 記憶體裝置 30-n 記憶體裝置 40 後侧 40-1 記憶體裝置 40-n 記憶體裝置 100 傳統記憶體系統 105 記憶體模組 110 記憶體模組 102051.doc -22- 1286765[Description of main component symbols] 10 Front side 10-1 Memory device 10-2 Memory device 10-n Memory device 20 Rear side 20-1 Memory device 20-2 Memory device 20-n Memory device 30 Front side 30 -1 Memory device 30-n Memory device 40 Rear side 40-1 Memory device 40-n Memory device 100 Traditional memory system 105 Memory module 110 Memory module 102051.doc -22- 1286765
115 控制器 120 動態隨機存取記憶體（DRAM)裝置 125 控制/位址（C/A)緩衝器 310 裝置 315 MUX 320 裝置 325 MUX 340 銲墊 345 銲墊 350 銲墊 355 銲墊 360 銲墊 365 銲墊 370 銲墊 375 銲墊 400 記憶體控制器 410 鏡像封裝（裝置） 420 常態封裝（裝置） 600 傳統記憶體裝置 600-1 任選銲墊 600-2 任選銲墊 610 開關電路 800 記憶體裝置 810 開關電路 102051.doc -23- 1286765 820 鏡像模式控制電路 900 鏡像模式控制電路 910 晶片選擇緩衝器 920 重置緩衝器 930 正反器 1000 鏡像模式控制電路 1010 晶片選擇緩衝器 1020 重置緩衝器115 Controller 120 Dynamic Random Access Memory (DRAM) Device 125 Control/Address (C/A) Buffer 310 Device 315 MUX 320 Device 325 MUX 340 Pad 345 Pad 350 Pad 355 Pad 360 Pad 365 Pad 370 Pad 375 Pad 400 Memory Controller 410 Mirror Package (Device) 420 Normal Package (Device) 600 Traditional Memory Device 600-1 Optional Pad 600-2 Optional Pad 610 Switch Circuit 800 Memory Device 810 Switching Circuit 102051.doc -23- 1286765 820 Mirror Mode Control Circuit 900 Mirror Mode Control Circuit 910 Chip Select Buffer 920 Reset Buffer 930 Rectifier 1000 Mirror Mode Control Circuit 1010 Chip Select Buffer 1020 Reset Buffer
1030 延遲元件 1040 正反器 1100 鏡像模式控制電路 1110 時鐘啟用緩衝器 1120 重置緩衝器 1130 正反器 1200 鏡像模式控制電路 1210 晶粒上終端緩衝器 1220 重置緩衝器 1230 正反器 1500 開關電路 1510 第一選擇電路 1520 第二選擇電路 102051.doc -24-1030 delay element 1040 flip-flop 1100 mirror mode control circuit 1110 clock enable buffer 1120 reset buffer 1130 flip-flop 1200 mirror mode control circuit 1210 die-on terminal buffer 1220 reset buffer 1230 flip-flop 1500 switching circuit 1510 first selection circuit 1520 second selection circuit 102051.doc -24-