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TWI285936B - Process for growing an epitaxial silicon layer on a semiconductor wafer - Google Patents

Process for growing an epitaxial silicon layer on a semiconductor wafer Download PDF

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Publication number
TWI285936B
TWI285936B TW090110944A TW90110944A TWI285936B TW I285936 B TWI285936 B TW I285936B TW 090110944 A TW090110944 A TW 090110944A TW 90110944 A TW90110944 A TW 90110944A TW I285936 B TWI285936 B TW I285936B
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Taiwan
Prior art keywords
semiconductor wafer
wafer
gas
crystal
cleaning gas
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TW090110944A
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Chinese (zh)
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Robert W Standley
Charles C Yang
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Memc Electronic Materials
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    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • H10P72/50
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4584Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally the substrate being rotated
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/12Substrate holders or susceptors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/90Apparatus characterized by composition or treatment thereof, e.g. surface finish, surface coating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10Apparatus

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

A modified susceptor for use in an epitaxial deposition apparatus and process is disclosed. The modified susceptor has an inner annular ledge capable of supporting a semiconductor wafer and has a plurality of holes in the surface to allow cleaning gas utilized during an epitaxial deposition process to pass through the susceptor and contact substantially the entire back surface of the semiconductor wafer and remove a native oxide layer. Also, the plurality of holes on the susceptor allows dopant atoms out-diffused from the back surface during the epitaxial deposition process to be carried away from the front surface in an inert gas stream and into the exhaust such that autodoping of the front surface is minimized.

Description

1285936 _案號90110944_年月日__ 五、發明說明(1) ^ 發明之背景 本發明係關於一種用於化學氣相沉積法之改良晶座。具 體而言,本發明係關於一種用於磊晶沉積反應器之具有多 個孔之改良晶座,使半導體晶圓正面之自動摻雜及半導體 晶圓背面上之不連續矽生長顯著減少或除去。 在由恰克勞斯基(C ζ 〇 c h r a 1 s k i )法生長之單石夕晶體之製 造中,多晶矽首先在具有或不具摻雜質之石英坩堝内熔 化。在多晶矽已熔化且溫度平衡化後,種子結晶被浸入熔 物内然後萃取以在石英坩堝旋轉時形成單晶矽錠塊。單晶 矽錠塊再被切成各個半導體晶圓,其受到若干加工步驟, 包括拋光/研磨、餘刻及磨光,以產生具有如鏡般光澤之 正面之最後半導體晶圓。為了製備最後晶圓供裝置製造, 晶圓可實施化學氣相沉積法如磊晶沉積法以在晶圓之正面 上生長通常為約0.1//m與約200//m厚之薄矽層,使裝置可 直接在屋晶層上製成。傳統蠢晶沉積法揭示於美國專利 5,9 0 4,7 6 9 號 5,7 6 9,9 4 2 號。 蠢晶沉積法通常包括二個步驟。在第一步驟中,在半導 體晶圓裝入沉積室内並向下在晶座上後,晶圓之前面在約 1 1 5 0 °C下施加清潔氣體如氫或氫/鹽酸混合物以π預烘焙π 及清潔矽晶圓之正面並除去該表面上之任何天然氧化物以 容許磊晶矽層連續又均勻地生長在正面上。在磊晶沉積法 之第二步驟中,晶圓之前面在約8 0 0 °C或以上施加蒸氣狀 矽源如矽烷或三氣矽烷以沉積並生長矽之磊晶層在正面 上。在蠢晶沉積法之二個步骤期間’半導體晶圓係藉旋 轉晶座支持於磊晶沉積室内,晶座通常在過程中旋轉以確1285936 _ Case No. 90110944_年月日日__ V. DESCRIPTION OF THE INVENTION (1) ^ Background of the Invention The present invention relates to an improved crystal holder for chemical vapor deposition. In particular, the present invention relates to an improved crystal holder having a plurality of holes for an epitaxial deposition reactor, which enables automatic doping of the front side of the semiconductor wafer and significant reduction or removal of discontinuous germanium growth on the back side of the semiconductor wafer. . In the fabrication of a monolithic crystal grown by the C ζ 〇 c h r a 1 s k i method, the polycrystalline germanium is first melted in a quartz crucible with or without doping. After the polycrystalline crucible has melted and the temperature is equilibrated, the seed crystals are immersed in the melt and then extracted to form a single crystal germanium ingot as the quartz crucible is rotated. The single crystal germanium ingot is then cut into individual semiconductor wafers which are subjected to a number of processing steps, including polishing/polishing, engraving, and buffing to produce a final semiconductor wafer having a mirror-like finish. In order to prepare the final wafer for device fabrication, the wafer may be subjected to a chemical vapor deposition method such as epitaxial deposition to grow a thin layer of germanium, typically about 0.1//m and about 200//m thick, on the front side of the wafer. The device can be made directly on the roofing layer. The conventional stray crystal deposition method is disclosed in U.S. Patent No. 5,900,7,9,5,7,6,9, 4, 2, 2, 2, 6, The stray deposition method usually involves two steps. In the first step, after the semiconductor wafer is loaded into the deposition chamber and down on the crystal holder, a cleaning gas such as hydrogen or a hydrogen/hydrochloric acid mixture is pre-baked at a front surface of the wafer at about 1150 °C. π and cleaning the front side of the wafer and removing any native oxide on the surface to allow the epitaxial layer to continuously and uniformly grow on the front side. In the second step of the epitaxial deposition method, a vapor source such as decane or trioxane is applied to the front side of the wafer at about 800 ° C or higher to deposit and grow a germanium epitaxial layer on the front side. During the two steps of the stray deposition method, the semiconductor wafer is supported by the epitaxial deposition chamber by means of a rotating crystal holder, and the crystal holder is usually rotated during the process.

O:\70\70781-960522.ptc 第5頁 1285936 _案號90110944_年月曰 修正_ 五、發明說明(2) ‘ 保磊晶層之均勻生長。晶座通常由高純度石墨所構成並具· 有碳化矽層完全覆蓋石墨以減少在高溫過程中污物如自石 墨釋出進入四周之量。用於磊晶生長法之傳統晶座為先行 技藝已知者且述於美國專利4,3 2 2,5 9 2號,4,4 9 6,6 0 9,5, 200, 157 號及5, 242, 501 號。 當傳統晶座用於磊晶沉積法時,在負載過程期間當晶圓 被降下在晶座上時,氣體可被截留在晶座與晶圓之間,造 成晶圓π漂浮”而以傾斜位置滑動在晶座上。此可導致不均 勻磊晶生長。此外,在預烘焙步驟期間,小量清潔氣體如 氫氣可散佈在晶圓與晶座間之晶圓邊緣四周,而進入晶圓 與晶座間之空間内。若晶圓之背面用氧化物層如低溫氧化 物層密封時,散佈之氫氣不會與氧化物層充分反應而在層 内產生針孔或完全除去氧化物層。若背面為許多裝置廠商 希望之蝕刻或磨光表面且僅具有薄天然氧化物層時,氫氣 或氫/鹽酸混合物通常會完全除去接近背面外緣之天然氧 化物層,其中清潔氣體散佈在晶圓四周,且當蝕刻自晶圓 之外緣向内移動時,在暴露矽表面之天然氧化物層内產生 針孔開口。此等針孔開口通常在晶圓四周形成環或π空洞 丨丨〇 在磊晶沉積過程期間,小量含矽源氣體亦可散佈在晶圓 與晶座間之晶圓邊緣四周並進入晶圓與晶座間之空間内。 若晶圓之背面被氧化物密封時,矽膜之成核及生長實質上 會抑制。在天然氧化物層完全被清潔氣體蝕刻掉之壓内, 生長石夕之平滑連續層。然而,在清潔氣體尚未完全除去天 然氧化物層而針孔已產生暴露矽時,含矽源氣體可沉積矽O:\70\70781-960522.ptc Page 5 1285936 _ Case No. 90110944_年月曰 修正 Amendment _ V. Invention description (2) ‘ Uniform growth of Baolei crystal layer. The crystal holder is usually composed of high-purity graphite and has a layer of tantalum carbide completely covering the graphite to reduce the amount of dirt, such as self-sludge, from entering the periphery during high temperature. Conventional crystal holders for epitaxial growth methods are known in the art and are described in U.S. Patents 4,3 2 2,5 9 2, 4,4 9 6,6 0 9,5, 200, 157 and 5 , 242, 501. When a conventional crystal holder is used for epitaxial deposition, when the wafer is lowered on the crystal holder during the load process, the gas can be trapped between the crystal holder and the wafer, causing the wafer to float π while tilting. Sliding on the crystal holder. This can result in uneven epitaxial growth. In addition, during the pre-baking step, a small amount of cleaning gas such as hydrogen can be spread around the edge of the wafer between the wafer and the crystal holder, and between the wafer and the crystal holder. In the space, if the back side of the wafer is sealed with an oxide layer such as a low-temperature oxide layer, the dispersed hydrogen does not react with the oxide layer sufficiently to generate pinholes in the layer or completely remove the oxide layer. When the device manufacturer wishes to etch or polish the surface and has only a thin layer of natural oxide, the hydrogen or hydrogen/hydrochloric acid mixture will typically completely remove the native oxide layer near the outer edge of the backside, with the cleaning gas spread around the wafer and When the etch is moved inward from the outer edge of the wafer, a pinhole opening is created in the native oxide layer that exposes the surface of the wafer. These pinhole openings typically form a ring or a π-cavity around the wafer. During the crystal deposition process, a small amount of helium-containing gas may also be scattered around the edge of the wafer between the wafer and the crystallizer and into the space between the wafer and the crystal seat. If the back side of the wafer is sealed by an oxide, the ruthenium film Nucleation and growth are substantially inhibited. In the pressure where the natural oxide layer is completely etched away by the cleaning gas, a smooth continuous layer of stone is grown. However, the cleaning gas has not completely removed the natural oxide layer and the pinhole has been exposed. When 矽, 矽 containing gas can be deposited 矽

O:\70\70781-960522.ptc 第6頁 1285936 案號 90110944 曰 修正 五、發明說明(3) 於針孔内, 膜。因此, 圓,在預烘 導致在背面 狀。此在晶 約0 . 5 // m及 等矽之隆起 會干涉機械 測晶圓之背 在蟲晶石夕 溫預烘焙及 外擴散通過 外擴散之摻 佈在晶圓邊 子會被包含 率的一致性 使用低溫氧 散。然而, 過程期間遭 面之不宜自 為了嚐試 為了消除背 JP11-16844 之氟化氫剝 額外加工步 並在磊晶沉積期間在晶圓後側上產生非均勻矽 對於僅具天然氧化物層之蝕刻或磨光背面之晶 培步驟期間,產生於天然氧化物層内之針孔會 上之不連續矽生長,其在亮光照明下出現模糊 圓背面上之模糊狀態或”空洞”係由具有直徑為 為約1 0 nm高之小矽生長或隆起物所構成。此 物散射光且導致模糊狀態可視為不宜,因為其 觀測及光學高溫測定系統,其在裝置加工時觀 面0 層之高溫生長期間所遭遇之另一問題為,在高 磊晶生長步驟期間,摻雜劑原子如硼或磷之間 半導體晶圓之背面。使用傳統晶座,自背面間 雜劑原子被截留在晶座與晶圓本身之間並可散 緣與晶座之間朝向晶圓之正面。此等摻雜劑原 且污染生長沉積層並惡化晶圓邊緣附近之電阻 。若半導體晶圓之背面被氧化物密封,例如, 化物時,摻雜劑原子實質上不會自背面向外擴 具有蝕刻或磨光背面之半導體晶圓在磊晶沉積 受摻雜劑原子自背面之向外擴散,其可導致正 動摻雜。 消除背面空洞及自動掺雜,已提出若干方法。 面空洞,Nakamura(日本未審查專利申請案 )揭不在晶圓裝入蠢晶反應以前’進行背面 除及/或高溫氫退火步驟高達1 0日。該法增加 驟,其會大大增加沉積過程之複雜性及成本。O:\70\70781-960522.ptc Page 6 1285936 Case No. 90110944 曰 Amendment V. Description of invention (3) Inside the pinhole, membrane. Therefore, the circle, which is pre-baked, results in a back shape. This lumps in the crystal of about 0.5 ohms and the like will interfere with the back of the mechanical wafer, and the pre-baking and out-diffusion of the smectite by the outer diffusion will be included in the wafer edge. Consistent use of low temperature oxygen dispersion. However, during the process, it is not advisable to attempt to eliminate the additional processing steps of the hydrogen fluoride stripping of JP11-16844 and to produce non-uniform enthalpy on the back side of the wafer during epitaxial deposition. For etching or grinding with only natural oxide layers. During the crystallizing step on the back side of the light, discontinuous enthalpy growth occurs on the pinholes in the natural oxide layer, which appears under the illumination of the blur on the back side of the blurred circle or the "void" is composed of a diameter of about It consists of a growth or bulge of 10 0 nm. This material scatters light and causes a hazy state to be considered unfavorable because of its observation and optical pyrometry system, another problem encountered during high temperature growth of the viewing layer during processing of the device is that during the high epitaxial growth step, A dopant atom such as boron or phosphorus is on the back side of the semiconductor wafer. With a conventional crystal holder, the dopant atoms from the back side are trapped between the crystal holder and the wafer itself and can be oriented toward the front side of the wafer between the aperture and the crystal holder. These dopants contaminate the deposited layer and degrade the resistance near the edge of the wafer. If the back side of the semiconductor wafer is sealed by an oxide, for example, the dopant atoms are not substantially extended from the back side, the semiconductor wafer having the etched or polished back surface is deposited by epitaxial deposition of dopant atoms from the back side. It spreads outward, which can lead to positive doping. Several methods have been proposed to eliminate back voids and autodoping. In the face of the hole, Nakamura (Japanese Unexamined Patent Application) discloses that the backside removal and/or high temperature hydrogen annealing steps are performed up to 10 days before the wafer is loaded into the stupid reaction. The addition of this method will greatly increase the complexity and cost of the deposition process.

O:\70\70781-960522.ptc 第7頁 1285936 案號 90110944 Λ_η 曰 修正 五、發明說明(4)O:\70\70781-960522.ptc Page 7 1285936 Case No. 90110944 Λ_η 曰 Correction V. Invention Description (4)

Deaton等人(美國專利5,960,555號)揭示一種藉利用具有 機内通道之晶座沿晶圓邊緣供導引洗滌氣體流至晶圓之邊 緣來防止正面之反應性源氣體散佈至晶圓背面之方法。此 法要求現存磊晶沉積室之實質修改並利用增加之洗滌氣體 流動,其可造成洗滌氣體溢出至正面並與源氣體混合,其 惡化所得蠢晶膜。 為了減少自動摻雜,Hoshi(日本未審查專利申請案 J P 1 1 - 8 7 2 5 0 )揭示在晶座之邊緣上使用真空吸入以抽空晶 座邊緣上之硼摻雜劑並防止自動摻雜。此法會影響晶圓邊 緣一致性及厚度且需要對現存磊晶沉積系統作實質修改。 Nakamura(日本未審查專利申請案JP10-223545)揭示一種 改良晶座,在晶座之邊緣上具有狹縫,使向外擴散之摻雜 劑原子會透過狹縫下推而進入廢氣中。此方法亦容許實質 量之沉積氣體被抽空在晶圓之背面下方,其可導致前述空 洞影響以及廢氣系統之過早腐蝕與安全問題。 因此,迄今為止,控制空洞對矽晶圓之背面的影響以及 在磊晶沉積過程期間與摻雜劑自背面之向外擴散相關之自 動摻雜問題之方法尚未令人滿意。因此,對在磊晶沉積過 程期間,解決矽晶圓前面之空洞影響及不宜自動摻雜之簡 單又成本低方式,在半導體工業中仍有需求。 發明之概述 因此,本發明之目的為設置改良晶座,其容許清潔氣體 實質上接觸半導體晶圓之整個背面;改良晶座之設置明顯 減少在磊晶矽生長期間半導體晶圓正面之自動摻雜;改良 晶座之設置容許在蠢晶沉積之預供培步驟期間自半導體晶 圓圓_画111 I iiiiliiiiii 圓 __1 1 圓圓國匯 O:\70\70781-960522.ptc 第8頁 1285936 修正 案號 90110944 五、發明說明(5) 圓之背面實 響;具有多 蠢晶晶圓具 在裝載期間 因此,簡 之裝置,其 大小及構型 口之密度為 晶圓呈一般 本發 晶層生 持半導 5開口 / 相對關 及晶圓 氣體入 本發 方法。 室,使 上背面 源氣體 以下 附圖之 明進 長在 體晶 公分 係以 之可 口與 明進 該方 氣體 以自 導入 將詳 簡單 質上完全移除天然氧化物且實質上消除空洞影 個孔之改良晶座之設置,使得使用晶座產生之 有改良品質;及改良晶座之設置可減少或消除 晶圓之π漂浮π 。 言之,本發明係關於一種用於化學氣相沉積法 中磊晶層生長在半導體晶圓上。裝置包含具有 供支持半導體晶圓之晶座。晶座之表面具有開 約0 . 2開口 /公分2與約4開口 /公分2之間,其與 平行相對關係以容許流體流過其間。 一步關於一種用於蠢晶沉積法之裝置,其中蟲 半導體晶圓上。裝置包含具有大小及構型供支 圓之晶座。晶座之表面具有開口之密度為約0. 2與約2開口 /公分2之間,其與晶圓呈一般平行 容許流體流過其間。裝置進一步包含支持晶座 旋轉構件、加熱元件、環繞晶座周邊之邊環及 氣體出口。 一步關於一種在半導體晶圓上生長磊晶矽層之 法包括將清潔氣體導入含有晶圓之磊晶沉積 平行於正、背面流動並接觸晶圓之正面及實質 表面除去天然氧化物層。在清潔氣體後,含石夕 沉積室内以在正面上生長磊晶矽層。 述本發明之其他目的及特性。 說明 圖1為圖2之線1 -1平面内所取之本發明改良晶座之截面 圖Deaton et al. (U.S. Patent No. 5,960,555) discloses the use of a wafer holder having an internal channel to direct a flow of scrubbing gas to the edge of the wafer along the edge of the wafer to prevent the front side of the reactive source gas from spreading to the wafer. The method of the back. This method requires substantial modification of the existing epitaxial deposition chamber and utilizes an increased flow of scrubbing gas which can cause the scrubbing gas to overflow to the front side and mix with the source gas, which deteriorates the resulting stupid film. In order to reduce the automatic doping, Hoshi (Japanese Unexamined Patent Application No. JP-A No. Hei No. No. Hei No. Hei No. Hei No. Hei No. 1 1 - 8 7 2 0 0) discloses the use of vacuum suction on the edge of a crystal holder to evacuate the boron dopant on the edge of the crystal seat and prevent automatic doping. . This method affects wafer edge uniformity and thickness and requires substantial modifications to existing epitaxial deposition systems. Nakamura (Japanese Unexamined Patent Publication No. JP-A No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei No. Hei. This method also allows a substantial amount of deposition gas to be evacuated below the backside of the wafer, which can cause the aforementioned void effects and premature corrosion and safety issues with the exhaust system. Thus, to date, methods for controlling the effects of voids on the backside of the wafer and the autodoping problems associated with the outward diffusion of dopants from the backside during the epitaxial deposition process have not been satisfactory. Therefore, there is still a need in the semiconductor industry for a simple and cost-effective solution to the effects of voids in front of germanium wafers and unsuitable for automatic doping during epitaxial deposition. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved crystal holder that allows the cleaning gas to substantially contact the entire back surface of the semiconductor wafer; the improved crystal holder arrangement significantly reduces the automatic doping of the front side of the semiconductor wafer during epitaxial growth The setting of the modified crystal seat is allowed from the semiconductor wafer circle during the pre-supply step of the stray crystal deposition_111 111 I iiiiliiiiii round __1 1 round country O:\70\70781-960522.ptc page 8 1285936 Case No. 90110944 V. Inventive Note (5) The back of the circle is real; there are many silly wafers during loading. Therefore, the device is simple, and the size and the density of the configuration port are the wafers. Hold semi-conducting 5 openings / relative off and wafer gas into the method. Room, the upper back source gas is as follows. The following figure shows the length of the crystal in the body of the common system, so that the gas is delicious and clear into the gas to completely remove the natural oxide from the introduction and substantially eliminate the hole The improved crystal seat arrangement provides improved quality using the crystal holder; and the improved crystal seat arrangement reduces or eliminates the π floating π of the wafer. In other words, the present invention relates to an epitaxial layer grown on a semiconductor wafer for use in a chemical vapor deposition process. The device includes a crystal holder having a semiconductor wafer for support. The surface of the crystal holder has an opening between about 0.2 cm/cm 2 and about 4 openings/cm 2 in parallel relation to allow fluid to flow therethrough. One step is directed to a device for stray deposition, in which a silicon semiconductor wafer is used. The device comprises a crystal holder having a size and configuration for the support circle. The surface of the crystal holder has an opening having a density of between about 0.2 and about 2 openings/cm 2 which is generally parallel to the wafer to allow fluid to flow therethrough. The apparatus further includes a support for the base rotating member, the heating element, a side ring surrounding the periphery of the base, and a gas outlet. One step in the process of growing an epitaxial layer on a semiconductor wafer includes introducing a cleaning gas into the wafer containing epitaxial deposition parallel to the front and back sides and contacting the front and back surfaces of the wafer to remove the native oxide layer. After the cleaning gas, the chamber is deposited in a stone chamber to grow an epitaxial layer on the front side. Other objects and features of the invention are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of the modified crystal seat of the present invention taken in the plane of line 1-1 of Fig. 2;

O:\70\70781-960522.ptc 第9頁 1285936 _案號90110944_年月日_i±±_ 五、發明說明(6) ' 圖2為本發明改良晶座之俯視圖。 圖3為磊晶反應室,顯示圖2之線1 - 1平面内所取之本發 明改良晶座之截面。 圖4為本發明改良晶座之截面圖。 圖5為本發明改良晶座之截面圖。 對應參考字母表示全部附圖之對應部份。 較佳具體例之詳細說明 根據本發明,傾發現在正面上具有磊晶矽層之高品質半 導體晶圓可利用裝有多個開口之改良晶座之磊晶沉積室製 成。有利的是,改良晶座實質上可消除在裝載期間之π漂 浮π且流體朝向並離開晶圓之背面運送,並容許磊晶沉積 法之預烘焙步驟使用之清潔氣體實質上接觸半導體晶圓之 整個背面且實質上以化學方式除去整個天然氧化物層,使 得在磊晶層之生長期間,當源氣體接觸半導體晶圓之背面 時,生長平滑連續矽層而在背面上之空洞影響實質上會減 少或消除。另外,改良晶座容許在磊晶沉積過程期間自晶 圓背面向外擴散之包含於半導體晶圓内之摻雜劑原子自洗 滌氣流内之晶圓正面帶走並進入廢氣中以防止實質量之摻 雜劑散佈在晶圓與晶座邊緣之間而接觸正面,導致正面之 不當自動摻雜。 現參照圖,特別是圖1 ,顯示有本發明改良晶座2之截面 圖。改良晶座2具有内環狀凸緣2 2,其可支持具有正面6與 背面8之半導體晶圓4。改良晶座2具有多孔表面9 ,具有多 個孔或開口 10, 11,12, 13, 14, 16及18與晶圓提升針孔21。 術語開口及孔此處可交換使用,且均指多孔表面9内之開O:\70\70781-960522.ptc Page 9 1285936 _ Case No. 90110944_年月日日_i±±_ V. Description of the invention (6) ' Fig. 2 is a plan view of the modified crystal seat of the present invention. Figure 3 is an epitaxial reaction chamber showing the cross section of the modified crystal holder of the present invention taken in the plane of line 1-1 of Figure 2. 4 is a cross-sectional view of a modified crystal seat of the present invention. Figure 5 is a cross-sectional view of a modified crystal seat of the present invention. Corresponding reference characters indicate corresponding parts of the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In accordance with the present invention, a high quality semiconductor wafer having an epitaxial layer on the front side is found to be formed by an epitaxial deposition chamber having a plurality of open modified crystal pads. Advantageously, the improved crystal holder substantially eliminates π floating π during loading and the fluid is transported toward and away from the back side of the wafer, and allows the cleaning gas used in the pre-baking step of the epitaxial deposition method to substantially contact the semiconductor wafer. The entire back side is substantially chemically removed from the entire native oxide layer such that during growth of the epitaxial layer, when the source gas contacts the back side of the semiconductor wafer, a smooth continuous layer of germanium is grown and the effect of voids on the back side is substantially Reduce or eliminate. In addition, the improved crystal holder allows dopant atoms contained in the semiconductor wafer to diffuse outward from the back side of the wafer during the epitaxial deposition process to be carried away from the front side of the wafer in the scrubbed gas stream and into the exhaust gas to prevent substantial mass. The dopant is interspersed between the wafer and the edge of the wafer to contact the front side, resulting in improper autodoping of the front side. Referring now to the drawings, and in particular to Figure 1, there is shown a cross-sectional view of an improved crystal holder 2 of the present invention. The modified crystal holder 2 has an inner annular flange 22 that supports the semiconductor wafer 4 having the front side 6 and the back side 8. The modified crystal holder 2 has a porous surface 9 having a plurality of holes or openings 10, 11, 12, 13, 14, 16 and 18 and a wafer lift pinhole 21. The terms opening and hole are used interchangeably herein and refer to the opening of the porous surface 9.

O:\70\70781-960522.ptc 第10頁 I285936 案號 90110944 曰 修正 五、發明說明(7) - 故通道。具有開口之多孔表面9直接位於半導體晶圓4下 方。本文所用之術語”多個,,意指二個或以上之孔。孔 1 〇, 1 1,1 2, 1 3, 1 4, 16及1 8在施加塗料前鑽入改良晶座2内。 在義晶沉積法之預烘培步驟期間,孔1 0,1 1,1 2,1 3,1 4,1 6 及1 8容許清潔氣體實質上接觸半導體晶圓4之整個背面8以 使清潔氣體反應,且實質上除去半導體晶圓4背面8上之所 有天然氧化物。與晶座2之内環狀凸緣2 2接觸之半導體晶 81 4之背面8部份實質上亦被清潔氣體蝕刻,因為氣體會散 ,在晶圓與晶座之間,導致實質上完全移除背面上之天然 氧^化物層。天然氧化物自背面8之移除明顯減少或消除在 半導體晶圓背面上之任何空洞影響,因為在磊晶生長過程 期間散佈在晶圓與晶座之間且接觸背面8之任何源氣體會 1顺利又連續地生長在矽表面之頂部上。孔丨〇,η,1 2,i 3, 2,1 6及1 8亦容許在磊晶沉積法之高溫清潔步驟及磊晶沉 '步驟期間自半導體晶圓4之背面8向外擴散之摻雜劑原子 過孔排入洗滌氣體或氫流内並離開半導體晶圓4之正面6 入排氣系統内。因此,可實現在磊晶沉積過程期間正面 之自動摻雜之顯著減少。 現參照圖2 ’顯示有内環狀凸緣2 2與具有多個孔之多孔 :面g 4之改良晶座2之俯視圖。多孔表面2 4上之晶圓提升 = ^28^0及32容許改良晶座2下方之提升針孔(圖未示)在 座m ί ί期3 t之後上升及下降半導體晶圓在改良晶 曰、、〃夢、二田、6環繞改良晶座2之周邊並在整個磊 S S】二:合谱I Ϊ保溫度橫過半導體晶圓之均勻性,使 μ又、,曰κ匕日日圓形成而不利影響沉積過程。邊環2 6O:\70\70781-960522.ptc Page 10 I285936 Case No. 90110944 修正 Amendment V. Invention Description (7) - Therefore channel. The porous surface 9 having an opening is directly below the semiconductor wafer 4. As used herein, the term "multiple," means two or more apertures. Holes 1 1, 1, 1, 2, 1 3, 1 4, 16 and 18 are drilled into the modified crystal holder 2 prior to application of the coating. During the pre-bake step of the deposition process, the holes 10, 1, 1, 2, 1 3, 1 4, 16 and 18 allow the cleaning gas to substantially contact the entire back surface 8 of the semiconductor wafer 4 for cleaning The gas reacts and substantially removes all of the native oxide on the back side 8 of the semiconductor wafer 4. The backside 8 portion of the semiconductor crystal 81 4 that is in contact with the annular flange 22 in the wafer holder 2 is also substantially etched by the cleaning gas. Because the gas will scatter between the wafer and the crystal holder, resulting in substantially complete removal of the natural oxide layer on the back side. The removal of the native oxide from the back side 8 is significantly reduced or eliminated on the back side of the semiconductor wafer. Any void effect, because any source gas that is interspersed between the wafer and the crystal holder and contacts the back surface 8 during the epitaxial growth process will smoothly and continuously grow on top of the crucible surface. Holes, η, 1 2 , i 3, 2, 16 and 18 also allow for the high temperature cleaning step and the epitaxial sinking step of the epitaxial deposition method The dopant atomic via which is diffused outward from the back surface 8 of the semiconductor wafer 4 is discharged into the scrubbing gas or hydrogen stream and exits the front surface 6 of the semiconductor wafer 4 into the exhaust system. Therefore, the epitaxial deposition process can be realized. There is a significant reduction in the automatic doping of the front side during the period. Referring now to Figure 2', there is shown a top view of the inner annular flange 22 and the modified crystal holder 2 having a plurality of holes: face g4. The crystal on the porous surface 24 Round lift = ^28^0 and 32 allow the improved pinhole under the modified crystal holder 2 (not shown) to rise and fall after the semiconductor m 3 t, and improve the wafer, the nightmare, the second field, 6 surrounds the periphery of the modified crystal holder 2 and is in the entire Lei SS. 2: The spectrum I guarantees the uniformity of the temperature across the semiconductor wafer, so that the formation of the μ, 曰 匕 匕 匕 yen adversely affects the deposition process. 2 6

1285936 案號 90110944 Λ_ 曰 修正 五、發明說明(8) ^ 通常具有直徑大於改良晶座2 4公分至約1 0公分並由具有 碳化矽或玻璃碳塗膜之高純度石墨所組成。 本發明之改良晶座可作成大小及構型,使晶座之内環狀 凸緣可適合任何直徑之半導體晶圓,包括例如,1 5 0毫 米,2 0 0毫米及3 0 0毫米晶圓。改良晶座可由傳統材料如高 純度石墨構成,並具有碳化矽或玻璃碳層覆蓋石墨以減少 在高溫磊晶沉積過程期間自石墨釋入周圍之污染物之量。 用以構成晶座之石墨通常為至少約9 9 %,更佳為至少約9 9 . 9 %,最佳為至少約9 9 . 9 9%純石墨。又,石墨較佳含有低於 約2 0 p p m全部金屬如鐵、顧、銅及鎳,更佳為低於約5 p p m全部金屬如鐵、鉬、銅及鎳。覆蓋石墨之碳化矽或玻 璃碳通常具有厚度為約7 5微米與約1 5 0微米之間,較佳為 約1 2 5微米。 直接位於半導體晶圓下方之改良晶座多孔表面内之孔較 佳為具有一直徑,使碳化矽或玻璃碳塗膜,若在孔已被鑽 入晶座後塗敷至晶座時,實質上不會阻隔或阻塞孔因而限 制流體流過其間。熟悉此技藝者當可明白,開口 ,通常指 為孔,可為方形、狹縫、鑽石形成任何容許流體流過其間 之其他形狀。開口較佳具有寬度為約0. 1毫米與約3毫米之 間,更佳為約0. 1毫米與約1毫米之間,最佳為約0. 5毫米 與約1毫米之間。若開口為圓形時,開口之寬度被界定為 開口或直徑之二個角落間之最大距離。孔隔開在改良晶座 上以容許在蠢晶沉積法之預供培步驟期間所用之清潔氣體 接觸且實質上蝕刻半導體晶圓之整個後表面。改良晶座孔 之隔開為約0. 5毫米與約4公分,更佳為約2毫米與約2公分1285936 Case No. 90110944 Λ_ 曰 Amendment V. Description of invention (8) ^ Usually has a diameter of more than 2 4 cm to about 10 cm of the modified crystal seat and consists of high-purity graphite with a tantalum carbide or glassy carbon coating. The improved crystal holder of the present invention can be sized and configured such that the annular flange within the crystal holder can be adapted to semiconductor wafers of any diameter, including, for example, 150 mm, 200 mm, and 300 mm wafers. . The modified crystal holder can be composed of a conventional material such as high-purity graphite and has a ruthenium carbide or glassy carbon layer covering the graphite to reduce the amount of contaminants released from the graphite during the high temperature epitaxial deposition process. The graphite used to form the crystal former is typically at least about 99%, more preferably at least about 99.9%, and most preferably at least about 99.9% pure graphite. Further, the graphite preferably contains less than about 20 p p m of all metals such as iron, gallium, copper and nickel, more preferably less than about 5 p p m of all metals such as iron, molybdenum, copper and nickel. The carbonized tantalum or glassy carbon covering the graphite typically has a thickness of between about 75 microns and about 150 microns, preferably about 1 25 microns. The hole in the porous surface of the modified crystal seat directly under the semiconductor wafer preferably has a diameter such that the tantalum carbide or glassy carbon coating film is applied to the crystal seat after the hole has been drilled into the crystal seat, substantially It does not block or block the holes and thus restrict fluid flow therethrough. As will be appreciated by those skilled in the art, the opening, generally referred to as a hole, can be square, slit, diamond, forming any other shape that allows fluid to flow therethrough. 5毫米之间之间之间之间。 The opening preferably has a width of between about 0. 1 mm and about 3 mm, more preferably between about 0. 1 mm and about 1 mm, preferably between about 0.5 mm and about 1 mm. If the opening is circular, the width of the opening is defined as the maximum distance between the two corners of the opening or diameter. The apertures are spaced apart on the modified crystal holder to permit contact with the cleaning gas used during the pre-feeding step of the doped deposition process and substantially etch the entire back surface of the semiconductor wafer. The spacing of the modified crystal seat holes is about 0.5 mm and about 4 cm, more preferably about 2 mm and about 2 cm.

O:\70\70781-960522.ptc 第12頁 1285936 案號 90110944 _η 曰 修正 五、發明說明(9) 之間,最佳為約6毫米與約1. 5公分之間,容 質上接觸半導體晶圓之整個背面,使其可自 上所有天然氧化物。晶座表面上開放面積之 晶座全部表面積之約0 . 5%與約4 %之間,更佳 面積之約1%與約3 %之間。晶座之表面較佳具 2孔/公分2與約4孔/公分2之間,更佳為約0.8 1 . 7 5孔/公分2之間。本文所用之密度意指均 度。 一般較佳的是,改良晶座之孔具有儘量小 讓碳化矽或玻璃碳塗膜限制流體透過孔流至 背面。若晶座内之孔被鑽得太大時,由背面 不均勻所造成之晶圓正面上之毫微表面狀態 改良晶座内之大直徑孔,藉位於半導體晶圓 透過背面之直接照射,可導致熱點或冷點在 面上之發展。此熱或冷點造成溫度級別,越 之正面形成並可在半導體晶圓之正面上導致 生長。磊晶層之不均勻生長明顯惡化晶圓之 座上之孔可在傾斜角度下鑽入晶座内以進一 加熱燈之直接照射及熱或冷點之形成導致正 磊晶生長之可能性,但仍容許氣體滲透晶座 容許向外擴散之摻雜劑原子自背面移走。為 熱或冷點之形成及因晶圓透過孔之直接照明 上溫度級別之產生以及減少或消除任何由提 之熱或冷點,可調整及調合在半導體晶圓上 燈之燈功率比以自燈產生平衡熱。 許清潔氣體實 背面蝕刻實質 全部百分比為 為晶座全部表 有密度為約0. 孔/公分2與約 勻或非均勻密 之直 半導 上局 問題 下方 半導 過半 不均 品質 步減 面上 並接 了進 在半 升針 、下 徑, 體晶 部化 會發 之加 體晶 導體 勻磊 〇改 少背 之不 觸背 一步 導體 孔所 方之 但不 圓之 溫度 生。 熱燈 圓背 晶圓 晶碎 良晶 面被 均勻 面且 減少 晶圓 造成 加熱O:\70\70781-960522.ptc Page 12 1285936 Case No. 90110944 _η 曰 Amendment 5, between the invention description (9), preferably between about 6 mm and about 1.5 cm, the capacitive contact semiconductor The entire back side of the wafer is made available from all natural oxides. The total surface area of the open area of the crystal seat on the surface of the crystal seat is between about 5% and about 4%, more preferably between about 1% and about 3%. The surface of the crystal holder preferably has between 2 holes/cm 2 and about 4 holes/cm 2 , more preferably about 0.8 1 .75 holes/cm 2 . The density used herein means mean. It is generally preferred that the aperture of the modified crystal holder be as small as possible so that the tantalum carbide or glassy carbon coating film restricts fluid flow through the aperture to the back side. If the hole in the crystal seat is drilled too large, the nanometer surface on the front side of the wafer caused by the unevenness of the back surface improves the large diameter hole in the crystal seat, and the direct irradiation of the semiconductor wafer through the back surface can be Lead to the development of hot spots or cold spots on the surface. This hot or cold point causes a temperature level that is formed on the front side and can cause growth on the front side of the semiconductor wafer. The uneven growth of the epitaxial layer significantly deteriorates the hole in the wafer can be drilled into the crystal seat at an oblique angle to directly irradiate the heating lamp and the formation of hot or cold spots leads to the possibility of positive epitaxial growth, but The gas permeable crystal holder is still allowed to allow the outward diffusion of dopant atoms to be removed from the back side. For the formation of hot or cold spots and the generation of temperature levels due to direct illumination of the through-wafer vias and the reduction or elimination of any heat or cold spots, the lamp power ratio of the lamps on the semiconductor wafer can be adjusted and adjusted. The lamp produces a balanced heat. The actual percentage of the backside etching of the cleaning gas is that the density of the crystal holder is about 0. The hole/cm 2 is approximately uniform or non-uniformly dense. The semi-conducting problem is below the semi-conducting half-inferior quality step-down surface. And in the half-lift needle, the lower diameter, the body-shaped part of the crystal will be added to the body-shaped crystal conductor to tamper with less back without touching the one-step conductor hole but not the temperature of the temperature. Heat lamp round back wafer crystallized fine surface is evenly surfaced and reduces wafer heating

O:\70\70781-960522.ptc 第13頁 1285936 _案號90110944_年月曰 修正_ 五、發明說明(10) _ 本發明之改良晶座可用作化學氣相沉積法如磊晶沉積法’ 之裝置的部份。現參照圖3,顯示有在使用本發明之改良 晶座3 6之磊晶生長過程期間所用之磊晶反應室3 4。改良晶 座3 6接附至可旋轉支持構件5 8及5 9且具有大小及構型以在 磊晶沉積過程期間支持内環狀凸緣42上之半導體晶圓38。 半導體晶圓3 8與改良晶座3 6之多孔表面4 9内之孔 4 4,4 5,4 6,4 7,4 8,4 9及5 1呈隔開關係。提升針孔6 2容許提 升針(圖未示)透過改良晶座3 6之外孔表面9接達至半導體 晶圓3 8,使半導體晶圓3 8會在磊晶沉積過程前、後升起及 離開改良晶座3 6。屋晶沉積室3 4亦含有燈陣列5 0,5 2,分 別位於改良晶座3 6之上、下方供磊晶沉積過程期間之加熱 用。氣體入口 5 4,5 6容許在磊晶沉積過程之預烘焙步驟期 間清潔氣體之導入,使清潔氣體導入半導體晶圓3 8之上、 下方以加強半導體晶圓3 8之正面6 0與背面6 2之天然氧化物 之移除。在磊晶生長步驟期間,氣體入口 5 4導入含矽源氣 體,其流動在晶圓3 8上方,氣體入口 5 6導入氫或惰性氣體 在晶圓3 8下方以沖洗半導體晶圓3 8之背面6 2並自正面帶走 向外擴散之摻雜劑原子。如圖3所示,射入蠢晶沉積室之 氣體平行於半導體晶圓之正、背面流動。該流動型式容許 注射之氣體接觸正面並透過晶座表面内之孔渗透晶座以接 觸晶圓之背面。因為氣體平行於半導體表面而非垂直流 動,所以半導體晶圓係由散佈在晶圓邊緣與環狀凸緣邊緣 間且變成變形之氣體提升離開環狀凸緣之可能性明顯減少 或消除。自氣體入口 5 4,5 6導入室3 4之氣體係透過排氣口 64自室34移除。O:\70\70781-960522.ptc Page 13 1285936 _ Case No. 90110944_年月曰曰 Revision _ V. INSTRUCTION DESCRIPTION (10) _ The improved crystal seat of the present invention can be used as a chemical vapor deposition method such as epitaxial deposition Part of the device of the law. Referring now to Figure 3, there is shown an epitaxial reaction chamber 34 for use during the epitaxial growth process using the improved crystal holder 36 of the present invention. The modified pedestal 36 is attached to the rotatable support members 58 and 59 and is sized and configured to support the semiconductor wafer 38 on the inner annular flange 42 during the epitaxial deposition process. The semiconductor wafer 38 is spaced apart from the holes 4 4, 4 5, 4 6, 4 7, 4 8, 4 9 and 5 1 in the porous surface 49 of the modified crystal holder 36. The lifting pinhole 6 2 allows the lifting pin (not shown) to pass through the outer hole surface 9 of the modified crystal seat 36 to the semiconductor wafer 3, so that the semiconductor wafer 38 rises before and after the epitaxial deposition process. And leave the modified crystal seat 3 6 . The house crystal deposition chamber 34 also contains a lamp array 50, 52, which is located above and below the modified crystal holder 36 for heating during the epitaxial deposition process. The gas inlets 5 4, 5 6 allow the introduction of the cleaning gas during the pre-baking step of the epitaxial deposition process, and the cleaning gas is introduced above and below the semiconductor wafer 38 to strengthen the front surface 60 of the semiconductor wafer 38 and the back surface 6 2 removal of natural oxides. During the epitaxial growth step, the gas inlet 54 is introduced with a helium-containing gas flowing over the wafer 38, and the gas inlet 56 is introduced with hydrogen or an inert gas under the wafer 38 to rinse the back of the semiconductor wafer 38. 6 2 and from the front side to the external diffusion of dopant atoms. As shown in Fig. 3, the gas injected into the stray deposition chamber flows parallel to the front and back sides of the semiconductor wafer. The flow pattern allows the injected gas to contact the front side and penetrate the crystal holder through the holes in the surface of the wafer holder to contact the back side of the wafer. Because the gas flows parallel to the semiconductor surface rather than vertically, the semiconductor wafer is significantly reduced or eliminated by the possibility of gas that is interspersed between the edge of the wafer and the edge of the annular flange and that is deformed away from the annular flange. The gas system from the gas inlet 5 4, 5 6 into the chamber 34 is removed from the chamber 34 through the exhaust port 64.

O:\70\70781-960522.ptc 第14頁 1285936 案號 90110944 Λ_η 曰 修正 五、發明說明(11) . 改良晶座内之孔將容許清潔氣體通過改良晶座且在清潔 步驟期間實質上接觸半導體晶圓之整個背面,使任何呈現 在背面上之天然氧化物會被清潔氣體除去。此天然氧化物 自背面之移除將容許平滑連續磊晶矽層生長在半導體晶圓 背面之任何部份上,在磊晶層之生長期間,其係與源氣體 接觸,因而實質上會消除任何空洞在背面上之形成。另 外,改良晶座内之孔將容許惰性氣體或氫氣接觸晶圓之背 面,使在清潔步驟與磊晶生長步驟期間自背面向外擴散之 摻雜劑原子會自半導體晶圓帶走而進入廢氣中,因而實質 上減少自動摻雜晶圓正面之可能性。 含有上述本發明之改良晶座之磊晶反應室可用於外延沉 積法之清潔與生長步驟。在一種根據本發明之磊晶沉積法 中,磊晶矽層生長在半導體晶圓之正面上。在本發明之一 較佳具體例中,矽晶圓在周圍壓力下導入磊晶沉積室内, 而清潔氣體如氫氣或氫氣與鹽酸之混合物在溫度為約1 0 0 0 °C與約1 3 0 0 °C下,流速為約1升/分鐘與約5 0升/分鐘之 間,較佳為約1 0升/分鐘與約20升/分鐘之間,導入室内至 少約1 0秒以除去半導體晶圓之正、背面上之天然氧化物 層。 一旦天然氧化物層自半導體晶圓之正、背面除去時,中 斷清潔氣體而將反應室内之溫度調整至約6 0 0 °C與約1 2 0 0 °c之間,含矽源氣體如矽烷或二氯矽烷,例如,在流速為 約1升/分鐘與約20升/分鐘之間,導入半導體晶圓之正面 上方一段時間,足以生長磊晶矽層在具有厚度為約0. 1與 約2 0 0微米之間,較佳為約1與約1 0 0微米之間之半導體晶O:\70\70781-960522.ptc Page 14 1285936 Case No. 90110944 Λ_η 曰 Amendment 5, Invention Description (11). Improvement of the hole in the crystal seat will allow the cleaning gas to pass through the modified crystal seat and substantially contact during the cleaning step The entire back side of the semiconductor wafer is such that any natural oxide present on the back side is removed by the cleaning gas. The removal of this native oxide from the back side will allow a smooth continuous epitaxial layer to be grown on any portion of the back side of the semiconductor wafer, which is in contact with the source gas during growth of the epitaxial layer, thus essentially eliminating any The formation of a void on the back. In addition, the holes in the modified crystal holder will allow the inert gas or hydrogen to contact the back side of the wafer, so that the dopant atoms diffused outward from the back surface during the cleaning step and the epitaxial growth step will be carried away from the semiconductor wafer into the exhaust gas. Medium, thus substantially reducing the likelihood of automatically doping the front side of the wafer. An epitaxial reaction chamber containing the above-described improved crystal holder of the present invention can be used for the cleaning and growth steps of the epitaxial deposition method. In an epitaxial deposition process in accordance with the present invention, an epitaxial layer is grown on the front side of a semiconductor wafer. In a preferred embodiment of the invention, the germanium wafer is introduced into the epitaxial deposition chamber at ambient pressure, and the cleaning gas such as hydrogen or a mixture of hydrogen and hydrochloric acid at a temperature of about 1000 ° C and about 1 30 At 0 ° C, the flow rate is between about 1 liter / minute and about 50 liter / minute, preferably between about 10 liter / minute and about 20 liter / minute, and introduced into the chamber for at least about 10 seconds to remove the semiconductor. A natural oxide layer on the front and back of the wafer. Once the natural oxide layer is removed from the front and back sides of the semiconductor wafer, the cleaning gas is interrupted and the temperature in the reaction chamber is adjusted to between about 60 ° C and about 1 20 ° C, containing a helium source gas such as decane. Or the thickness of the epitaxial layer is about 0.1 Å and 约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约约A semiconductor crystal between 200 μm, preferably between about 1 and about 100 μm

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—案號 90110944 五、發明說明(12) 圓的正面上。同時,含矽源氣體導入半導 之沉積室内,氣體如氮、氬、氫、其混合物f :上方 k速為約1升/分鐘與約50升/分鐘之間,較佳氣原乳體,在 鐘與約20升/分鐘之間,導入在半導體晶圓之升/分 使洗滌氣體可接觸半導體晶圓之背面並自背嫌下方’ 散之摻雜劑原子朝向排放出口。此較佳具體二^ =外擴 消除任何背面空洞效應並使正面之自動摻雜降1 f,少或 然較佳蟲晶沉積法係在周圍壓力下實施,但 三雖 沉積法亦在本發明之範圍内。 予氣相 在本發明之替代具體例中,改良晶座可作成大 以容許半導體晶圓直接停留在多孔表面上,因而消^^ 狀凸緣2 2,如圖1所示。現參照圖4,顯示有一改良曰 嶮 截面,其中半導體晶圓直接停留在多孔表面上。之 圓70之背面76直接座落在改良晶座74之多孔表面72上體^ 然晶圓70之背面76直接接觸多孔表面72,但流在改良曰^ 74下方之氣體可透過孔78, 80, 8 2, 8 4, 8 6, 8 8及9〇滲透/ 表面7 2且實質上接觸晶圓7 0之整個背面7 6。 在另一替代具體例中,可進一步改良圖4所示之本發明 改良晶座,使多孔表面7 2為盤形或圓頂形以容許僅半導體 晶圓之外緣接觸改良晶座。現參照圖5,顯示有改良晶座 之截面,其中半導體晶圓直接停留在晶座之多孔表面上。 半導體晶圓7 0之背面7 6直接座落在改良晶座7 4之多孔表面 7 2上。多孔表面7 2之形狀如同盤或圓頂,使半導體晶圓7 〇 之外緣9 2, 9 4直接接觸多孔表面72而背面76或晶圓70之其 餘部份則未直接接觸孔多表面7 2。在使用期間,孔7 8,8 0,- Case No. 90110944 V. Description of invention (12) On the front side of the circle. At the same time, the helium-containing gas is introduced into the semi-conducting deposition chamber, and the gas such as nitrogen, argon, hydrogen, and the mixture f thereof has an upper k-speed of between about 1 liter/min and about 50 liter/min, preferably a gas original emulsion. Between the clock and about 20 liters/minute, the liters/mins introduced into the semiconductor wafer are such that the scrubbing gas can contact the back side of the semiconductor wafer and from the underside of the dopant dopant atoms toward the discharge outlet. Preferably, the external expansion eliminates any back cavity effect and reduces the automatic doping of the front side by 1 f. The preferred method is to perform the system under ambient pressure, but the deposition method is also in the present invention. Within the scope. Pre-gas phase In an alternative embodiment of the invention, the modified crystal holder can be made large to allow the semiconductor wafer to directly reside on the porous surface, thereby eliminating the flange 22, as shown in FIG. Referring now to Figure 4, there is shown a modified crucible section in which the semiconductor wafer resides directly on the porous surface. The back side 76 of the circle 70 is directly seated on the porous surface 72 of the modified wafer holder 74. The back side 76 of the wafer 70 directly contacts the porous surface 72, but flows through the gas permeable aperture 78, 80 below the modified 曰^74. , 8 2, 8 4, 8 6, 8 8 and 9 〇 penetration / surface 7 2 and substantially contact the entire back surface 7 of the wafer 70. In another alternative embodiment, the improved crystal holder of the present invention shown in Figure 4 can be further modified such that the porous surface 72 is disk-shaped or dome-shaped to permit only the outer edge of the semiconductor wafer to contact the modified crystal holder. Referring now to Figure 5, there is shown a cross section of an improved crystal holder in which the semiconductor wafer resides directly on the porous surface of the crystal holder. The back surface 71 of the semiconductor wafer 70 is directly seated on the porous surface 71 of the modified crystal holder 74. The porous surface 72 is shaped like a disk or dome such that the outer edge 9 2, 94 of the semiconductor wafer 7 is in direct contact with the porous surface 72 and the back portion 76 or the remainder of the wafer 70 is not in direct contact with the multi-surface 7 2. During use, holes 7 8,8 0,

O:\70\70781-960522.ptc 第16頁 1285936 案號 90110944 曰 修正 五、發明說明(13) * 8 2,8 4,8 6,8 8及9 0容許流體流過其間至晶圓之背面。 熟悉此技藝者當可明白,本發明之改良晶座可與各種沉 積反應器包括桶式、薄餅式及迷爾分批式反應器使用而與 所用之晶座之形狀無關。 鑒於上述,可知可達到本發明之若干目的。因為在不脫 離本發明之範圍以外可對上述改良晶座作各種改變,所以 希望是上述所包括之所有事物均闡明為例示性而非限制 性。O:\70\70781-960522.ptc Page 16 1285936 Case No. 90110944 曰Revision 5, Invention Description (13) * 8 2,8 4,8 6,8 8 and 90 allow fluid to flow through to the wafer back. It will be apparent to those skilled in the art that the improved crystal holder of the present invention can be used with a variety of deposition reactors, including barrel, pancake, and micro-batch reactors, regardless of the shape of the wafer holder used. In view of the above, it will be appreciated that several objects of the invention are attained. Since the above-described modified crystal holders can be variously modified without departing from the scope of the invention, it is intended that all of the above-described aspects be construed as illustrative and not limiting.

O:\70\70781-960522.ptc 第17頁 1285936 案號 90110944 Λ_ 曰 修正 圖式簡單說明 主要元件符號說明 2, 36, 74 4, 38, 70 6, 60 8, 62, 76 9,24,49,72 改良晶座 半導體晶圓 正面 背面 多孔表面 10, 11,12, 13, 14, 16, 18, 44, 45, 46, 47, 48, 49, 51,78, 80, 8 2, 8 4, 8 6, 8 8, 9 0 孔/ 開口 21,2 8, 3 0, 3 2, 6 2 22,42 晶圓提升針孔 内環狀凸緣 26, 40 34 58 50 54 64 92,94 邊環 59 52 56 蟲晶反應室 可旋轉支持構件 加熱燈陣列 氣體入口 排氣口 外緣O:\70\70781-960522.ptc Page 17 1285936 Case No. 90110944 Λ _ 曰 Correction diagram Simple description of the main components Symbol Description 2, 36, 74 4, 38, 70 6, 60 8, 62, 76 9,24, 49,72 modified wafer semiconductor wafer front and back porous surface 10, 11,12, 13, 14, 16, 18, 44, 45, 46, 47, 48, 49, 51,78, 80, 8 2, 8 4 , 8 6, 8 8, 9 0 hole / opening 21,2 8, 3 0, 3 2, 6 2 22,42 Wafer lifting pinhole inner flange 26, 40 34 58 50 54 64 92,94 side Ring 59 52 56 insect crystal reaction chamber rotatable support member heating lamp array gas inlet exhaust rim

O:\70\70781-960522.ptc 第18頁O:\70\70781-960522.ptc Page 18

Claims (1)

1285936 _案號90110944 X年0月#日 修正_ 六、申請專利範圍 ’ 1 · 一種在一半導體晶圓上生長一磊晶矽層之方法,該半’ 導體晶圓具有一正面與一背面,該方法包含: 將清潔氣體導入含有半導體晶圓之磊晶沉積室内,使 清潔氣體平行於正面與背面流過並接觸半導體晶圓之正面 及半導體晶圓之實質上整個背面,以自半導體晶圓之正面 與背面除去一天然氧化物層;及 將一含石夕源氣體導入蠢晶沉積室以在半導體晶圓之正 面上生長蠢晶石夕層,同時將洗務氣體導入蠢晶沉積室内以 自半導體晶圓之正面除掉半導體晶圓背面之間外擴散的摻 雜劑原子。 2.根據申請專利範圍第1項之方法,其中磊晶層為約在 0 . 1微米與2 0 0微米厚之間。 3 .根據申請專利範圍第1項之方法,更進一步包括當導 入該清潔氣體進入該沉積室中時,利用一晶座支持該半導 體晶圓。 4. 根據申請專利範圍第1、2或3項之方法,更進一步包 括當導入該含矽源氣體及洗滌氣體進入該沉積室時,利用 一晶座支持該半導體晶圓。 5. 根據申請專利範圍第1、2或3項之方法,更進一步包 括利用一晶座支持該半導體晶圓且允許清潔氣體及洗滌氣 體透過晶座其中之複數個孔滲透晶座以接觸晶圓之背面。 6. 根據申請專利範圍第1、2或3項之方法,其中該清潔 氣體包含氫氣且該清潔氣體在溫度約為1 0 0 0 °C與約1 3 0 0 °C 之間導入該沉積室内。1285936 _ Case No. 90110944 X Year 0 Month #日修正_ Six, application patent range '1 · A method of growing an epitaxial layer on a semiconductor wafer, the semi-conductor wafer has a front side and a back side, The method comprises: introducing a cleaning gas into an epitaxial deposition chamber containing a semiconductor wafer, and flowing the cleaning gas parallel to the front and back surfaces and contacting the front surface of the semiconductor wafer and substantially the entire back surface of the semiconductor wafer from the semiconductor wafer Removing a natural oxide layer from the front side and the back side; and introducing a stone-containing source gas into the stray crystal deposition chamber to grow a stucco layer on the front side of the semiconductor wafer, and introducing the cleaning gas into the stray crystal deposition chamber The dopant atoms that are externally diffused between the back side of the semiconductor wafer are removed from the front side of the semiconductor wafer. 2. The method of claim 1, wherein the epitaxial layer is between about 0.1 micron and 200 microns thick. 3. The method of claim 1, further comprising supporting the semiconductor wafer with a wafer holder when the cleaning gas is introduced into the deposition chamber. 4. The method of claim 1, 2 or 3, further comprising supporting the semiconductor wafer with a wafer holder when the helium-containing gas and the scrubbing gas are introduced into the deposition chamber. 5. The method of claim 1, 2 or 3, further comprising supporting the semiconductor wafer with a crystal holder and allowing the cleaning gas and the scrubbing gas to pass through the plurality of holes of the crystal holder to penetrate the crystal holder to contact the wafer The back. 6. The method of claim 1, 2 or 3, wherein the cleaning gas comprises hydrogen and the cleaning gas is introduced into the deposition chamber at a temperature of about 1000 ° C and about 130 ° C. . O:\70\70781-960522.ptc 第19頁 1285936 _案號90110944_年月日 修正_ 六、申請專利範圍 7. 根據申請專利範圍第6項之方法,其中該清潔氣體係 在流速約1升/分鐘與約5 0升/分鐘之間被導入。 8. 根據申請專利範圍第7項之方法,其中該清潔氣體導 入該沉積室中之時間至少約1 0秒。 9 ·根據申請專利範圍第1、2或3項之方法,更進一步包 括以一晶座之内環狀凸緣支持該半導體晶圓。 1 0 .根據申請專利範圍第9項之方法,其中該半導體晶圓 之支持係包括晶座内之複數個孔以隔開關係支持該半導體 晶圓。O:\70\70781-960522.ptc Page 19 1285936 _ Case No. 90110944_年月日日 Revision _ 6. Patent application scope 7. According to the method of claim 6, wherein the cleaning gas system has a flow rate of about 1 Liters/minutes are introduced between approximately 50 liters/minute. 8. The method of claim 7, wherein the cleaning gas is introduced into the deposition chamber for at least about 10 seconds. 9. The method of claim 1, 2 or 3, further comprising supporting the semiconductor wafer with a ring-shaped inner flange. The method of claim 9, wherein the support of the semiconductor wafer comprises a plurality of holes in the crystal holder to support the semiconductor wafer in spaced relationship. O:\70\70781-960522.ptc 第20頁O:\70\70781-960522.ptc Page 20
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US20010037761A1 (en) 2001-11-08
US6444027B1 (en) 2002-09-03
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CN1223709C (en) 2005-10-19
US6596095B2 (en) 2003-07-22
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EP1287187B1 (en) 2009-06-17
WO2001086034A2 (en) 2001-11-15
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KR100784001B1 (en) 2007-12-07
WO2001086034A3 (en) 2002-02-21

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