1285426 九、發明說明： 【發明所屬之技術領域】 人本發明係有關於一種晶片與被動元件埋入基板之整 5、、、σ構，尤扣一種半導體晶片與被動元件兩者皆埋入 件之半導體整合結構。 ^【先前技術】 由於半導體製程之進步，以及半導體晶片上電路功能 2不斷提昇，使得半導體裝置之發展走向高度集積化’目 則以球柵陣列式（BGA)封裝結構及覆晶球栅陣列式 (FCBGA)封裝結構，逐漸取代傳統以導線架（Lead frame) 為主之半導體裝置，該球栅陣列式半導體裝置於相同單位 %内得有U之輸出/輸人連接端，以容納更多之帝 電路及半導體晶片接置其上。 电 I·隹半‘體裝置之集積化，封裝構造之接腳數 =而由於接腳數目與線路佈設之增多，導致雜訊亦： | 壯-因此’―般為消除雜訊或作電性補償，係於半導 、二，加入被動元件’如電阻元件、電容元件與電 片二除雜訊與穩定電路’藉以使得所封裝之半導 體日日片付合電性特性之要求。 之恭m1，所示’為配合現今高密度多晶片模組化 FrC 0式球柵陣列㈣P-⑶P Ban Grid Array, FCBGA)半導體封裝件係 與球柵陣列之封裝結構主=同時具有覆晶 數個凸持咖^苒使日曰片11的主動面1U可藉由複 ▲ 〇 ef BUmps)電性連接至封裝基板 18180 5 1285426 13(Substrate)表面13a上’此夕卜，該封震基板i3表面… 則可再依設計的需要另外形成至少—被動元件i4，並於該 封裝基板13之另一表面植設複數個作為輸入/輸出_ = 之銲球15(SolderBall)。此-連接結構可大幅縮減體卜而 同時亦免除習知打線（Wire bond)之設計，而可降低阻貝广提 昇電性，以避免訊號於傳輸過程中衰退，因此已 几 與電子元件的封裝主流技術。 …θθ . 然而習知覆晶式球栅陣列係將晶片u及被動元件Μ 接置在封裝基板13的外部，#因電路設計的需要，於該封 裝基板13表面必須接置相當數量的被動元件14，則'因^皮 動元件14的數量增加，而佔用較多的電路面積，使得封裝 基板13的面積增加，如此即無法達到縮小體積之目的。又 在封裝基板13的表面接置數量眾多的被動元件14，若封 ，基板13所能提供的面積有限，因此不利於高密度封裝 高密度組裝。 、 丨再者，電路板的線路佈局（lay〇ut)若排列不當，則會導 致不必要的寄生阻抗（parasitic ⑽CC)，如寄生電阻 (parasitic resistance)的形成是從零件到零件的走線結果， 而寄生電容（parasitic capacitance)可能因走線、桿點以及平 行走線所產生，又寄生電感（parasitic induct⑽α)的產生則 因周邊形成的回路造成電感及互感應。而寄生阻抗對於訊 號的傳送會造成不良的影響，導致訊號傳輪缺乏完整性 (Integrity)，即訊號中含有雜訊（n〇ise)，而影響訊號傳送 正確性。 18180 6 1285426 …該被動元件14係接置在封裝基板13外部的表面 S亥被動元件14連接的線路延伸至封f其 走線太長使得雜％及…部，而因 于“及阻抗增加，使電氣特性之提昇受到限 制0 =卜，請參閱第2圖，上述之半導體封料之晶片η 後，則完成之封裝件又必 "在尸刷電路板 2Uprinted circuit board, pCB)上 = : = 21表面亦同樣需設置複數被動元件以供 【發明内容】^在衣私上相虽繁複而增加製造成本。 鑒於上述習知技術之缺點，本發明之 一種晶片與被動元件埋入美柘之效人&描^的係棱众 裝置内被動元件之佈設數=:: :佈， 里並$曰加線路佈局的靈活性。 Χ之另目的係提供一種晶片與被動元件埋入 基板之整合結構，俾縮減半導體裝置使 ^ •體裝置輕薄短小之目標。 償 乂違+¥ 美；二目的係提供-種晶片與被動元件埋入 Π二:構，讓半導體晶片與被動元件直接電性連 • ，^ 接線長度，減少阻抗並提升電氣特性。 本發明之再—目1 基板之整合結構，！^以將=一種晶片與被動元件埋入 整合於-體，提高;载二被動元件及承載件 度以及簡化製程步驟，降低封裝之亚有效^集積 為達上揭及其它Η ώΑ , 9 ’本％明之晶片與被動元件埋入 18180 7 1285426 基板之整合結構，主要係包括一承載件；至少 數=連接塾之半導體晶片，係接置於該承載件上；= 電層’係形成於該承載件上，且覆蓋該半導體晶片. 線路層，係形成於該介電層上，且該線心：藉由 複數牙過該介電層之導電結構以電性連接至該 之電性連接墊，其中，至少一導+ έ 、曰曰片 V私、、、口構與黾性連接墊間形 成有被動元件材料藉以構成被動元件。 此外，本發明之晶片與被動元件埋人基板之整合結 ’使可包括形成於該介電層及線路層上之線路士 :線:Γ增層結構係包含有介電層、形成於該介電:上 導:;ΓΓ介電層中而提供線路層作層間電 孔以電性連接至該線路層，其中至少 亡目 間係形成有被動元件材料以形成所需之被動二1。、線路層 目此’本發明之W與被動元件埋 ，係將半導體晶片接置於承載件 反之正口、、、口構 吉姑山4丄4 f戰件上，亚嵌埋於介電層中，再 直接由该半v體晶片主動面上之 伸，且於部分該電性連㈣ 2接f向外作線路延 料以形成所需之被動元件有被動元件材 性連接’且於該增層線路結構中之線= 亦了於$電盲孔與線路声 — 被動元件枯·山U 成 件材料’俾藉由將 皮動7G件材科鑲肷至線路間，並 昇半導體裳置内被動元件之佈設數合而= 額外於裝置表面增設被動^ 功此，而世需 被動70件’以增加整體線路佈局靈活 18180 1285426 Τ’*亚可縮減使用面積，以達半導體裴置輕薄短小之目標， 同時，亦因本發明係將被動元件鑲嵌於半導體晶片之電性 連^墊上與層間線路間，遂可因此縮短被動元件與晶片間 •之兔性傳輸距離，藉以避免因傳輸距離過長所產生之雜訊 •干擾及電性不佳問題。 【實施方式】 上為使本發明之目的、特徵及功效’能更進一步的瞭解 •共⑽同’兹*供下述實施方式，配合詳細揭露及圖式詳加 說明如后。當,然，本發明可以多種形式實施之，以下所述 係為本發明之較佳實施例，而非用以限制本發明之範圍， 合先敘明。 請參閱第3圖，係顯示本發明之晶片與被動元件埋入 基板之整合結構的第一實施例。該整合結構係包括有一承 載件3〇,該承載件30復可包括第一承載板3〇〇及第二承 載板301 ’第二承載板3〇1具有貫穿開孔，該承載件 験30材料可為金屬，如具高導熱性的銅，或陶兗、有機絕緣 層，亦或為已形成有線路之電路板，其中，該第一、第二 承載板300、301之材質係可相同或不㈣，且該第一、第 二承載板300、301之厚度可視需要而定。其係將半導體晶 片304以導熱黏著層3〇3接置於第二承載板貫穿開孔 302内之第一承載板3〇〇上，並在半導體晶片3〇4及承載 件30上覆有一介電層3〇8，該介電層係可部分填入第二承 載板301與半導體晶片3〇4間之間隙以固定該晶片3⑽， 及在該介電層308上形成有線路層3〇9，且該線路層 18180 9 1285426 藉由，過該介電層3〇8之導電結構3〇6(例如為導電 目子）以電性連接至該+導體晶片3G4之電性 其中，藉由該承載件3〇、介^ > 3Q8、+ -線路層309形成一半導# ^導體晶片304與 成·^體曰曰片304埋入基板之整合結構， .材：：Γ”:冓306與電性連接墊305間形成有被動元件 = 30^。雨述有關半導體晶片3〇4與承載板間之固定關 展’於貝把時弟—承載板3〇〇於材料選擇時亦 _層3㈣樣為含樹脂類之材f，可於壓合 第^ 載板3G1與半導體晶片304間之間隙。 …弟一承 線路# 3:9 f正口、構復可包含有形成於該介電層308及 、勺1 之線路增層結構31，該線路增層結構31係 匕括’I電層310、形成於該介電層31〇上之線路層如、以 及形成於該介電層3ΐ〇φ 4^ θ λ 接之導中 線路層311作層間電性連 e、Η ，俾供該線路增層結構31藉&複數導命 盲孔312以電性連接至該線路層309。其中至少 ^ 312與線路層_間係得形成有被動元件材料3〇7: 成所需之被動元件。 了十川/以形 〜元件材料3〇7可選擇為電阻材料或電容材料。 =阻材料可為選自鎳鉻⑽心）、鎳填（Ni_p)、錄錫 ㈣必A1)、及氮化鈦⑽)合金所組成之 粉末埴充之高分=為局分子材料、陶咖、陶莞 之—者所構成。相似物之混合物所組成組群之其中 該線路增層結構31外表面可形成有防焊 18180 10 1285426 复數開σ以外露出部分線路，俾於其上植 31611球、導電凸塊或金屬焊塾等導電元件 過心收納於該承載件30之該半導體晶片3〇4透 ==生連接墊3〇5、導電結構3。6、線路層·、 。路θ層、、、σ構3 1之線路、以及導電 外部裝置。 乂及件316以電性連接至 此外，在本發明之第二實施例中， 亦可如第4圖所示為 料U冓 式陥言甘a 狀 其材質可為如銅之金屬 Ϊ 半導體晶片楊以導熱黏著層_接置;^ 承載件40上，並在 考層403接置於 少一介恭#伽广體曰曰片4〇4及承載件4〇上覆有至 且1魂腺^ 4Π及在5亥介電層4〇8上形成有線路層409， 傷m9係藉由複數穿過該介電層4〇8之導電結構 性遠:二孔)以電性連接至該半導體晶片4〇4之電 介Ϊ = 8 其中，藉由該承載件40、半導體晶片4。4、 二：：與線路層4。9形成一半導體晶片4。4埋入基板 形成有被動元件材料40^、、、°構4〇6與電性連接塾他間 另外’祕合結構復可包含有形成於該介電層4 線路層409上之線路增層結構41，該線路增層士士構 包括：電層⑽、形成於該介電層41。上之線路；Mb以 41()中而提供線路層4ιι作層間電 :==12’俾供該線路增層結構41藉由複數導電 § 电！·連接至该線路層4〇9。其中至少一亡 孔412與線路層間係得形成有被Μ件材料407以形^斤 18180 1285426 需之被動元件。 A被動7〇件材料4()7可選擇為電阻材料或電谷本 ^阻材料可為選自鎳鉻⑽心）、義⑽_p)、錄錫 (Ν’、鉻叙（Cr_A1)、及氮化鈦⑽)合金所組成之 之任一者。★女Φl丨 、、、’ 於太J Ϊ 可為高分子材料、陶竟材料、陶究 =—者所^二分子及其相似物之混合物所組成組群之其中 此外，該線路增層結構41外表面可形成有防焊声 414，且該防焊層4〗4且女〜如 曰 於其上植置有多數例如=1口以外露出部分線路’俾 元件川，俾得以提Π 導電凸塊或金屬焊塾等導電 404透過t 該承載件4G之該半導體晶片 409、線路電性連接墊他、導電結構儀、線路層 、、泉路增層結構41之 曰 連接至外部裝置。 ^及冷电兀件416以電性 本發明如第3盥4圖所+彡m , 嵌至線路間以开〉成被動 〜4猎由將被動元件材料鑲 ”化成被動兀件’並與半導體晶片整人，以挺 二置内被動元件之佈設數#與電:1 設被動元件，以增加整體線路佈局= 二，：減使用面積，以達半導體裝置輕薄短小之二 :’亦因將被動元件鑲歲於半導體晶片之電 二问 逐可因此縮短被動元件與晶片間之電性 上， 免因傳輪距離過長所產生之雜訊干擾及其：電：門：以避 ^閱第5圖所示，係、為本發明 元 入基板之整合結構第三實施例之剖面示意圖:：： 18180 12 1285426 一實施例大致相同，主要差異係在於本實施例亦可用於例 如印刷電路板等多層電路板。該多層電路板具有至少 電層508與至少一線路層5〇9形成於該介電層5〇8上，盆 中各該線路㉟509係可藉由電鑛導通孔（ρτΗ)52〇或導電盲 孔510而加以相互電性連接，且至少一具複數電性連接^ 5〇5之半導體晶片504係嵌埋於介電層5〇8中，該半導體 日日片504亚藉由複數形成於該介電層5〇8中例如為導電盲 •孔之導電結構506以電性連接至該線路層5〇9,其中 由該半導體晶片504、介電層5〇8與線路層5〇9形成一 ^ 導體晶片504埋人基板之整合結構，於該晶片電性連接塾 中5與線路層5〇9間，以及相鄰層間之線路層間係可因應 a性需求性形成有例如電阻或電容之被動元件材料 5〇7以形成所需之被動元件，藉以提升半導體裝置之電性1285426 IX. Description of the Invention: [Technical Field] The present invention relates to a whole 5, and σ structure in which a wafer and a passive component are embedded in a substrate, and in particular, a semiconductor wafer and a passive component are embedded therein. The semiconductor integrated structure. ^ [Prior Art] Due to advances in semiconductor manufacturing and the increasing functionality of circuits on semiconductor wafers, the development of semiconductor devices has become highly integrated. The goal is to use ball grid array (BGA) package structures and flip-chip arrays. The (FCBGA) package structure gradually replaces the conventional lead frame-based semiconductor device. The ball grid array type semiconductor device has a U output/input connection terminal in the same unit % to accommodate more. Emperor circuits and semiconductor wafers are placed on top of them. The accumulation of electric I·隹 半' body devices, the number of pins in the package structure = and the number of pins and the number of lines are arranged, so that the noise is also: | Zhuang - so 'general to eliminate noise or electricity The compensation is based on the semi-conductor and the second, adding passive components such as resistive components, capacitive components, and two-chip noise removing and stabilizing circuits to make the encapsulated semiconductor solar wafers meet the electrical characteristics. Christine m1, shown as 'incorporating today's high-density multi-chip modular FrC 0 ball grid array (4) P-(3)P Ban Grid Array, FCBGA) package structure of the package and ball grid array main = simultaneous flip chip number The embossing substrate 1U can be electrically connected to the package substrate 18180 5 1285426 13 (Substrate) surface 13a by the ▲ 〇 ef ef mp mp ' , , , , , , , , , , , , , , , , , , , , The surface... can further form at least the passive component i4 according to the design requirement, and a plurality of solder balls 15 (SolderBall) as input/output_= are implanted on the other surface of the package substrate 13. This-connected structure can greatly reduce the body and at the same time eliminate the design of the conventional wire bond, and can reduce the resistance of the block to improve the electrical properties, so as to avoid the signal degradation during transmission, so it has been packaged with electronic components. Mainstream technology. However, the conventional flip-chip ball grid array is used to connect the wafer u and the passive component to the outside of the package substrate 13. Due to the design of the circuit, a considerable number of passive components must be connected to the surface of the package substrate 13. 14. Then, because the number of the skin moving elements 14 is increased, the circuit area is occupied, and the area of the package substrate 13 is increased, so that the volume reduction cannot be achieved. Further, a large number of passive elements 14 are attached to the surface of the package substrate 13. If the area of the substrate 13 can be limited, the high-density package is disadvantageous for high-density packaging. Furthermore, if the circuit layout (lay〇ut) is improperly arranged, it will cause unnecessary parasitic impedance (parasitic (10)CC). For example, the formation of parasitic resistance is the result of the trace from the part to the part. Parasitic capacitance may be generated by traces, rods, and parallel traces, and the parasitic inductance (10) α is caused by inductance and mutual induction due to the loop formed in the periphery. The parasitic impedance will have a bad effect on the transmission of the signal, resulting in the lack of integrity of the signal transmission wheel (Integrity), that is, the signal contains noise (n〇ise), which affects the correct transmission of the signal. 18180 6 1285426 ... the passive component 14 is connected to the surface of the package substrate 13 and the circuit connecting the passive component 14 extends to a line where the trace is too long to cause a miscellaneous portion, and due to "and the impedance increases, The improvement of the electrical characteristics is limited to 0 = Bu, please refer to Figure 2, after the wafer η of the above semiconductor sealing material, the completed package must be "on the 2Uprinted circuit board, pCB) = : The surface of the 21 surface also needs to be provided with a plurality of passive components for the purpose of the invention. In addition, the manufacturing cost is complicated, and the manufacturing cost is increased. In view of the above disadvantages of the prior art, a wafer and a passive component of the present invention are buried in the United States. The number of passive components in the actor and the device is =:: : cloth, and the flexibility of the circuit layout. The other purpose is to provide an integration of the chip and the passive component embedded in the substrate. Structure, shrinking and reducing the size of the semiconductor device to make the device thin and light. The compensation for the device is +000 US; the second purpose is to provide a type of wafer and passive components buried in the second structure: the semiconductor wafer and the passive component are directly electrically connected • , ^ wiring length, reduce impedance and improve electrical characteristics. The re-import of the invention - the integrated structure of the substrate, ^ ^ to = a wafer and passive components buried in the body, improve; two passive components and carriers Degree and simplification of the process steps, reducing the sub-effectiveness of the package to achieve the above and other Η ώΑ, 9 '%% of the wafer and passive components buried 18180 7 1285426 substrate integrated structure, mainly including a carrier; at least a semiconductor wafer to be bonded to the carrier; the electrical layer is formed on the carrier and covers the semiconductor wafer. The circuit layer is formed on the dielectric layer, and the core And electrically connected to the electrical connection pad by a plurality of teeth passing through the conductive layer of the dielectric layer, wherein at least one of the lead + έ, the cymbal V private, the mouth structure and the 连接 connection pad are formed The passive component material is used to constitute the passive component. Furthermore, the integrated structure of the wafer of the present invention and the passive component buried substrate can be included to form a line formed on the dielectric layer and the wiring layer: the wire: the layer structure includes介介a layer formed in the dielectric: upper:: germanium dielectric layer to provide a circuit layer as an interlayer electrical hole to be electrically connected to the circuit layer, wherein at least the passive element material is formed to form a desired component Passive two 1. The circuit layer is the same as the W and the passive component of the present invention. The semiconductor wafer is placed on the carrier, and vice versa, and the mouth is constructed on the 4th and 4th warfare parts of the Jigu Mountain. In the dielectric layer, directly extending from the active surface of the half-v body wafer, and partially extending the electrical connection (4) 2 to f to form a desired passive component having a passive component material connection 'And the line in the structure of the build-up line = also in the electric blind hole and the line sound - the passive component dry · mountain U into the piece of material' 俾 by lining the 7G parts of the material to the line, and The number of passive components in the semiconductor device is set to be equal to = additional to the surface of the device to add passive ^, and the world needs to pass 70 pieces 'to increase the overall line layout flexibility 18180 1285426 Τ '* 亚 可 可 reducing the area to reach the semiconductor The goal of being light and short, and at the same time, The component is embedded in the electrical connection between the semiconductor chip and the interlayer circuit, so that the transmission distance between the passive component and the wafer can be shortened, so as to avoid the noise, interference and poor electrical performance caused by the long transmission distance. problem. [Embodiment] In order to further understand the object, features and effects of the present invention, a total of (10) and the following are provided for the following embodiments, with detailed disclosure and detailed description of the drawings. The invention may be embodied in a variety of forms, and the following is a preferred embodiment of the invention, and is not intended to limit the scope of the invention. Referring to Fig. 3, there is shown a first embodiment of the integrated structure of the wafer of the present invention and the passive component embedded in the substrate. The integrated structure includes a carrier member 3, and the carrier member 30 includes a first carrier plate 3 and a second carrier plate 301. The second carrier plate 3〇 has a through hole, and the carrier member 30 is made of a material. The material may be a metal, such as copper having high thermal conductivity, or a ceramic layer, an organic insulating layer, or a circuit board on which a line has been formed. The materials of the first and second carrier plates 300 and 301 may be the same or No (4), and the thickness of the first and second carrier plates 300, 301 may be determined as needed. The semiconductor wafer 304 is connected to the first carrier plate 3 of the second carrier through the opening 302 by the thermal conductive adhesive layer 3〇3, and is covered on the semiconductor wafer 3〇4 and the carrier 30. The electrical layer 3 〇 8 is partially filled into the gap between the second carrier 301 and the semiconductor wafer 3 以 4 to fix the wafer 3 ( 10 ), and the wiring layer 3 〇 9 is formed on the dielectric layer 308 . And the circuit layer 18180 9 1285426 is electrically connected to the electrical property of the + conductor wafer 3G4 by the conductive structure 3〇6 (for example, a conductive mesh) passing through the dielectric layer 3〇8 The carrier 3〇, the dielectric layer 3309, and the +-circuit layer 309 form an integrated structure of the semiconductor wafer 304 and the substrate 304 embedded in the substrate. The material::Γ::冓306 A passive component is formed between the electrical connection pads 305 = 30 ^. The rain related to the fixed connection between the semiconductor wafer 3 〇 4 and the carrier plate is in the same time as the carrier plate 3 〇〇 layer 3 (4) The material f is a resin-containing material, and can be used to press the gap between the carrier board 3G1 and the semiconductor wafer 304. ...Day a line #3:9 f-port, structure The circuit build-up structure 31 formed on the dielectric layer 308 and the scoop 1 may be included. The circuit build-up structure 31 includes an 'I electrical layer 310, and a circuit layer formed on the dielectric layer 31〇. And the circuit layer 311 formed in the dielectric layer 3 ΐ〇 φ 4 ^ θ λ is connected as an interlayer electrical connection e, Η, 俾 for the line build-up structure 31 to borrow & the number of blind holes 312 electrically Connected to the circuit layer 309. At least ^ 312 and the circuit layer _ are formed with a passive component material 3 〇 7: into a desired passive component. The shichuan / shape ~ component material 3 〇 7 can be selected as a resistive material Or a capacitor material. The resistive material may be a powder selected from the group consisting of nickel-chromium (10) core, nickel-filled (Ni_p), tin-plated (four) must A1), and titanium nitride (10) alloy. The material, the pottery, the pottery and the pottery are composed of a mixture of similar substances, wherein the outer surface of the line build-up structure 31 can be formed with the anti-welding 18180 10 1285426, and the partial line is exposed outside the σ, and the plant is exposed thereon. A conductive element such as a 31611 ball, a conductive bump or a metal soldering is centrally received in the half of the carrier 30 The conductor wafer 3〇4 transmits the == connection pad 3〇5, the conductive structure 3.6, the circuit layer·, the circuit θ layer, the σ structure 3 1 line, and the conductive external device. In addition, in the second embodiment of the present invention, as shown in FIG. 4, the material may be a metal such as copper. The material of the semiconductor wafer is a thermal conductive adhesive layer. Attached; ^ on the carrier 40, and in the test layer 403 is placed in the Shaoyi Jiegong #加广体曰曰片4〇4 and the bearing member 4〇 covered with 1 and the soul gland ^ 4Π and at 5 介介A circuit layer 409 is formed on the electrical layer 4〇8, and the damage m9 is electrically connected to the semiconductor wafer 4〇4 by a plurality of conductive structures far beyond the dielectric layer 4〇8. Ϊ = 8 wherein a semiconductor wafer 4 is formed by the carrier 40, the semiconductor wafer 4, 4, 2: and the wiring layer 4. 9. The buried substrate is formed with a passive component material 40^,,, and 4 〇6 and the electrical connection 另外 another 'secret structure complex may include a line build-up structure 41 formed on the circuit layer 409 of the dielectric layer 4, the line build-up layer includes: electrical layer (10) formed on the dielectric layer 41. The upper line; Mb provides the circuit layer 4 ιι as interlayer power in 41 (): == 12' 俾 for the line build-up structure 41 by the plurality of conductive § electricity! • Connect to the circuit layer 4〇9. At least one of the dead holes 412 and the circuit layer is formed with a passive component that is formed by the material 407 to form the 18180 1285426. A passive 7-piece material 4 () 7 can be selected as a resistive material or an electric resist material can be selected from the group consisting of nickel-chromium (10) core, Yi (10)_p), recorded tin (Ν', chrome (Cr_A1), and nitrided Any of the titanium (10)) alloys. ★Female Φl丨,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The outer surface of the 41 may be formed with a solder resist 414, and the solder resist layer 4 is 4 and the female is placed on a plurality of, for example, =1, and a part of the line is exposed, and the conductive element is lifted. The conductive 404 such as a block or a metal soldering wire is connected to the external device through the semiconductor wafer 409 of the carrier 4G, the line electrical connection pad, the conductive structure meter, the circuit layer, and the spring road addition structure 41. ^ and the cold-wired device 416 is electrically connected to the line according to the invention, as shown in Figure 3盥4, 嵌m, embedded in the line to become passive~4 hunting by the passive component material into a passive element and with the semiconductor The whole person of the chip, with the number of passive components in the two sets, and the number of electricity: 1 set passive components to increase the overall circuit layout = 2, reduce the use area, to achieve the semiconductor device is light and short: "Because it will be passive The component is mounted on the semiconductor chip and the second problem can shorten the electrical property between the passive component and the wafer, so as to avoid the noise interference caused by the long distance of the transmission wheel and its: electricity: door: to avoid the fifth picture BRIEF DESCRIPTION OF THE DRAWINGS The cross-sectional view of the third embodiment of the integrated structure of the present invention is: 18180 12 1285426 An embodiment is substantially the same, the main difference is that the embodiment can also be used for a multilayer circuit such as a printed circuit board. The multi-layer circuit board has at least one electric layer 508 and at least one circuit layer 5〇9 formed on the dielectric layer 5〇8, wherein each line 35509 in the basin can be electrically conductive via hole (ρτΗ) 52〇 or Conductive blind holes 510 and electrically connected to each other And at least one semiconductor wafer 504 having a plurality of electrical connections is embedded in the dielectric layer 5 〇 8 , wherein the semiconductor solar 504 is formed by the plurality of dielectric layers 5 〇 8 Conductive blind hole conductive structure 506 is electrically connected to the circuit layer 5〇9, wherein the semiconductor wafer 504, the dielectric layer 5〇8 and the circuit layer 5〇9 form a conductive wafer 504 embedded substrate integrated The structure is between the circuit 5 and the circuit layer 5〇9 of the chip, and the circuit layer between the adjacent layers can form a passive component material 5〇7 such as a resistor or a capacitor according to the requirement of a property to form a desired Passive components to enhance the electrical properties of semiconductor devices
功能。 W 另外’該些線路層間係可藉由導電盲孔51〇作層 性且於部分線路層與導電盲孔別間係形成有被動 兀件材料507以形成所需之被動元件。 孫Π 本發明之晶片與被動元件埋人基板之整合結構 合有半導體晶片與被動元件，提供半導體晶片與 直接電性連接，有效縮短接線長度，減少阻抗並 接*屯生功月匕。再者’本發明係將被動元件欲入於封裝么士 :中’藉以大幅縮減於承载件表面上安置被動元件之面、、。 積^達半導體裝置㈣短小之目標。並復包括 兀件於線路增層結構之相線路層，藉以 2 18180 13 1285426 内被動元件之佈設數量，並增加線路佈局的 本發明可同時整合半導體口此’ 俨，楹古？I止 饭動兀件及承載件於一 Γ半上之71料度，並有效提高集積度，且整 口、被動元件及承載件於 能降低封裳之成本。 Π化衣私步知’ 惟以上所述僅為本發明之較佳實施 疋本發明之實質技術内裳之f 非用以限 俜卢羞P 本發明之實質技術内容 係廣義地Μ於下述之申請專利 之技術實體或方法，若是盘下述之·…丨仃他人所-成 =目ϋ’或疋為同-等效之變更，如本發明所稱之基板 、’限疋於覆晶式基板，亦可使用打綠4 I^ 視為涵蓋於此專利範圍之中。 …土反’，均將被 【圖式簡單說明】 視示=圖係為習知覆晶式球柵陣列之半導體封褒件的剖 n係為習知半導體封裝件及被動元件接置 电路板之剖視圖； ' 構第-第=::=與被動元件埋人基板之整合 弟4圖為本發明之晶片 構第二實施例之剖面示意圖 第5圖為本發明之晶片 構第三實施例之剖面示意圖 與被動元件埋入基板之整合結 ;以及 與被動元件埋入基板之整合結 【主要元件符號說明】 18180 14 1285426 11 晶片 11a 主動面 12 凸塊 13 封裝電路板 13a 表面 14 被動元件 15 銲球 21 印刷電路板 40 承載件 300 第一承載板 301 第二承载板 302 貫穿開孔 303, 403黏著層 304, 404, 504 半導體晶 305, 405, 505電性連接墊 306, 406, 506導電結構 307, 407, 507被動元件材料 308，408，508 介電層 309, 409, 509 線路層 31，41線路增層結構 310, 410 介電層 311, 411 線路層 312, 412 導電盲孔 314, 414 防焊層 316, 416 導電元件 520 電鍍導通孔 510 導電盲孔 15 18180Features. Further, the circuit layers may be layered by the conductive vias 51 and a passive component material 507 is formed between the portion of the wiring layers and the conductive vias to form the desired passive components. Sun Wei The integrated structure of the wafer and the passive component buried substrate of the invention combines a semiconductor wafer and a passive component to provide a direct connection between the semiconductor wafer and the device, thereby effectively shortening the length of the wiring and reducing the impedance and connecting the power. Furthermore, the present invention is intended to reduce the passive component to the surface of the carrier member on the surface of the carrier. The product of the semiconductor device (4) is short. The invention further includes the phase circuit layer of the circuit-added structure, and the number of passive components disposed in 2 18180 13 1285426, and the circuit layout is increased. The invention can simultaneously integrate the semiconductor port. I stop the feed piece and the carrier on the first half of the 71-degree, and effectively increase the accumulation degree, and the whole, passive components and the carrier can reduce the cost of the cover. The above description is only a preferred embodiment of the present invention, and the technical scope of the present invention is not limited to Lu Sha. The technical content of the present invention is broadly described below. The technical entity or method of applying for a patent, if it is the following, ... 丨仃 所 - 成 成 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 , , , , , , , , , , , , The substrate can also be used in the scope of this patent. [土反', both will be [simplified description of the diagram] View = diagram is a conventional flip-chip ball grid array of semiconductor package section n is a conventional semiconductor package and passive component connection board FIG. 5 is a cross-sectional view showing a second embodiment of the wafer structure of the present invention. FIG. 5 is a third embodiment of the wafer structure of the present invention. The cross-section diagram is integrated with the buried component of the passive component; and the integrated structure of the passive component embedded in the substrate. [Main component symbol description] 18180 14 1285426 11 Wafer 11a Active surface 12 Bump 13 Package circuit board 13a Surface 14 Passive component 15 Solder Ball 21 printed circuit board 40 carrier 300 first carrier 301 second carrier 302 through opening 303, 403 adhesive layer 304, 404, 504 semiconductor crystal 305, 405, 505 electrical connection pads 306, 406, 506 conductive structure 307, 407, 507 passive component material 308, 408, 508 dielectric layer 309, 409, 509 circuit layer 31, 41 line build-up structure 310, 410 dielectric layer 311, 411 circuit layer 312, 412 conductive blind hole 314, 414 Solder mask 31 6, 416 Conductive Element 520 Plating Through Hole 510 Conductive Blind Hole 15 18180