TWI284934B - Multi-layer semiconductor wafer structure and fabrication method thereof - Google Patents

Abstract

A multi-layer semiconductor wafer structure with free areas limiting the placement of test key. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of multi-layer structure, and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribed line and is defined by the equation: A1=D1xS1, where D1 is the distance from the corner point of the die toward the main area of the die along the first scribe line, and S1 is the width of the first scribe line. Free area As is defined on the intersection of the first scribed line and the second scribe line, and is defined by the equation: As=S1xS2, where S1 is the width of the first scribe line, and S2 is the width of the second scribe line.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor wafer having a low dielectric constant inner metal dielectric layer, and more particularly to a test key on a scribe line (test) Key) The design rules for the configuration. The present invention relates to a design rule for a wire loop (c ο n d u c t i v e r i n g ) in a corner region of a wafer. The term "free area" means an area on the scribe line where test keys are prohibited from being set, which prevents stress peellng in the delamination area near the corner area of the wafer. Forming one or more trenches in the wire loop avoids the application of defects to the defects of the low dielectric constant layer. Prior Art Integrated circuit manufacturers have been developing ultra-compact and high-speed semiconductor components for electrical constant materials and other small and small line width and low dielectric related technologies. As far as reliability is concerned, the challenge of rate and yield becomes more constant. The material will have crack defects, and the low dielectric near the corner area will occur.另 最 最 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片Individual wafer modules with circuits. In semiconductor manufacturing, semi- & independent packaging or packaging into a multi-chip continuously in each step, the U-body component or integrated circuit (IC) must be made at the same time as the actual component. Quality, while test electricity, & ° typical test method is on the wafer

1284934 V. INSTRUCTIONS (2) Several test keys are provided on the scribe line between the two, and the test key is electrically connected to the external electrode by the metal 塾. The test key is selectively tested for various properties of the wafer, such as starting voltage, saturation current, inter-layer oxide thickness or leakage current, and the like. Generally, the dicing track is a multi-layered structure having no pattern, and the width is about 80 to 100, and the width thereof is different depending on the size of the wafer produced in the wafer. In order to prevent cracks induced by the wafer dicing process from spreading to the inside of the wafer, a sealing ring (s(5)i ring) is provided around each wafer, and has a width of about 3 to 10. However, in the wafer manufacturing process, the cutting lane often induces some defects. Moreover, if at least one of the layers of the multilayer structure is composed of a metal material having a high coefficient of thermal expansion, the change in the thickness of the layer is sufficient to induce a high-order internal stress to the scribe line, and the peripheral portion of the scribe line may be defective, such as • Peeling, delamination or breakdown of the dielectric layer, and the like. If the multi-layer structure contains a low dielectric constant inner metal dielectric layer, the above-mentioned scribe line defects are often found. The rule of the test button configuration on the 曰切吾彳道, the main consideration is whether the stress generated by the cutting process will cause serious peeling phenomenon near the test button at the corner of the wafer. The delamination occurs at the interface of the multilayer material. The delamination phenomenon affects the reliability of the component' and contributes to the stringer and interferes with subsequent processes and tests of the integrated circuit. 'β Several solutions have been proposed to address some of the technical issues related to semiconductor wafer fabrication and cutting processes. One way is to use a plasma etching process to make a plurality of trenches in the insulating region, which can greatly reduce the cracks here.

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V. INSTRUCTIONS (3) • However, it is still impossible to completely prevent the occurrence of cracks. Therefore, there is a need for new development and test key design rules to prevent delamination or peeling near the corners of the wafer. In order to provide a line to supply a ground voltage or a supply voltage to a circuit unit within the wafer, conventional techniques produce a conductive ring on a major portion of the wafer. In the sealing process of the resin type package, it is often found that the protective film at the corner of the wafer is broken by stress. U.S. Patent No. 5,3,7,1,1,1, discloses a solution for making a groove or a row of small holes in a guard ring, but it is generally considered to be an opening in such a guard ring. It is still not possible to prevent cracking defects in the inner metal dielectric layer during the wafer dicing process. If a low dielectric constant material is used near the corner of the guard ring, the above-mentioned crack problem becomes more serious and the reliability is lowered. Therefore, ^ = a new development of a guard ring design rule on the corners of the wafer to prevent the cracking of the inner metal dielectric layer during the wafer cutting process. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide an idle area which is a zone on the scribe line that prohibits or substantially limits the placement of test keys to prevent delamination or peeling from occurring near the corners of the wafer. °° 3 ' Another object of the present invention is to provide a conductive ring with a plurality of trenches or a plurality of trenches to prevent low dielectric constant =; cracks generated by applying stress to the corners of the wafer problem. " A multi-layer semiconductor wafer junction. In order to achieve the above object, the present invention provides _ for defining a plurality of products fabricated thereon.

1284934 V. INSTRUCTION INSTRUCTION (4) - * extends in a first direction, wherein the second cutting lane: the second cutting lane extends along the -second direction - the corner - black. At least = the first scribe line is staggered in the - the first scribe line, at least the j-zone is defined in the first scribe line and Ί|ί1 J- , jMl φ _ 'Hit is set in the idle area Inside. The eight T / then bond system is limited to the top layer of the wafer structure, or the region is defined by at least the layer of the layer of the semiconductor wafer. The crystal cutting, jet cutting, and water knife cutting methods are separated: diamond cutting, at least one screen cutting in the laser wafer structure, or a combination of the above cutting methods. The number is slightly less than 3.5, which is more concentric; the dielectric I of low dielectric constant, the dielectric often has an idle area defined by ^ (4) less than, 3. 0. The area of the person is shamed by the following formula; w on the scribe line, and the corner of the first wafer in the idle area is Al = Dl X Sl, where D1 represents the self-representation of the first scribe line = The first direction extends the distance, and S, the test key, and the test key Yue; := The area is set with at least - column formula 4 = Ml / Ai, complex;; the area ratio h of the VW area meets the total area of the next test key, and 1 indicates that the idle area is at least _, the The first cutting lane 丄 = 1: 1:%. The distance ^ is slightly smaller than the idle area is defined by the first: cut, "slightly" staggered, and the σ of the idle area, the s2 of the first scribe line, where S1 represents the Λ ^, =: ΓΓ formula Definition: AJ 宽度 The width of the scribe line. Within the idle area, set the second and 'small and one' to represent the second test key and the face of the idle area 7 > a test key, and Λ < area ratio Rs Meet the following formula · ρ

0503-10005twF(nl); tsmc2003-0150; 1283; Cherry.ptd goods 11 words Fulibei 1284934 V. Description of the invention (5) The width 31 of the track and the first multilayer semiconductor chip. The wafer extending the wafer junction includes a first extension, a conductive ring and the second peripheral region adjacent to the first two less trenches, or two regions and the second peripheral sheet includes The power is connected to the circuit single circuit unit. The total conductive area, and Rs is approximately less than 1%. The width of the first cut-cutting track & is approximately greater than about 20. In order to achieve the above object, the present invention provides a structure in which a plurality of crystal-first peripheral regions are formed on the basis of a parallel region of the first dicing street and parallel to the second dicing channel. The first peripheral region of the first wafer and an opening pattern are formed in a corner region of the conductive ring wafer. The opening pattern includes a plurality of holes, and the opening pattern extends in at least one of the first peripheral regions. The circuit area of the first plurality of circuit units, the conductive ring system is configured to provide a power supply voltage or a ground voltage to the width of the ring of 50 to 30 0 am. The above and other objects, features, and advantages of the present invention will become more apparent and understood. The embodiment provides a semiconductor wafer having an "idle area", and the "idle area" means an area on the scribe line where the test button is limited. The area where the test button is prohibited or limited can reduce delamination or peeling near the corner of the wafer. phenomenon. The "idle area" on the cutting track can be

1284934 V. Invention description (6) "--, use square, low; | electric constant wafer (L K wa f er ). It is worth noting that the "idle area" means an area that defines the test button, and allows a small number of test keys to be placed in the idle area, but the f test key, ', 'area and idle area' in the idle area The ratio of the area must conform to an acceptable range or 'the "idle area" means an area where the test button is prohibited from being set, that is, it is not allowed to place any test keys in the idle area. Fig. 1 is a top plan view showing a wafer of a first embodiment of the present invention, in which a plurality of lamellas of the package 3 are separable via a dicing street. A semiconductor wafer i package contains a plurality of wafers 16, and a plurality of first-cut streets 12 and second scribe lines 14 effect a substantial isolation between the plurality of dies 16. The first scribe line 12 extends in the first direction, the second scribe line 14 extends in the second direction, and the intersection of the strip first cut 1 2 and the second scribe line 4 defines at least one wafer 16 A corner point. As shown in the figure, the first scribe line 12 extends in the horizontal direction, and the second scribe line 14 extends in the vertical direction, so that the staggered portion can define the corner points of the four wafers 16 other than the semiconductor wafer 10 A plurality of test keys 18 are included in the area other than the "idle area" of the first chute 1 2 and the second chopping path 14, and the design rule of the "idle area" will be described below. The 帛 conductor wafer ίο is a low dielectric constant wafer, and the first scribe line 12 and the second scribe line 14 are both a multilayer structure. Figure 2 shows a schematic cross-sectional view of a multilayer structure of a wafer dicing street. / The substrate 20 is formed with a multi-layer structure 24, and the first cutting lane 2 and the second cutting lane 14 are each a portion of the multilayer structure 24. The substrate 2 is made of a bulk silicon, a germanium insulator (S0I), a germanium telluride (SiGe), gallium arsenide.

1284934 V. INSTRUCTIONS (7) • (GaAs), Indium Phosphide (InP) or other semiconductor materials The structure 24 comprises a plurality of material layers 21, 22. At least one of the plurality of layers is a low dielectric constant dielectric layer 2, = material layer H is 3.5 Å, preferably a dielectric constant of less than 3 Å. The dielectric layer can be picked up by one of the following materials: S1〇C, Sl0CN formed by low-electricity, and polymer material formed by spin coating and vapor deposition by chemical vapor deposition. The cloth is opened, and the Si〇c is formed by the chemical sub-material, the fluorine-containing glass (FSG), and the oxidized cloth. y^102) or a group of the above materials, the "idle area" is at least a layer of the multilayer structure 24 of 12, 14. Brother everything. j·, domain is defined at the top of the multi-layer structure 24: “The “idle zone is defined in the top three of the multi-layer structure 24” in the second=two “idle zone”, including the 糌/layer by appropriate cutting method . Jet cutting (for example: waterjet cutting) or H, cutting, laser cutting, so that the combination of circuit unit 2 = cutting mode on the wafer 10, the test button 18 is an auxiliary conductive structure i The film 16 is separated. Pulse modulating modulator (PCM) or a non-electrical starting structure (eg: cell (fr)). Non-electrical starting structure (eg, frame below) The first and the first = V ^ ' near a corner point of 1 6 indicates the area where the test button 18 is placed on a wafer. All the sub-channels 1 2, 1 4 are limited to the 3A picture as the first type of idle area. The idle area on the nearby cutting road. X # 再 再 再 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一

1284934 V. INSTRUCTION DESCRIPTION (8) • The track 12 and the second scribe line 14 extending in the second direction are staggered to separate the main region 26 of the f-sheet 16. A circuit unit is formed on the main area 26, and the brother cuts the road! The intersection of 2 and the second cutting lane 14 defines a main zone, a corner point P of 26, and a first cutting lane W near the corner point p. & According to the material rule of the idle area, the test key 18 can be arbitrarily placed on any area of the outer-first scribe line 12 or the second scribe line 14. The area of the idle area A is defined by the following formula. Dl X Sl 'where Dl represents the distance from the corner P to the main area 26 and extends in the first direction 'S! represents the width of the first cutting path i 2 . Preferably, Dl is less than 60 0 (four), ^ is greater than 2"m. The idle area is at least one of the plurality of layers 24 of the first scribe line 12. Preferably, the free area is located on top of the multilayer structure 24. Alternatively, the free area A is located in at least one of the top three layers of the multilayer structure 24. The test button 丨8 is completely prohibited in the above-mentioned idle area. A small test button 18 can also be set in the idle area & the value is a prerequisite. The area ratio defined by the following formula must be approximately less than 1〇%: Ri= Μ〆, where 蝌 is representative of the idle area Ai Test the total area of the keys 18. Figure 3B is a top view of a second type of free area showing an idle area on a scribe line near a wafer. The elements similar to those shown in Fig. 3A are omitted here. An idle area Az is defined on the second scribe line 14 near the corner p of the wafer 16. Similar to the foregoing, the test key 18 can be arbitrarily placed on any area of the first scribe line 12 or the second scribe line 14 other than the idle area a2 in accordance with the design rule of the idle area. The area of the idle area μ is defined by the following formula: A2 X where d2 represents the rotation angle p

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^84934 ____ V. Description of invention (10) 'The area ratio of Rs must be no more than 10%: Ms/As, where Ms represents the total area of the test key 18 in the idle area As. Figure 3D is a top view of a fourth idle area showing an idle area on a scribe line near a wafer. Elements similar to those shown in Figures 3A to 3C are omitted from the description herein. Similar to the foregoing, depending on the design rule of the idle area, the test key 18 can be arbitrarily placed on any area of the idle area, such as the gossip, A2, As, or any of the sub-channels 14. A small number of test keys 1 8 can also be set in the idle area A f , , , As, but the precondition is that the area ratio R defined by the following formula must be slightly less than 10 % : R = (MMMsVUjajAs). The following embodiment details the "idle area" which describes the area on the first and second scribe lines 1 2, 14 near the four corner points of a wafer 16 which limits the setting of the test key 18. Figure 4 is a top view of a fifth idle area showing the idle area on the scribe line near the four corner points of a wafer. The elements similar to those shown in Figs. 3A to 3D are omitted here. - a wafer 16 can be separated from the first scribe lines 121, 121 I and a pair of second scribe lines j 41, hi I, and the intersections can define the four corners p of the main region 26, and each corner point p There are defined idle areas Αι, ,, A nearby. In the design rule of the idle area, the test key 18 can be arbitrarily placed on the area of the first scribe line 12 and the second scribe line 14 other than \, A?, As. 1 区域 区域 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Figure 5 is a top view of the sixth idle area, showing four crystals of 蹲^

1284934

V. INSTRUCTIONS (11) ‘The idle area on the scribe line between the sheets. The first dicing street 12 and the second dicing street 14 can isolate the adjacent four wafers 161, 16U, 16 ΙΠ, 16IV from each other, and the intersections can define four wafers 16 Ϊ, 丨 6 丨丨, respectively.四个6丨丨j, ° 1 6 IV four corner points Pi, P2, P3, and four corner points Pi, p2, 'p3, P4 are defined near the idle area Μ, A2, a3,,, As. According to the design rule of the free area, the test key 18 can be placed on any of the first scribe line 12 and the second scribe line 14 other than the idle areas Αι, Μ, As, Μ, As. The idle area is defined on the first scribe line 12 between the first wafer 161 and the third wafer 16 , and adjacent to the corner points Ρ, p3. The area of the free area core is defined by the following formula: Al = h X Sl, where Di represents the rotation corner point P! The distance toward the main area of the first wafer 161 and extending in the first direction 'S1 represents the first cut The width of the road 12. Preferably, Di is less than 6 〇〇 "m, Si is greater than 2 0 /zm. A small number of test keys 18 may be allowed in the idle area A! but the area proportionality defined by the following formula must be approximately less than 10%: R1= , where the milk system represents the total area of the test key 18 in the idle area 。. The idle area VIII is defined between the first wafer 161 and the first 曰μι 00 ^ „, the middle day and the Japanese film 1 6 11 The second brother cuts the track 14 and is adjacent to the corner points Ρι, ρ2. The area of the idle area 0 is defined by the column: A2 = D2 X s2, where D2 represents the rotation angle point toward the main area of the second wafer 1611 and is separated by the first, and the s2 line represents the width of the second cutting track. Good: The distance to the extension is "111,32 is greater than 20"111. The idle area can also be allowed within 8:2, 1)2 is less than 6〇() Test key 1 8, but the area ratio defined by the following formula ^ W \ must be approximately less than

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1284934 V. INSTRUCTIONS (12) .1 0 % : R = M / A ' where & represents the total area of the test key 1 8 2 2 2 _ set in the idle area 八2. The idle area A3 is defined on the second scribe line 14 between the third wafer 16 Η I and the fourth wafer 166 V and adjacent to the corner points Ρ4. The area of the idle area 八3 is defined by the following formula: A3 = D3 X S2 ' where D3 represents the distance from the rotation corner point p3 toward the main area of the third wafer 166 and extends in the second direction, and the S2 represents the second Cut the width of the track 14 . Preferably, it is less than 6 0 0 "m, and S2 is greater than 2〇. A small test button 1 can also be set in the idle area, but the area ratio R3 defined by the following formula must be slightly less than 10%: R3= M3/A3 'where M3 represents the test key in the idle area A3. The total area. The idle area VIII is defined on the first scribe line 12 between the second wafer 1611 and the fourth wafer 16IV, and adjacent to the corner points h, P4. The area of the idle area 八 4 is defined by the following formula: A4 = D4 X ' where D4 represents the distance from the corner point P4 toward the main area of the fourth wafer and extends in the direction of the younger brother, and Sj represents the second scribe line 12 width. Preferably, D4 is less than 60 0 "m, and Si is greater than 2〇. In the idle area, a small test button 1 can also be set. However, the area ratio I defined by the formula must be slightly less than 10%: R4= Μ4/Α4 'where the system represents the idle area. The total area of 8. The idle area As is defined at the staggered arrangement of the first scribe line 12 and the second scribe line 14 and adjacent to the corner points P!, P2, P3, P4. The area of the intervening area As is defined by the following formula: · As = Si X S2 ' where Si represents the width of the first scribe line 12 and represents the width of the second scribe line 14. Better

0503-10005 twF(η1);t smc2003-0150;1283;Che rry.ptd Page 19 1284934 V. Description of invention (13) - For, Si is greater than 2 0 # m, s2 is greater than 2 〇 // m. A small test button 1 can also be set in the idle area As. However, the area ratio Rs defined by the following formula must be slightly less than 10%: Rs=Ms/As, where Ms represents the test key set in the idle area As. The total area. In addition to this, for the multilayer structure 24 of the first dicing ballast 2 or the second dicing street 14, the vacant areas ^, , 八, 3, 4, and 5 are at least one of the multilayer structures 24. Preferably, the idle areas A1, A2, A3, A4, and As are located on the top layer of the multilayer structure 24. Alternatively, the idle areas Αι, , , , A4, and As are located in at least one of the top three layers of the multilayer structure 24. Figure 6 is a top view of the seventh idle area showing the idle area on the scribe line between the four wafers. The elements similar to those shown in Fig. 5 are omitted here. The difference is that the idle areas Ai, a2, A3, A4, and As are asymmetric patterns, where Di is not equal to D4, and D2 is not equal to D3. Compared with the prior art, the above-mentioned seven kinds of idle areas provided by the present invention avoid the occurrence of peeling in the vicinity of the wafer corner by the stress applied in the cutting process, thereby preventing delamination of the multilayer structure interface near the corner of the wafer. Therefore, the reliability of the integrated circuit components can be ensured by limiting the test key setting area on the scribe line by the idle area. SECOND EMBODIMENT A second embodiment of the present invention provides a conductive structure that surrounds a main area of a wafer. In order to prevent the stress applied to the corner of the wafer from causing a crack defect, an opening pattern is provided near the corner of the wafer, and the crack prevention defect is achieved for the design of the opening pattern using the low dielectric constant material (II) Effect meter ° 'Big is significant. very

1284934 V. INSTRUCTIONS (14) • Also, a conductive structure having an open pattern can be combined with the design rules of the aforementioned idle area to achieve both functions. Figure 7 shows a top view of the first opening pattern of the conductive ring of a main area. Elements similar to those shown in the previous figures are omitted here. The main region 26 of the wafer 16 is formed by the definition of the dislocation configuration of the first scribe line 12 and the second scribe line 14. The first region 26 has a first peripheral region 271, and the main region has a second peripheral region 2711 in the direction of the younger brother, and the first peripheral region 271 and the second peripheral region 2711 are interleaved. It is defined as the corner area 29. A conductive structure (hereinafter referred to as a conductive ring 28) is formed in the main region 26 so as to extend adjacent to the first peripheral region 271 and the second peripheral region 27A. It is worth noting that the "conducting ring" covers the circular, rectangular and square sealing patterns. The conductive ring 28 includes an opening pattern, such as one or more grooves 30, which are positioned adjacent to the corner region 29. In addition, main region 26 includes a circuit region 32 in which circuit cells and wires are fabricated and surrounded by conductive rings 28. For a wafer surrounded by a conductive ring 28, a conductive ring 28 is electrically connected to the circuit unit to provide a supply voltage or a ground voltage. Preferably, the width W of the conductive ring 28 is from 2 350 to 350 //m. Further, the desired region 26 includes a plurality of connection pads 33 formed on the first peripheral region 271 or the second peripheral region 2711 outside the conductive ring 28. The main region 26 of the wafer 16 can be formed on a low dielectric constant wafer, and the corner region 29 can be a part of the multilayer structure. Fig. 8 is a schematic cross-sectional view showing a pair of grooves 3A along a tangent line 8-8 of Fig. 7. A conductive ring 28 having a trench 30 in the main region 26 is formed in a multilayer junction of a substrate 20.

1284934 V. Description of invention (15) • Structure 24. The multilayer structure 24 comprises at least a solid material layer 21, 22, 23 of the material layers 21, 22, 23, and a dielectric constant of less than about 3.5, which is a low dielectric constant dielectric layer, such as The low dielectric constant dielectric layer has a lower dielectric constant of less than 3.0. For example, the material of 2Si〇c formed by vapor deposition is composed of: si〇c, chemical vapor deposition, eight polymer materials formed by spin coating, and fluorine. Knife material, which is composed of a combination of materials (4) (4) (10)), oxygen cutting (calling) or

The top view of Fig. 7 shows a suitable opening pattern, 1 having two pairs of grooves 30 and disposed on the corner area 29. For a trench ^ and =, at least a portion thereof will extend along the first direction or the second direction. According to Fig. 7, the conductive ring 28 located at the corner area 29 has at least two L-shaped grooves 30. A Figure 9 shows a top view of a second opening pattern of the conductive ring 28. The conductive ring 28 located at the corner region 29 includes two rows of holes, and the manner of the holes may extend along the first peripheral region 271 or the second peripheral region 271I. According to Figure 9, the two rows of holes are arranged in an L-shape. The 10A to 10C drawings show a top view in which the conductive ring having the opening pattern is combined with the design rule of the aforementioned idle area. The elements similar to those shown in Figs. 3A to 3C and Fig. 7 are omitted here. The first cutting lane 12 and the second cutting lane 14 located near the corner point P of the main area 26 define idle areas Μ, A2, a. s According to the design rule of the idle area, the test key 18 can be arbitrarily placed on any area of the first scribe line 12 and the second scribe line 14 other than the idle area \, A2, As.

1284934 V. INSTRUCTION DESCRIPTION (16) • As shown in Fig. 10A, the test key 18 can be arbitrarily placed. The area of the area Ai of any area other than the first scribe line 12 or the second scribe line 14 is defined by the following formula: Ai = h X \. It is also allowed to set a small test key 1 8 ' in the idle area a. However, the area ratio ratio defined by the following formula must be slightly less than 10%: &= W/Ai, where Μι represents the test key in the idle area Ai. The total area. As shown in FIG. 10B, the test key 18 can be arbitrarily placed on any area other than the first cut-out track 1 2 or the second cut-off track 14 other than the idle area A:. The area of the idle area A? is defined by the following formula: A X S2. The idle area ~ can also be set to a little test button 1 8, but the area ratio & defined by the following formula must be approximately less than 10%: R2 = Mg / 八2, where a is the test key set in the idle area A2 The total area of 1 8 . 2 μ, as shown in Fig. 10C, the test button 18 can be arbitrarily placed on any area of the first scribe line 12 or the second scribe line 14 other than the idle area 乂. The area of the idle area A is defined by the following formula: · As= \ x &. It is also allowed to set a little test button 1 in the idle area & 1 but the area ratio of 3 defined by the following formula must be no more than 1〇%: RS= Ms/As, where (' Generation 2 is set in the idle area As) The total area of the key 18. Although the present invention has been disclosed in the preferred embodiments as above, the bran is not intended to limit the invention to any of the skilled artisan, and may be used in some ways without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims.

1284934 BRIEF DESCRIPTION OF THE DRAWINGS * Fig. 1 is a top view showing a wafer of a first embodiment of the present invention. Figure 2 shows a schematic cross-sectional view of a multilayer structure of a wafer dicing street. Figure 3A is a top view of the first type of free area showing an idle area on a scribe line near a wafer. Figure 3B is a top view of a second type of free area showing an idle area on a scribe line near a wafer. Figure 3C is a top view of a third idle area showing an idle area on a scribe lane near a wafer. Figure 3D is a top view of a fourth idle area showing an idle area on a scribe line near a wafer. Figure 4 is a top view of a fifth idle area showing the idle area on the scribe line near the four corner points of a wafer. Figure 5 is a top view of the sixth idle area showing the idle area on the scribe line between the four wafers. Figure 6 is a top view of the seventh idle area showing the idle area on the scribe line between the four wafers. Figure 7 shows a top view of the first opening pattern of the conductive ring of the main area. Fig. 8 is a schematic cross-sectional view showing a pair of grooves along a tangent 8-8 of Fig. 7. Figure 9 shows a top view of a second opening pattern of the conductive ring. 10A to 10C are views showing a top view in which a conductive ring having an opening pattern is combined with a design rule of the aforementioned idle area.

0503-100051wF(η1); tsmc2003-0150; 1283; Cherry.ptd Page 24 1284934 Schematic description of the 'symbol description semiconductor wafer ~ 1 〇; first scribe line ~ 1 2; second scribe line ~ 1 4 ; Wafers ~1 6 , 1 6 I , 1 6 II , 1 6 III , 1 6 IV ; test keys ~1 8 ; substrate ~ 2 0 ; material layer ~ 2 1 , 2 2, 2 3 ; multilayer structure ~ 2 4 ; main area ~ 2 6 ; corner point ~ P, Pi, P2, P3, P4; idle area ~ Ai, A2, A3, A4, As; first peripheral area ~ 271; second peripheral area ~ 271 I; conductive ring ~ 28; corner area ~ 2 9 ; trench ~ 3 0 ; circuit area ~ 3 2 ; connection pad ~ 33.

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Claims (1)

1284934 1 . A multilayer semiconductor wafer structure using 'a plurality of wafers, the wafer structure comprising: a first scribe line fabricated thereon having a selected ° extension and adjacent to the plurality of wafers The second 曰 曰 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿Interleaving at one of the first wafer corners=two cutting lanes and the at least one idle area is defined on at least one of the first and second lanes, wherein a test key system j is forced to Two cut in the idle area. The hard breaking limit is set in the configuration, and the constant is as described in the first aspect of the patent application, wherein the dielectric layer of the multilayer semiconductor wafer structure is a thin layer of the germanium wafer. The layer is a low-dielectric structure. The dielectric constant of the dielectric layer of the low-k dielectric layer is less than 3. 〇. 5. The multilayer semiconductor wafer according to claim 2, wherein the dielectric constant of the dielectric constant is formed by chemical vapor deposition of Si〇c, Si〇CN formed by one of the following materials. a polymer material formed by chemical vapor deposition, which is formed by spin coating, a polymer material formed by chemical vapor deposition, a polymer material formed by = transfer coating, fluorocarbon glass (FSG), yttrium oxide (1⁄4) or Its combination material. 1284934 VI. Application for patent scope '6. If the patent application scope is the first structure, wherein the idle area 俜, the area A1 of the multilayer semiconductor wafer junction region is on the first scribe line, and the idle area is idle The table is from the first wafer. The first one is D1 and S1, where D1 is the system and the Si system represents the distance of the first cut "...the distance extending in the first direction. Loose. 7. If the patented 簕圊 ώ ώ 号 号 号 干 干 五 五 五 五 五 五 五 五 五 五 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层 多层8. The multilayer semiconductor wafer structure of claim 1, wherein the free area is defined in at least one of the top three layers of the multilayer semiconductor wafer structure. 9. The multi-layer semiconductor wafer structure described in claim 6 of the patent application, wherein the idle area is provided with one less test key, and the area ratio Pi of the test key and the side idle area conforms to the following formula: &; two M! / A! ' where Μι represents the total area of the test key in the idle area, and & is less than about 10%. 1 〇 · The multi-layer semiconductor wafer structure described in Section 6 of the patent application' wherein the distance h is approximately less than 6 〇 0 // m. 11. The multilayer semiconductor wafer structure of claim 6, wherein the width S! of the first scribe line is approximately greater than 20 #m. The multi-layer semiconductor wafer structure according to the above-mentioned patent application, wherein the multi-layer semiconductor wafer is formed on a substrate, and the 5-well substrate is composed of one of the following materials: · substrate 矽(bulk Si), germanium insulator (SOI), germanium telluride (SiGe), gallium arsenide (GaAs), indium phosphide 0503-10005 twF(η 1);t smc2003-0150;1283;Che r ry.pt d 201284934 6. Patent application scope (InP) or a combination thereof. The multi-layer semiconductor wafer structure of claim 1, wherein the first wafer comprises: a first peripheral region formed in the first wafer and parallel to the first scribe line a second peripheral region is formed in the first wafer and parallel to the second scribe line; a conductive ring is formed in the first wafer along the first peripheral region and the second peripheral region And an opening pattern formed in the conductive ring and adjacent to the corner region of the first wafer. The multi-layer semiconductor wafer structure of claim 13, wherein the opening pattern comprises The multi-layered semiconductor wafer structure of claim 13 wherein the opening pattern comprises two columns of holes. 1 6. As described in claim 13 The multilayer semiconductor wafer structure, wherein the opening pattern extends along at least one of the first peripheral region and the second peripheral region. 1 7. The multilayer semiconductor wafer junction according to claim 13 The first wafer includes a circuit region having a plurality of circuit units electrically connected to the circuit unit to provide a power supply voltage or a ground voltage to the circuit unit. The multilayer semiconductor wafer structure of claim 3, wherein the conductive ring has a width of 50 to 300 / / m. 0503-10005twF(η 1);t smc2003-0150;1283;Cherry.ptd Page 28 1284934 VI. Patent Application Scope 1 1. The multilayer semiconductor wafer structure described in claim 1 of the patent application, wherein the idle The zone is defined at the intersection of the first scribe line and the second scribe line, and the area 8.5 of the idle zone is defined by the following formula: As = Si X S2, wherein the Si system represents the width of the first scribe line, And S2 represents the width of the second scribe line. The multi-layer semiconductor wafer structure of claim 19, wherein at least one test key is disposed in the idle area, and an area ratio Rs of the test key and the idle area conforms to the following formula: Rs= Ms/As, wherein Ms represents the total area of the at least one test key in the idle area, and Rs is approximately less than 10%. 21. The multilayer semiconductor wafer structure of claim 19, wherein the width Si of the first scribe line and the width & amp of the second scribe line are both approximately greater than 20 //m. The multi-layer semiconductor wafer structure of claim 1, wherein the at least one idle area comprises: a first idle area defined on the first scribe line, and an area of the first idle area Defined by the following formula: Ai Di Di X Si, wherein Di represents a distance extending from the corner point of the first wafer in the first direction, and Si represents the width of the first scribe line; and a second The idle area is defined on the second scribe line, and the area A2 of the second idle area is defined by the following formula: A2 = D2 X S2, wherein D2 represents the second point from the corner point of the first wafer The distance in which the direction extends, and S2 represents the width of the second scribe line. 23 · Multilayer semiconductor wafer junction as described in claim 2 0503-10005twF(nl); tsmc2003-0150; 1283; Cherry.ptd page 29 1284934 6. Patent application scope, wherein the at least one idle area comprises: a third idle area defined by the first cut The intersection of the track and the second scribe line, and the area As of the third idle area is defined by the following formula: As = S! X S2 〇 24. The multilayer semiconductor wafer structure as described in claim 23 The method further includes: at least one test key disposed on the at least one of the first idle area, the second idle area, and the third idle area; wherein, the first area proportional core meets the following formula: Ratio = / Ai, where W is the total area of the at least one test key in the first idle area; wherein a second area ratio r2 conforms to the following formula: r2 = m2 / a2, wherein M2 represents the second a total area of the at least one test key in the idle area; wherein a third area ratio Rs conforms to the following formula: Rs = Ms / As, wherein Ms represents the total area of the at least one test key in the third idle area And wherein a ratio of the total area R satisfy the following equation: R = (+ M2 + Ms) / (A} + A2 + As). The multilayer semiconductor wafer structure of claim 24, wherein the first area proportional core is approximately less than 1%. The multilayer semiconductor wafer structure of claim 24, wherein the second area ratio R2 is approximately less than 10%. 2 7. A multilayer semiconductor wafer junction as described in claim 24 0503-10005twF(nl); tsmc2003-0150;1283;Cherry.ptd Page 30 1284934 6. Patent application scope, wherein the third area ratio is slightly less than 1%. 2 8 . The multilayer semiconductor wafer structure of claim 24, wherein the total area ratio r is approximately less than 1 〇 %. 2. The multilayer semiconductor wafer structure as described in claim 2, wherein the distance is approximately less than 6 〇 〇 # m. A multilayer semiconductor wafer structure as described in claim 2, wherein the distance D2 is approximately less than 6 〇 〇 #m. 3 1 · The multi-layer semiconductor wafer structure as described in claim 2, wherein the width of the first scribe line & is approximately greater than 20 // m. 3 2 - The multilayer semiconductor wafer structure as described in claim 2, wherein the width of the second scribe line & is approximately greater than 20 // m. A multilayer semiconductor wafer structure for defining a plurality of wafers fabricated thereon, the wafer structure comprising: a first scribe line having a selected width and along a first direction Extending; a brother-cutting track having a selected degree of I and extending in a first direction, wherein the second scribe line is interleaved with the first scribe line; four wafers are bound by the first scribe line The second dicing street is separated from each other by six, wherein each of the wafers includes a corner point, and the corner point is adjacent to the intersection of the first scribe line and the second scribe line, and the first idle area is The system is defined on the first scribe line and the corner point of the first wafer, and the surface of the first idle area is near the formula definition: Ai = D! XS!, wherein D is represented by the first曰1 takes the distance extending along the first direction with the following corner points, and the first cut of the n-table of the Si-separator 0503-10005twF(η 1); tsmc2003-0150; 1283; Cherry.ptd 31st buy 1284934 6. The width of the patent application ramp; ^ a second idle area, defined on the second cutting lane and adjacent to the a corner point of the second wafer, and an area a2 of the second idle area is defined by the following formula: A2 = D2 X S2, wherein D2 represents a distance extending in the second direction from the corner point of the second wafer, And s2 represents the width of the second scribe line; a third idle area is defined on the second scribe line and adjacent to the corner point of the third wafer, and the area A3 of the third idle area is defined by the following formula · A3 = XS? 'where Dg represents the distance extending from the corner point of the remote two wafers in the second direction; a fourth idle area is defined on the first scribe line adjacent to the fourth wafer a corner point, and an area A4 of the fourth idle area is defined by the following formula: A4 = D4 X Si , wherein D4 represents a distance extending from the corner point of the fourth wafer in the first direction; Five idle areas, And the area of the fifth idle area is defined by the following formula: As = Si X S2 〇 34. As described in claim 3, The multi-layer semiconductor wafer structure further includes: at least one test key disposed at least in the first idle area, the second idle area, the third idle area, the fourth idle area, and the fifth idle area a region; wherein, a first area proportional heart conforms to the following formula: heart = / Ai, wherein the total represents the total of the at least one test key in the first idle area 0503-10005twF(nl); tsmc2003-0150;1283;Cherry.ptd Page 32 1284934 VI. Patent scope • Area; wherein, a second area ratio r2 conforms to the following formula: R21= M2 / A2, where M2 represents a total area of the at least one test key in the second idle area; wherein a third area ratio R3 conforms to the following formula: R3=M3/A3, wherein M3 represents the at least one test key in the third idle area The total area of the fourth area is in accordance with the following formula: h 2 M4 / A4, wherein M4 represents the total area of the at least one test key in the fourth idle area; wherein, a fifth area ratio Rs meets The following formula: Rs = Ms / As, where Ms represents the total area of the at least one test key in the fifth idle area; and wherein a total area ratio R conforms to the following formula: R = (+M2 + M3 + M4 + Ms) / (A} + A2 + A3 + A4 + As) 0 3 5 . The multilayer semiconductor wafer structure of claim 4, wherein the first area proportional core is approximately less than 10% . The multilayer semiconductor wafer structure of claim 3, wherein the distance D4 is approximately less than 60 0 // m. The multi-layer semiconductor wafer structure of claim 3, wherein the width Si of the first scribe line is approximately greater than 20 // m. 38. The multilayer semiconductor wafer structure of claim 3, wherein the width S2 of the second scribe line is approximately greater than 20 // m. 3 9 · Multilayer semiconductor wafer junction as described in claim 3 0503 -10005 twF(η 1);t smc2003-0150;1283;Che r ry.ptd page 33 1284934 6. The scope of the patent application, wherein the multilayer semiconductor wafer structure is formed on a substrate, the substrate system It consists of one of the following materials: ·BuIk Si, 矽Insulator (SOI), bismuth telluride (siGe), gallium arsenide (GaAs), indium phosphide (InP) 〇4 0 ·Applicable to the scope of patent application The multilayer semiconductor wafer structure of claim 3, wherein one of the mother wafers includes a first peripheral region parallel to the first/cutting channel 'a second peripheral region, which is parallel to the first, and the tangent track' A conductive ring is formed in the wafer along the first peripheral region and the far first peripheral region; and an opening pattern is formed in the conductive ring and adjacent to a corner region of the wafer. 41. The multilayer semiconductor wafer structure of claim 3, wherein at least one of the plurality of semiconductor wafer structures is a low dielectric constant dielectric layer, and the low dielectric constant dielectric 5。 The dielectric constant of the layer is approximately less than 3.5. The multilayer semiconductor wafer according to the fourth aspect of the invention, wherein the opening pattern comprises two rows of holes, and the multilayer semiconductor wafer according to the fourth aspect of the patent application. The opening pattern includes at least a rain trench. The multi-layer semiconductor wafer structure of claim 4, wherein the opening pattern extends in at least one of the first rim region and the second peripheral region. 4 5 ·Multilayer semiconductor wafer junction as described in Clause 4 of the patent application 0503-10005twF(η1); tsmc2003-0150; 1283; Cherry.ptd 34th buy 1284934 6. Patent application scope, wherein each wafer includes an electric_road area having a plurality of circuit units, the conductive ring is electrically Connected to the circuit unit to provide a power supply voltage or a ground voltage to the circuit unit. 4 6. The multilayer semiconductor wafer structure of claim 40, wherein the conductive ring has a width of 50 to 300/zm. 47. A method of fabricating a multilayer semiconductor wafer structure for defining a plurality of wafers fabricated thereon, the method of manufacturing comprising the steps of: providing a semiconductor wafer comprising a a scribe line and a second scribe line, wherein the intersection of the first scribe line and the second scribe line defines a corner point of a wafer; defining the first cut of the idle area near the corner point of the wafer In the track, wherein the idle area limits a test button; and a cutting process is performed on the first scribe line and the second scribe line to separate the wafer. 4. The method of fabricating a multilayer semiconductor wafer structure according to claim 47, wherein the cutting process uses one of the following cutting methods: diamond cutting, laser cutting, jet cutting, water jet cutting or the above cutting. a combination of ways. 49. The method of fabricating a multilayer semiconductor wafer structure according to claim 47, wherein at least one of the plurality of semiconductor wafer structures is a low dielectric constant dielectric layer, and the low dielectric constant 5。 The dielectric constant of the dielectric layer is approximately less than 3.5. 5 0 · Multilayer semiconductor wafer junction as described in claim 49 0503 -100051wF(η 1);t smc2003-0150;1283;Che rr yp td Page 35 1284934 VI. Patent application scope ~~1 Manufacturing method, wherein the low dielectric constant dielectric layer is composed of the following A '1 shell> consists of: Si〇C, Si OCN formed by chemical vapor deposition, s丨〇c formed by spin coating, and polymer material formed by chemical fluorine phase deposition. The polymer material formed by the cloth, fluorocarbon glass (FSG), oxidized stone (Si〇2) or a combination thereof. The manufacturing method of the multilayered semiconductor wafer structure of claim 47, wherein the idle area is defined on the first scribe line and the area of the vacant area is defined by the following formula: h XI 'where Di represents the distance along the first scribe line from the corner point of the wafer, and Si represents the width of the first scribe line. The manufacturing method of the multi-layer semiconductor wafer structure of claim 51, wherein the idle area is provided with at least one test key 'and the area ratio of the test key to the idle area & Formula: R, where 4 represents the total area of the at least one test key within the idle area, and & is approximately less than 1%. The manufacturing method of the multilayered semiconductor wafer structure according to claim 51, wherein the distance Di is approximately less than 600 " m. The manufacturing method of the multilayered semiconductor wafer structure according to claim 51, wherein the width si of the first scribe line is approximately greater than 20 0 m ° 5 5 · as claimed in item 47 The method for fabricating a multilayer semiconductor wafer structure, wherein the multilayer semiconductor wafer structure is formed on a substrate, and the substrate is composed of one of the following materials: a bulk silicon Si, a germanium insulator (SOI) ), 矽化锗(SlGe), deuterated gallium 0503-10005twF(η 1); tsmc2003-0150; 1283; Cherry.ptd 1284934 Sixth, the scope of application for patent (GaAs), filling indium (InP). The method of manufacturing a multilayer semiconductor wafer structure according to claim 47, further comprising the steps of: defining a first peripheral region in the wafer, the first peripheral region being parallel to the first a dicing street; defining a second peripheral region in the wafer, the second peripheral region being parallel to the second scribe line; forming a first peripheral region and the second peripheral region that are electrically conductive from the wafer; and forming An opening pattern is in the conductive ring, and the opening pattern is adjacent to a corner area of the wafer. 5. The method of fabricating a multilayer semiconductor wafer structure according to claim 56, wherein the opening pattern comprises at least two trenches. 58. A method of fabricating a multilayer semiconductor wafer structure according to claim 56, wherein the opening pattern comprises two columns of holes. The manufacturing method of the multilayer semiconductor wafer structure of claim 56, further comprising a step of: connecting the conductive ring to the circuit unit of the chip, and connecting a power terminal to the conductive ring . The manufacturing method of the multi-layer semiconductor wafer structure of claim 59, wherein before the cutting process, an idle area is defined at the intersection of the first scribe line and the second scribe line, and The area As of the idle area is defined by the following formula: As di Si X S2, wherein Si represents the width of the first scribe line, and S2 represents the width of the second scribe line; 0503-10005twF(η 1); tsmc2003-0150; 1283; Cherry.ptd Page 37 1284934^ 6. In Patent Application No. 2, at least one test button is disposed in the idle area, and the test key is in the idle area. The area ratio I conforms to the following formula: Rs = Ms / As, where Ms represents the total ▲ product of the at least one test button in the idle region and Rs is approximately less than 1 〇%. The method of fabricating a multilayer semiconductor wafer according to claim 59, wherein the first scribe line has a width Si that is approximately slightly larger: 20 // m. 62. The method of fabricating a multilayer semiconductor wafer structure according to claim 59, wherein the second cutting prop has a width S2 that is approximately greater than 20 // m 〇, 63. as described in claim 47. The manufacturing method of the multi-layer semiconductor wafer structure, wherein the idle area is defined by the intersection of the first scribe line and the two dicing streets, and the area of the vacant area is defined by the following formula: As = Si X S2, wherein Si is the width of the first scribe line and S2 is the width of the second scribe line. 64. The method of fabricating a multilayer semiconductor wafer structure according to claim 63, wherein the step of defining the idle region further comprises: defining a first idle region on the first scribe line, and the The area of an idle area is defined by the following formula: A 〆 Di x &, where h is " represents ° ° from the corner point of the wafer, the distance from the first scribe line extends, and defines a second idle area is on the second scribe line, and an area A2 of the set area is defined by the following formula: 込χ &, representing a distance from the corner of the wafer extending along the second scribe line . 0503-10005twF(nl);tsmc2003-0150;1283;Cherry.ptd