1284969 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體封裝技術，尤指一種製程以及一種簡易 覆曰曰組裝結構’用以強化晶片（die)以及底膠（underfill encapsulant material)間之結合，其中部分金屬層被氧化以確保該底部填充材料 可與該部分金屬層形成可靠結合。 【先前技術】1284969 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor packaging technology, and more particularly to a process and a simple overlay assembly structure for reinforcing a die and an underfill encapsulant material. In combination, a portion of the metal layer is oxidized to ensure that the underfill material can form a reliable bond with the portion of the metal layer. [Prior Art]
I960年代，IBM首次將利用錫鉛材料進行銲墊 (bond pads)連接的覆晶結構（Flip chip )，引入商業運 用的領域。在覆晶領域中，錫鉛銲塊技術與其他覆晶技 術相較擁有最長的生產歷史、最高的生產量以及最充分 的可靠度資料。近來錫鉛銲塊覆晶製程的成本日低，擴 大了覆晶技術的應用層面，並使得運用覆晶技術的產品 得以進入市場。 覆晶的製程基本上可包含以下四個步驟··備妥一晶 圓用以於其上生成錫鉛凸塊；形成並置放該錫鉛凸塊 於該晶圓；切割晶圓形成含有凸塊之晶片：將包含錫鉛 凸塊的晶片與基板或載體連結；於上述結構中填入黏合 用的底膠（Underfill)。 習知的覆晶製程技術，可引用例如美國專利證書號 6,787,903揭露之—個包含銲塊底部金屬化及其製程的 習知半導體裝置做進一步說明，該習知技術敘述於下： 挣2參Γ第半1圖’一半導體晶片looji形成-錫錯凸 塊15〇’第—步驟為於該半導體晶片1GG的-銲墊11〇 士，形成一個銲塊底部金屬化結構130。該銲塊底部金 ;:結構13°包含-黏著層⑽，可為一二層金 m該連接’u〇上；-擴散障礙層，可為一 ί二Γ，形可ΓΓ著層i3Ga之上；以及-濕潤 曰 -、銅金屬層，形成於該擴散障礙層 1284969 130b之上。錫鉛材料可被應用於該濕潤接合層130c ^，並透過回銲（Ren〇w)程序以於該銲塊底部金屬化 結構130上形成一錫鉛凸塊15〇。這個銲塊底部金屬化 結構1 30可視為擴散障礙層，並於該錫鉛凸塊1以及 該銲墊110之間提供適當的附著力。 第2A至第2E圖係為一習知之製程技術，用以於 覆晶結構上形成一錫鉛銲塊。請參考第2A圖所示，準 備一半導體晶片100，該半導體晶片100包含複數銲墊 110形成於其表面上，一保護層120覆蓋於該半導體晶 片100之表面。該保護層120被選擇性的移除以暴露該 半導體晶片100上的該複數銲墊110。其後，施加濺鍍 (Sputtering)與電鍍（Plating)程序以使得任一個銲 墊110上均形成一銲塊底部金屬化結構13〇。 請參考第2B圖，一錫鉛遮罩薄膜（Dry film) 14〇， 該錫鉛遮罩薄膜可為一乾燥薄膜，應用於該保護層12〇 上並形成複數開口 141以暴露該銲塊底部金屬化結構 130 ° 請參考第2C圖’隨後施加一銲料塗佈程序，該程 序係藉由網版印刷或其他塗佈技術，於複數開口 141中 填充知料（Solder paste )’該銲料可為錫錯合金材料， 覆蓋於該銲塊底層金屬130上，以分別於該銲塊底層金 屬130上形成複數銲塊150。 一 如第2D圖所示，為一第一回銲程序，用以完成該 銲塊底層金屬化結構13 0與該複數銲塊丨5 〇的電性輕 合。如第2E圖所示’隨後剝除（Strip)該錫鉛遮罩薄 膜’該銲塊150透過一第一回銲程序形成球形。 接著將晶另接置在基板之上，經過回銲程序後，將 晶片藉凸塊的熔融產生電性結合，其後以底膠填入晶片 與基板之間，以填滿凸塊間之空隙。 1284969 曰^述習知覆晶結構與製程中的底膠技術，係用以於 =片/、基底間形成機械結合力，使得不同材料間不同的 …、膨脹係數不至於損毁或損壞凸塊間的電性連接。底膠 的利用可在—定的程度内，延長錫錯凸塊的使用壽命。 =覆晶結構可靠度提升的需要，用以強化接合端點的 技術也不斷被提出。 例如美國專利證書冑5,72G，1GG、纟國專利證書號 6,〇74,895以及美國專利證書號6,372,544，揭露了一個 包含覆晶底膠的覆晶結構，該結構用以強化該接合端點 而不影響其電性連接並且減低熱形變力對該覆晶結構 的影響，其中該積體電路藉由錫鉛銲塊與晶片載體連 接，並使用一聚合物材料進行封裝，這樣的技術延長了 該組裝結構的使用壽命。 然而，上述習知技術中，需要使用不同的底膠以滿 足不同的保護層材料所需。習知上常見的保護層可為任 何絕緣材料，但其較佳者為一聚合物，例如聚醯亞胺、 矽基氧化物與矽基氮化物等。也因此導致了製程的過度 $雜以及因為材料間揚氏係數或是熱膨脹係數差異所 造成的脫層（delamination)問題。總結來說，習知技 術無法有效解決積體電路上的保護層與底膠間因材料 特性所造成的脫層問題，僅能利用不同的底膠材料來減 少脫層現象的發生，當擁有低熱膨脹係數或者低揚氏 (彈性）係數的底膠材料，被應用以解決脫層的問題 時，卻也衍生出低揚氏係數的底膠材料，未能對覆晶結 構提供足夠機械保護力的新問題。此外，針對不同的保 護層需要提供不同底膠材料的狀況，也大大增加了製程 的複雜度’從而使得生產成本提高並降低了覆晶結構的 可靠度。 為了充分地提高覆晶組裝結構的可靠性與電性效 1284969 能，使得在不增加製程滿M电从作从 更卢妯蚀用表％硬雜度的條件下，覆晶技術可以 更廣乏的被使用，-個心防止底膠與該 發生脫層問題的方法是十分被需要的。的表面間 【發明内容】 本發明之主要目的係提供一簡易之底膠封裴製 程，用以充分地提高—覆晶結構的可靠度，且無須隨著 不同保護層（pasSivationlayer)而更換*同底膠，、使覆 晶技術的應用更加普及，並提供一個方法，用以預防該 底膠與-晶片（dle)(或一積體電路（心以咖山㈤⑴ 之表面間發生脫層現象。 本發明之另一目的係利用一晶片（或一積體電路） 上之氧化亞銅層或氧化銅層與底部填充材料形成良好 鍵結，以減低發生於該底膠與該晶片上保護層間常見的 脫層問題。該底膠可與該晶片上的氧化亞銅層或氧化銅 層以及該載體形成良好鍵結，以提高該覆晶結構的可靠 度。因此，該覆晶結構中因為揚氏係數或是熱膨脹係數 差異而產生的脫層問題可以被克服解決。 本發明之另一目的係提供一簡易覆晶組裝結構用 以減少製程的複雜性以及因為熱膨脹係數（c〇efficient of thermal expansion)或是揚氏係數（Y〇ung，s Module) 差異所造成的脫層現象。 本發明之另一目的係提供一製造方法用以強化一 晶片（die)(或一積體電路（integrated circuit))與一 底膠間之鍵結以防止脫層現象的發生。 因此，為達成上述目的，本發明提供一種覆晶組裝 結構，包含： 一半導體裝置，包含： 一晶片，具有一銲墊形成於該晶片之一側表 1284969 面； 一保濩層’形成於該晶片以及該銲墊之表面 上’其中該保護層形成一銲墊開口 （ b〇nd pad opening)用以暴露該銲墊； 一金屬銲塊；In the 1960s, IBM introduced the Flip chip, which uses tin-lead materials for bond pads, for commercial applications. In the field of flip chip, tin-lead solder bump technology has the longest production history, highest throughput and the most reliable reliability data compared to other flip chip technologies. Recently, the cost of the tin-lead solder bump flip-chip process has been low, which has expanded the application of flip chip technology and enabled the use of flip chip technology to enter the market. The flip chip process basically comprises the following four steps: preparing a wafer for forming a tin-lead bump thereon; forming and placing the tin-lead bump on the wafer; and cutting the wafer to form a bump Wafer: A wafer containing tin-lead bumps is bonded to a substrate or a carrier; and an underfill for bonding is filled in the above structure. The conventional flip-chip process technique can be further described by, for example, a conventional semiconductor device including solder bump bottom metallization and its process as disclosed in U.S. Patent No. 6,787,903, which is incorporated herein by reference. The first half of FIG. 1 'a semiconductor wafer looji formation - tin bumps 15 〇 ' the first step is for the semiconductor wafer 1GG - pad 11 gentleman, forming a solder bump bottom metallization structure 130. The bottom of the solder bump is gold; the structure 13° contains an adhesive layer (10), which can be a layer of gold m, which is connected to the 'u〇; the diffusion barrier layer can be a two-dimensional layer, which can be placed on top of the layer i3Ga And a wet tantalum-, copper metal layer formed over the diffusion barrier layer 1284969 130b. A tin-lead material can be applied to the wet bonding layer 130c^ and through a reflow process to form a tin-lead bump 15 on the solder bump bottom metallization structure 130. This solder bump bottom metallization structure 130 can be considered a diffusion barrier layer and provides suitable adhesion between the tin-lead bump 1 and the pad 110. 2A through 2E are conventional process techniques for forming a tin-lead solder bump on a flip chip structure. Referring to FIG. 2A, a semiconductor wafer 100 is prepared. The semiconductor wafer 100 includes a plurality of pads 110 formed on a surface thereof, and a protective layer 120 covers the surface of the semiconductor wafer 100. The protective layer 120 is selectively removed to expose the plurality of pads 110 on the semiconductor wafer 100. Thereafter, a sputtering and plating process is applied to form a solder bump bottom metallization structure 13 on either of the pads 110. Referring to FIG. 2B, a tin-lead film (Dry film) 14〇, the tin-lead mask film may be a dry film applied to the protective layer 12〇 and forming a plurality of openings 141 to expose the bottom of the solder bump. Metallized structure 130 ° Please refer to FIG. 2C 'subsequent application of a solder coating procedure for filling a plurality of openings 141 with a solder paste by screen printing or other coating technique. A tin-staggered alloy material is overlaid on the under-metal 130 of the solder bump to form a plurality of solder bumps 150 on the under-metal 130 of the solder bump. As shown in Fig. 2D, it is a first reflow process for completing the electrical coupling of the underlying metallization structure 130 of the solder bump with the plurality of solder bumps 丨5 。. The tin-lead mask film is subsequently stripped as shown in Fig. 2E. The solder bump 150 is formed into a spherical shape by a first reflow process. Then, the crystal is further connected to the substrate. After the reflow process, the wafer is electrically bonded by the melting of the bumps, and then filled with the primer between the wafer and the substrate to fill the gap between the bumps. . 1284969 习^ The conventional flip-chip structure and the primer technology in the process are used to form a mechanical bond between the film and the substrate, so that different materials... Electrical connection. The use of the primer can extend the service life of the tin bumps to a certain extent. = The need to increase the reliability of flip chip structures, and techniques for enhancing the joint end points have also been proposed. For example, U.S. Patent No. 5,72, G, 1 GG, PCT Patent No. 6, 〇 74, 895, and U.S. Patent No. 6,372, 544 disclose a flip-chip structure comprising a flip chip for reinforcing the joint end. Does not affect its electrical connection and reduces the influence of thermal deformation force on the flip chip structure, wherein the integrated circuit is connected to the wafer carrier by a tin-lead solder bump and encapsulated using a polymer material, such a technique extends the The service life of the assembled structure. However, in the above prior art, it is necessary to use different primers to meet the requirements of different protective layer materials. A conventional protective layer may be any insulating material, but it is preferably a polymer such as polyimine, sulfhydryl oxide and fluorenyl nitride. As a result, the process is excessively confusing and the delamination problem is caused by the Young's coefficient between materials or the difference in thermal expansion coefficient. In summary, the conventional technology cannot effectively solve the delamination problem caused by the material properties between the protective layer and the primer on the integrated circuit, and only the different primer materials can be used to reduce the occurrence of delamination. A primer material with a coefficient of thermal expansion or a low Young's (elasticity) coefficient is applied to solve the problem of delamination, but a primer material with a low Young's modulus is also derived, failing to provide sufficient mechanical protection for the flip chip structure. New question. In addition, the need to provide different primer materials for different protective layers also greatly increases the complexity of the process', thereby increasing production costs and reducing the reliability of the flip chip structure. In order to fully improve the reliability and electrical effect of the flip-chip assembly structure, the 1284969 energy can make the flip chip technology more versatile without increasing the process full M power from the more difficult conditions. The method used to prevent the primer and the delamination problem is very much needed. BACKGROUND OF THE INVENTION The main object of the present invention is to provide a simple primer sealing process for fully improving the reliability of the flip chip structure without replacing it with different protective layers (pasSivationlayer). Primer, which makes the application of flip chip technology more popular, and provides a method to prevent delamination between the primer and the dle (or a integrated circuit (the surface of the heart of the mountain). Another object of the present invention is to form a good bond with an underfill material by using a cuprous oxide layer or a copper oxide layer on a wafer (or an integrated circuit) to reduce the occurrence of common between the primer and the protective layer on the wafer. Debonding problem. The primer can form a good bond with the cuprous oxide layer or the copper oxide layer on the wafer and the carrier to improve the reliability of the flip chip structure. Therefore, in the flip chip structure, because of the Young's The delamination problem caused by the coefficient or the difference in thermal expansion coefficient can be overcome. Another object of the present invention is to provide a simple flip-chip assembly structure for reducing the complexity of the process and because of thermal expansion. The delamination phenomenon caused by the difference in coefficient of thermal expansion or the Young's coefficient (Y Module). Another object of the present invention is to provide a manufacturing method for strengthening a die ( Or an integrated circuit is bonded to a primer to prevent delamination. Therefore, in order to achieve the above object, the present invention provides a flip chip assembly structure comprising: a semiconductor device comprising: a wafer having a pad formed on one side of the wafer 1284969; a protective layer 'on the wafer and the surface of the pad' wherein the protective layer forms a pad opening (b〇nd pad opening ) for exposing the pad; a metal solder bump;
一銲塊底部金屬化（under bUmp metallurgy UBM)結構層，包含複數金屬層，該銲塊底部金屬 化結構層覆蓋該銲墊以及該銲墊周圍的部分該保 遵層’其中該金屬銲塊形成於該銲塊底部金屬化結 構層上，覆蓋該銲墊開口及其周圍區域；以及 一外部結構’包含該複數金屬層，且該外部結 構未被該金屬銲塊所覆蓋，其中該外部結構之表^ 被氧化以形成一氧化層； 基板’藉由該金屬鲜塊與該半導體裝置連接，且 該金屬銲塊係電連接該基板上之一接觸塾（ pad)與該晶片上相對應之銲墊，因而形成一空間，該 空間介於該氧化層與該基板的表面之間；以及 一底部填充材料用以填滿該空間。An underbout metallurgy UBM structural layer comprising a plurality of metal layers, the bottom metallization structure layer of the solder bump covering the solder pad and a portion of the solder pad surrounding the solder pad And covering the pad opening and its surrounding area on the bottom metallization layer of the solder bump; and an external structure 'comprising the plurality of metal layers, and the outer structure is not covered by the metal solder bump, wherein the outer structure is The surface is oxidized to form an oxide layer; the substrate ' is connected to the semiconductor device by the fresh metal block, and the metal solder bump is electrically connected to one of the contact pads on the substrate and the corresponding solder on the wafer The pad thus forms a space between the oxide layer and the surface of the substrate; and an underfill material to fill the space.
^為使本發明上述之目的、特徵以及優點更為明顯易 懂，將由下述之詳細說明、圖式以及申請專利範圍做一 更清楚說明。 【實施方式】 第3圖所示為本發明較佳實施例中，一覆晶半導體 組裝結構200之剖面示意圖，該覆晶半導體組裝結構 200包含一半導體裝置以及一基板28〇。該半導體裝置 包含一晶片210。於本實施例中，該晶片21〇包含一晶 片表面211，該晶片表面211具有複數銲墊22〇a、 220B(為簡化表示，圖例中僅顯示兩個銲墊）。該半導體 裝置與該基板280結合以形成一覆晶結構，其中該基板 1284969 280包含接觸塾（contact pads ) 281A以及281B。該複 數銲墊220A、 220B以使用銅材質之銲墊為最佳，但 不限於使用銅材質之銲墊。 該半導體裝置包含一保護層（passivation layer) 23 0、 複數銲塊底部金屬化（under bump metallurgy，UBM)結構層 250A以及250B、一外部結構251，該外部結構251係 部分圍繞存在於該銲塊底部金屬化結構層250A之外 圍，另一外部結構252以及253係為該銲塊底部金屬化 結構層250B之延伸，且氧化層257係形成於該外部結 構251、252、253之表面上。該保護層230係覆蓋於該 晶片表面211以及該鲜塾220A以及220B之部分區域。 該保護層230可為任何絕緣材料但較佳者為一聚合 物，例如聚醯亞胺、矽基氧化物與矽基氮化物等。換言 之，該保護層230係為一介電層。該保護層230包含複 數銲墊開口（ bond pad opening)，該銲墊開口用以暴露其下 之該銲墊21 0A以及210B。複數金屬層形成於該保護層 230以及該銲塾220A、220B之上方，並且提供該複數 金屬層以及該銲墊220A、220B間良好的黏著力。此外， 該複數金屬層包含複數開口 244、245、246以及247(如 第5圖所示），用以形成該銲塊底部金屬化結構層 250A、250B以及複數外部結構251、252以及253。換 句話說，該複數外部結構251、252、253以及該銲塊底 部金屬化結構層250A、250B較佳情況下具有相同金屬 層，但不限於上述之情況。因此，由於該複數金屬層之 最上層表面可被視為一接地平面，並未電連接該銲墊 220A，因此該銲墊22〇A可被視為一獨立銲墊（如啦 Pad)。另一方面，由於該複數金屬層之最上層表面可被 視為^接地平面，電連接該銲墊22〇B，因此該銲墊22〇b 可被視為一接地銲墊（。因此，本發明提供一 1284969 覆晶半導體組裝結構具有一大接地平面，用以增進該結 構的電性效能。 再者，如第4C圖以及第4D圖所示，為本發明較 佳實施例中之複數金屬層，該複數金屬層較佳情況下具 有三層金屬層結構，但不限於上述之情況。於本實施例 中’該衩數金屬層包含一第一金屬層240a、一第二金 屬層240b以及一第三金屬層240c。該第一金屬層形成 於該保護層230以及該複數銲墊220A、220B上方，並 提供該第一金屬層240a以及該複數銲墊220 A、220B • 之間良好的黏著力。該第一金屬層24〇a較佳情況下係 為一鈇（Ti)金屬層，但不限於鈦（丁丨）金屬層。該第 一金屬層240a亦可為一鋁金屬層。該第二金屬層24〇b 形成於該第一金屬層240a之上以覆蓋該第一金屬層 240a。該第二金屬層240b較佳情況下係為一鎳（Ni) 金屬層，但不限於鎳（Ni)金屬層。該鎳金屬層沈積於 該鈦金屬層之上做為一障礙層（barrier layer)用以防止介金 屬化合物（Intermetallic compounds )的產生，該介金 屬化合物係由錫鉛元素以及該銲墊反應生成。該第三金 屬層240c形成於該第二金屬層24〇b之上。該第三金屬 Φ 層240e較佳情況下係為銅（Cu)金屬層。最後，一銅金 屬層施加於該鎳（Ni)金屬層之上以使該錫鉛銲塊可成 功的與該結構240耦合。因此，該第三金屬層24〇c除 了提供足夠的保護給該第二金屬層240b，更提供良好 的潤濕效應給複數銲塊270A以及270B (如第4G圖與 第4H圖所示），隨後使該複數銲塊容易於黏著於該結構 240。值得注意的是，本發明並不限於任何特別或多層 化之銲塊底部金屬化（under bump metallurgy，UBM)結構層。The above detailed description, the drawings, and the claims are intended to be more clearly understood. [Embodiment] FIG. 3 is a schematic cross-sectional view showing a flip-chip semiconductor package structure 200 according to a preferred embodiment of the present invention. The flip chip semiconductor package structure 200 includes a semiconductor device and a substrate 28A. The semiconductor device includes a wafer 210. In the present embodiment, the wafer 21A includes a wafer surface 211 having a plurality of pads 22A, 220B (for simplicity of illustration, only two pads are shown in the legend). The semiconductor device is bonded to the substrate 280 to form a flip chip structure, wherein the substrate 1284969 280 includes contact pads 281A and 281B. The plurality of pads 220A and 220B are preferably made of a copper pad, but are not limited to copper pads. The semiconductor device includes a passivation layer 23 0, an under bump metallurgy (UBM) structural layer 250A and 250B, and an outer structure 251 partially surrounding the solder bump. The periphery of the bottom metallization structure layer 250A, the other outer structures 252 and 253 are extensions of the solder bump bottom metallization structure layer 250B, and the oxide layer 257 is formed on the surface of the outer structure 251, 252, 253. The protective layer 230 covers the wafer surface 211 and portions of the sputum 220A and 220B. The protective layer 230 can be any insulating material but is preferably a polymer such as polyimide, cerium-based oxide and cerium-based nitride. In other words, the protective layer 230 is a dielectric layer. The protective layer 230 includes a plurality of bond pad openings for exposing the pads 21A and 210B thereunder. A plurality of metal layers are formed over the protective layer 230 and the pads 220A, 220B and provide a good adhesion between the plurality of metal layers and the pads 220A, 220B. In addition, the plurality of metal layers includes a plurality of openings 244, 245, 246, and 247 (as shown in FIG. 5) for forming the solder bump bottom metallization structure layers 250A, 250B and the plurality of outer structures 251, 252, and 253. In other words, the plurality of outer structures 251, 252, 253 and the solder bump bottom metallization layers 250A, 250B preferably have the same metal layer, but are not limited to the above. Therefore, since the uppermost surface of the plurality of metal layers can be regarded as a ground plane and the pad 220A is not electrically connected, the pad 22A can be regarded as a separate pad (e.g., a pad). On the other hand, since the uppermost surface of the plurality of metal layers can be regarded as a ground plane, electrically connecting the pads 22B, the pads 22〇b can be regarded as a ground pad (. Therefore, The invention provides a 1284969 flip-chip semiconductor assembly structure having a large ground plane for enhancing the electrical performance of the structure. Furthermore, as shown in Figures 4C and 4D, the plurality of metals in the preferred embodiment of the present invention Preferably, the plurality of metal layers have a three-layer metal layer structure, but are not limited to the above. In the present embodiment, the plurality of metal layers include a first metal layer 240a and a second metal layer 240b. a third metal layer 240c. The first metal layer is formed over the protective layer 230 and the plurality of pads 220A, 220B, and provides a good relationship between the first metal layer 240a and the plurality of pads 220 A, 220B. The first metal layer 24A is preferably a tantalum (Ti) metal layer, but is not limited to a titanium (butadiene) metal layer. The first metal layer 240a may also be an aluminum metal layer. The second metal layer 24〇b is formed in the first gold The layer 240a is overlying the first metal layer 240a. The second metal layer 240b is preferably a nickel (Ni) metal layer, but is not limited to a nickel (Ni) metal layer. The titanium metal layer acts as a barrier layer for preventing the formation of intermetallic compounds which are formed by reacting tin-lead elements and the pad. The third metal layer 240c is formed. The second metal Φ layer 240e is preferably a copper (Cu) metal layer. Finally, a copper metal layer is applied over the nickel (Ni) metal layer. The tin-lead solder bump can be successfully coupled to the structure 240. Therefore, the third metal layer 24c provides a good wetting effect to the plurality of solder bumps 270A in addition to providing sufficient protection to the second metal layer 240b. And 270B (as shown in Figures 4G and 4H), which subsequently facilitates adhesion of the plurality of solder bumps to the structure 240. It is noted that the invention is not limited to any special or multilayer solder bump bottom metallization. (under bump metallurgy, UBM) structural layer .
因此，因為複數外部結構251、252以及253之銅 金屬層240c並未被複數銲塊270A以及270B(如第4H Ϊ284969 圖所示）所覆蓋，所以該複數外部結構25丨、252以及 253之銅金屬層24〇c係暴露於外以形成一氧化亞銅層 或是氧化銅層257在該複數外部結構251、252以及253 之表面。 • 請參考第3圖，一底膠290被用以填滿該晶片210 以及該基板280之間的空間。此過程可利用一習知的填 充材料或填充製程加以實現。該底膠290被直接注入該 晶片210之下，並藉由毛細作用填滿該晶片210以及該 基板280之間的空間。 如前所述，包含底膠的覆晶結構中最大的問題，在 攀 於該保護層以及該底膠間的介面脫層現象。基於需配合 保護層（例如氮化矽或聚合物材料）的不同而更換不同 的底膠的原因，習知技術利用不同的底膠以填充介於晶 片與基板之間空間的製程是相當複雜的。本發明利用該 第二金屬層240c中的氧化亞銅或氧化銅層257與該底 膠290形成良好鍵結。以此結果，該底膠29〇可與該第 三金屬層240c中的氧化亞銅或氧化銅層257以及該基 板2 80均形成良好鍵結。因此，即使本發明中並未使用 不同的底部填充材料以減輕保護層與底膠材料間發生 • 的脫層問題，本發明中，包含底膠的覆晶結構已克服肇 因於揚氏係數或是熱膨脹係數不同而產生的脫層問 題三總括來說，本發明利用該第三金屬層中的氧化亞銅 或氧化銅層2 5 7與該底膠形成良好鍵結以預防該晶片 以及底膠結構間脫層現象的發生。總之，本發明提供一 簡單的封膠製程以充分地提高覆晶結構的可靠性，且無 須隨著不同保護層而更換不同底膠’以使覆晶技術的應 用更加普及。 更進一步來說，該晶片210可為一積體電路。同 時，該基板280以及接觸墊（contactpads) 28lA以及 12 1284969 2 8 1B亦可為印刷電路版的一部份，其中於錫鉛銲塊以 及接觸塾間產生的鍵結係同時考慮到該積體電路以及 印刷電路板間的機械與電性連接。 第4A圖至第4E係為本案上述較佳實施例之製程 與結構示意圖，用以形成一錫鉛銲塊於一包含銲塊底部 金屬化結構層之覆晶結構上。第4A圖係為該晶片21〇 之部分剖面示意圖。本實施例中，該晶片210可為一半 導體裸晶，包含該晶片表面211。該晶片21〇包含複數 銲墊220A、220B ((為簡化表示，圖例中僅顯示兩個銲 墊），該半導體裝置與一基板280結合以形成一覆晶結 構。該基板包含接觸墊281A以及281B。該複數銲墊 220A、220B以使用銅材質之銲墊為最佳，但不限於使 用銅材質之銲墊。 如第4B圖所示，一保護層23〇係覆蓋於該晶片表 面211以及該複數銲墊220A、 220B之上。該該保護 層230可為任何絕緣材料但較佳者為一聚合物，例如聚 醯亞胺、矽基氧化物與矽基氮化物等。換句話說，該保 護層230為一介電層。該保護層23〇隨後進行光阻塗 布、光罩、顯影以及蝕刻以形成銲墊開口 23丨A以及 23 1B，該銲墊開口用以暴露其下的該銲墊22〇a以及 220B。光罩剩餘部分隨後被完全移除以完整暴露該保護 層 230 〇 如第4C圖所示，該第一金屬層24〇a形成於該保護 層230以及該銲墊220A以及220B之上，並於該第一 金屬層240a與該銲墊22〇A以及22〇B間提供良好黏著 力。該第一金屬層240a較佳情況下係為鈦（Ti)材質，但 不限於鈦（Ti)材質，亦可為鋁（A〗）材質。該第二金屬 層24 Ob形成於該第一金屬層24 〇a之上。該第二金屬層 240b較佳情況下係為鎳（Ni)材質，但不限於鎳（川）材 13 1284969 用、該錄至屬層沈積於該鈦金屬層之上，提供一保護層 乂防止介金屬化合物（Intermetallic compounds)的 生β 4介金屬化合物係由錫鉛元素與鋁元素反應生 ' ·此^成封襄結構的失效。該第三金屬層240c形 成於該第二金屬層240b之上。該第三金屬層240c較佳 情況下係為銅（Cu)材質。最後銅金屬層施加於該鎳（Ni) ^屬層之上以使該錫鉛銲塊可成功的與該結構240麵 合。因此，該第三金屬層24〇e除了提供足夠的保護給 $第二金屬層24〇b，更提供良好的潤濕效應給該第三 金屬層240c使該錫鉛銲塊與該結構24〇耦合。 如第4D圖所示，除了覆蓋於該銲墊開口 231A、 23 1B以及其鄰近區域的部分外，該銅金屬層24〇c隨後 塗佈光阻層250、上光罩、暴露並且蝕刻以產生開口 244、245。該光罩的殘餘部分隨後被移除以暴露出該結 構240的剩餘部分。因此，該複數金屬層具有該開口 244、245以形成習知技術中銲塊底部金屬化（under bump metallurgy，UBM)結構層 25〇A，25〇B 以及外部結 構251，252, and 253，如第4E圖所示。換句話說，該 複數外部結構251、252、253以及該銲塊底部金屬化結 構層250A、250B較佳情況下具有相同金屬層，但不限 於上述之情況。該銲塊底層金屬結構（UBM) 250A、250B 係經由該結構2 4 0的餘刻而形成，習知技術中，上述 UBM之形成方法可藉由化學氣相沈積、電漿增強化學 氣相沈積或物理氣相沈積方法實現。該物理氣相沈積方 法可為濺鍍、蒸鍍或其他類似方法。值得注意的是，本 發明並不限於任何特別或多層化之銲塊底部金屬化 (under bump metallurgy, UBM)結構層。 請參考第4E圖，一銲塊遮罩薄膜260形成於複數 外部結構251、252、253以及該銲塊底部金屬化結構層 14 1284969 250B的部分表面上，並形成複數開口 254A、254B以暴 露其下的部分銲塊底部金屬化結構層250A、250B。其 中該銲塊遮罩薄膜260形成於該銲塊底部金屬化結構 層250B的部分表面上，該部分表面不包含覆蓋該銲墊 開口 23 1B及其鄰近區域的部分。 請參閱第4F圖，為一銲料塗佈程序，該程序係藉 由網版印刷或其他塗佈技術，於複數開口 254A、254B 中填充銲料（Solder Paste)，該銲料覆蓋於該銲塊底部金 屬化結構層250A、25〇B上，以分別於該銲塊底部金屬 化結構層250A、250B上形成複數銲塊26〇a、260B。 睛再次參閱第4F圖，該銲塊底部金屬化結構層25〇 a、 250B上形成的複數銲塊26〇a、26〇b可視為導電介面， 孩”面可為柱狀、圓柱狀或球狀。該導電銲塊包含但不 限於任何可用於覆晶結構上的已知導電金屬或合金，例 如鉛、錫、銅、銀、金等金屬，導電聚合物或導電合成 物。該銲塊底部金屬化結構層中的該濕潤層可直接與該 導電銲墊連接，並於溫度預設的回銲（refl〇w)程序後， 元成與該導電銲墊的電性耦合。該溫度將依據習知技藝 中，施加於該導電銲墊以及該濕潤層的該導電材料特性 而調整。Therefore, since the copper metal layers 240c of the plurality of external structures 251, 252, and 253 are not covered by the plurality of solder bumps 270A and 270B (as shown in FIG. 4H 284 969, the copper of the plurality of external structures 25, 252, and 253) The metal layer 24〇c is exposed to form a cuprous oxide layer or a copper oxide layer 257 on the surface of the plurality of outer structures 251, 252, and 253. • Referring to FIG. 3, a primer 290 is used to fill the space between the wafer 210 and the substrate 280. This process can be accomplished using a conventional filling or filling process. The primer 290 is directly injected under the wafer 210 and fills the space between the wafer 210 and the substrate 280 by capillary action. As mentioned earlier, the biggest problem in the flip chip structure comprising the primer is the delamination of the interface between the protective layer and the primer. The process of using different primers to fill the space between the wafer and the substrate is quite complicated, depending on the need to replace the different primers with the different protective layers (such as tantalum nitride or polymer materials). . The present invention utilizes the cuprous oxide or copper oxide layer 257 in the second metal layer 240c to form a good bond with the primer 290. As a result, the primer 29A can form a good bond with the cuprous oxide or copper oxide layer 257 and the substrate 280 in the third metal layer 240c. Therefore, even if different underfill materials are not used in the present invention to alleviate the delamination problem occurring between the protective layer and the primer material, in the present invention, the flip chip structure including the primer has overcome the cause of the Young's coefficient or The problem of delamination caused by different coefficients of thermal expansion. In summary, the present invention utilizes a cuprous oxide or copper oxide layer in the third metal layer to form a good bond with the primer to prevent the wafer and the primer. The occurrence of delamination between structures. In summary, the present invention provides a simple encapsulation process to substantially increase the reliability of the flip chip structure without the need to replace the different primers with different protective layers to make the application of flip chip technology more popular. Furthermore, the wafer 210 can be an integrated circuit. At the same time, the substrate 280 and the contact pads 28lA and 12 1284969 2 8 1B may also be part of a printed circuit board in which the bond between the tin-lead solder bump and the contact turns is taken into consideration. Mechanical and electrical connection between the circuit and the printed circuit board. 4A to 4E are schematic views showing the process and structure of the above preferred embodiment of the present invention for forming a tin-lead solder bump on a flip-chip structure including a metallization structure layer at the bottom of the solder bump. Figure 4A is a partial cross-sectional view of the wafer 21A. In this embodiment, the wafer 210 may be a half conductor bare crystal including the wafer surface 211. The wafer 21A includes a plurality of pads 220A, 220B ((for simplicity of illustration, only two pads are shown in the illustration), the semiconductor device is combined with a substrate 280 to form a flip chip structure. The substrate includes contact pads 281A and 281B. The plurality of pads 220A, 220B are preferably copper pads, but are not limited to copper pads. As shown in FIG. 4B, a protective layer 23 is coated on the wafer surface 211 and the The plurality of pads 220A, 220B. The protective layer 230 may be any insulating material but is preferably a polymer such as polyimide, cerium-based oxide, cerium-based nitride, etc. In other words, The protective layer 230 is a dielectric layer. The protective layer 23 is then subjected to photoresist coating, photomasking, development, and etching to form pad openings 23A and 23BB for exposing the underlying solder. Pads 22A and 220B. The remaining portion of the mask is then completely removed to completely expose the protective layer 230. As shown in FIG. 4C, the first metal layer 24A is formed on the protective layer 230 and the pad 220A. And above 220B, and on the first metal layer 24 0a provides good adhesion between the pads 22A and 22B. The first metal layer 240a is preferably made of titanium (Ti), but not limited to titanium (Ti) or aluminum ( A]) material. The second metal layer 24 Ob is formed on the first metal layer 24 〇 a. The second metal layer 240b is preferably made of nickel (Ni) material, but not limited to nickel (Chuan) The material 13 13284969 is deposited on the titanium metal layer to provide a protective layer to prevent the intermetallic compound of the β 4 intermetallic compound from being reacted with the aluminum element by the tin-lead element. The failure of the first metal layer 240c is formed on the second metal layer 240b. The third metal layer 240c is preferably made of copper (Cu). Finally, the copper metal layer is applied. Overlying the nickel (Ni) layer, the tin-lead solder bump can be successfully planarized with the structure 240. Thus, the third metal layer 24〇e provides sufficient protection to the second metal layer 24 〇b, further providing a good wetting effect to the third metal layer 240c to make the tin-lead solder bump and the structure 24〇 As shown in FIG. 4D, the copper metal layer 24〇c is subsequently coated with a photoresist layer 250, a mask, exposed and etched except for portions covering the pad openings 231A, 23 1B and adjacent regions thereof. Openings 244, 245 are created. The remaining portion of the reticle is then removed to expose the remainder of the structure 240. Thus, the plurality of metal layers have the openings 244, 245 to form a solder bump bottom metallization in the prior art. (under bump metallurgy, UBM) structural layers 25 〇 A, 25 〇 B and external structures 251, 252, and 253, as shown in Figure 4E. In other words, the plurality of outer structures 251, 252, 253 and the solder bump bottom metallization layers 250A, 250B preferably have the same metal layer, but are not limited to the above. The underlayer metal structures (UBM) 250A, 250B are formed by the remnant of the structure 240. In the prior art, the UBM can be formed by chemical vapor deposition, plasma enhanced chemical vapor deposition. Or physical vapor deposition method. The physical vapor deposition method can be sputtering, evaporation, or the like. It is to be noted that the invention is not limited to any particular or multilayered under bump metallurgy (UBM) structural layer. Referring to FIG. 4E, a solder mask film 260 is formed on a portion of the surface of the plurality of outer structures 251, 252, 253 and the bottom metallization layer 14 1284969 250B, and forms a plurality of openings 254A, 254B to expose The lower portion of the solder bump bottom metallization structure layers 250A, 250B. The solder mask film 260 is formed on a portion of the surface of the solder bump bottom metallization layer 250B, the portion of the surface not including a portion covering the pad opening 23 1B and its adjacent region. Referring to FIG. 4F, a solder coating process is performed by screen printing or other coating technique to fill a plurality of openings 254A, 254B with a solder (Solder Paste) covering the bottom metal of the solder bump. On the structural layers 250A, 25B, a plurality of solder bumps 26A, 260B are formed on the solder bump bottom metallization structure layers 250A, 250B, respectively. Referring again to FIG. 4F, the plurality of solder bumps 26〇a, 26〇b formed on the metallization structure layers 25〇a, 250B at the bottom of the solder bump can be regarded as a conductive interface, and the child can be cylindrical, cylindrical or spherical. The conductive solder bumps include, but are not limited to, any known conductive metal or alloy that can be used on a flip chip structure, such as lead, tin, copper, silver, gold, etc., conductive polymers or conductive composites. The wetting layer in the metallized structural layer can be directly connected to the conductive pad and electrically coupled to the conductive pad after a temperature preset reflow process. The temperature will be based on In the prior art, the properties of the conductive material applied to the conductive pad and the wetting layer are adjusted.
隨後為一第一回銲程序，透過本程序以完成該銲塊 底部金屬化結構層25〇A、25〇B與該銲塊27〇A、27〇B 的電性耦合。隨後該銲塊遮罩薄膜260被移除。如第 4G圖所示，該銲塊27〇A、27〇B透過一第二回銲程序 形成球形。 第4H圖係為該覆晶組裝結構2〇〇之A_A剖面示意 圖，，該圖同時表示了該外部結構251、252、253之銅 金^層240c的氧化程序。該氧化程序於該回銲程序後 實施，由於該部分銅金屬層24〇c以及複數外部結構 15 1284969 251、252、253未被該銲塊270A、270B覆蓋，上述結 構被暴露於外，以化學氧化之製程以形成氧化銅或氧化 亞銅結構之氧化層2 5 7。依上述方法，該氧化層形成於 該未被覆蓋的銅金屬層240c表面上。 該晶片210藉由該銲塊27 OA、27 OB以及該基板280 上的接觸塾281A、281B與該基板280電性連接。該銲 塊置於該基板280表面，且經由回銲程序，與該晶片表 面的該導電銲塊270A、270B以及與其對應的該基板280 的表面銲墊281A、281B形成電性連接。最後，一底膠 被用以填滿該晶片210與該基板28〇間的空間。該底膠 290以及其填充方法已被習知技術充分揭露，不再於此 處贅述。該底膠290係利用毛細作用填滿介於該晶片 210以及該基板280間的空間。 請參考第5圖，係為本發明較佳實施例中，形成於 該覆晶結構上的銲塊上視圖，該覆晶結構具有銲塊底層 金屬化結構。如第5圖所示，本實施例中，具有兩半圓 開口’該開口係圍繞該金屬層的中心以形成部分該銲塊 底部金屬化結構，該銲塊底部金屬化結構係位於該銲塊 270B之下。依此結果，該銅金屬層24〇e可為該覆晶半 導體裝置200之接地平面。基於該銅金屬層24〇〇與該 銲墊220B的電性連接關係，該銲墊22〇B可定義為一 接地塾。反之，因該銅金屬240c與該銲塾220A並無電 性連接關係，該銲墊220A可定義為一獨立銲墊。 杏 > 本發明的目的已經被完整而有效地的達成。其具體 貝訑方法已被顯示並描述以說明本發明功能與結構原 理的目的且其變化不出上述原則。因此，本發明包含所 有下列權利要求項的精神與範圍内之變化。 Ί284969 【圖式簡單說明】 為—f知的鱗銲塊錢化結構示意圖。 上m帛2E圖為—f知製程方法示意圖，該方法用以於覆晶結構 上形成錫鉛銲塊。 2圖為-依據本發明較佳實施例之覆晶組裝構造示意圖，該示意圖 包含一底部銲塊金屬化結構。 =4^圖至第4H圖為依據本發明較佳實施例之一製程方法與結構示意 銲塾Γ方相以於覆晶結構上，與—底轉塊金屬化結構形成一錫船Subsequently, a first reflow process is performed through which the electrical connection of the undermetallization structural layers 25A, 25B of the solder bump to the solder bumps 27A, 27B is completed. The solder bump film 260 is then removed. As shown in Fig. 4G, the solder bumps 27A, 27B are formed into a spherical shape by a second reflow process. Fig. 4H is a schematic cross-sectional view of the A_A of the flip chip assembly structure 2, which also shows the oxidation procedure of the copper layer 240c of the outer structure 251, 252, 253. The oxidation process is performed after the reflow process, since the portion of the copper metal layer 24〇c and the plurality of external structures 15 1284969 251, 252, 253 are not covered by the solder bumps 270A, 270B, the structure is exposed to the outside, The oxidation process is to form an oxide layer of copper oxide or cuprous oxide structure 257. According to the above method, the oxide layer is formed on the surface of the uncovered copper metal layer 240c. The wafer 210 is electrically connected to the substrate 280 by the solder bumps 27 OA, 27 OB and the contact pads 281A, 281B on the substrate 280. The solder bump is placed on the surface of the substrate 280, and is electrically connected to the conductive pads 270A, 270B on the surface of the wafer and the surface pads 281A, 281B of the substrate 280 corresponding thereto via a solder reflow process. Finally, a primer is used to fill the space between the wafer 210 and the substrate 28. The primer 290 and its filling method have been fully disclosed by the prior art and will not be further described herein. The primer 290 fills the space between the wafer 210 and the substrate 280 by capillary action. Referring to Figure 5, there is shown a top view of a solder bump formed on the flip chip structure in accordance with a preferred embodiment of the present invention, the flip chip structure having a solder bump underlying metallization structure. As shown in FIG. 5, in this embodiment, there are two semicircular openings 'the opening surrounds the center of the metal layer to form a portion of the solder bump bottom metallization structure, and the solder bump bottom metallization structure is located on the solder bump 270B. under. Accordingly, the copper metal layer 24〇e can be the ground plane of the flip chip semiconductor device 200. Based on the electrical connection relationship between the copper metal layer 24A and the pad 220B, the pad 22A can be defined as a ground 塾. Conversely, because the copper metal 240c is not electrically connected to the solder fillet 220A, the solder pad 220A can be defined as a separate pad. Apricot > The object of the present invention has been achieved in a complete and effective manner. The specific beryllium method has been shown and described to illustrate the purpose of the functional and structural principles of the present invention and it does not change the above principles. Accordingly, the present invention is intended to embrace a Ί 284969 [Simple description of the diagram] is a schematic diagram of the structure of the scale welding block. The upper m帛2E diagram is a schematic diagram of the process method for forming a tin-lead solder bump on the flip-chip structure. 2 is a schematic view of a flip chip assembly structure in accordance with a preferred embodiment of the present invention, the schematic including a bottom solder bump metallization structure. 4 to 4H are diagrams showing a process method and structure according to a preferred embodiment of the present invention. The soldering phase is formed on the flip chip structure, and a tin boat is formed with the metal structure of the bottom turn block.
第5圖為依據本發明較佳實施例之一覆晶半導體裝置上視圖。Figure 5 is a top plan view of a flip chip semiconductor device in accordance with a preferred embodiment of the present invention.
【主要元件符號說明】 200覆晶半導體組裝結構 211晶片表面 220B鲜塾 244 開口 246 開口 250A銲塊底層金屬化結構 251外部結構 253外部結構 270A銲塊 210晶片 220A銲墊 230保護層 245 開口 247 開口 250B鲜塊底層金屬化結構 252外部結構 257氧化銅層 270B銲塊 17[Main component symbol description] 200 flip chip semiconductor assembly structure 211 wafer surface 220B fresh 244 opening 246 opening 250A solder bump underlying metallization structure 251 external structure 253 external structure 270A solder bump 210 wafer 220A solder pad 230 protective layer 245 opening 247 opening 250B fresh block underlying metallization structure 252 external structure 257 copper oxide layer 270B solder bump 17