I282602 九、發明說明： 【發明所屬之技術領域】 本發明係有關於銅内連線半導體製程領域，特別是有關於一種 部分介層洞優先(Partial-via-first)銅雙鑲嵌製程，其中較特別的是本 發明採用具有較低碳濃度的四乙基氧矽烷(TEOS)石夕氧蓋層，藉此 改善介層洞自我停止蝕刻的問題。 曰 > 【先前技術】 如熟習該項技藝者所知，鑲嵌内連線技；^已經成為目前半導體 業中銅^線之主要製作方式。簡言之，鑲嵌内連線結構的製作 方法，是先在介電材料薄膜上蝕刻出電路圖案，然後再將銅金屬 填入這個圖案凹槽中。而依在介電材料薄膜上蝕刻電路圖案的方 式來區分，雙鑲嵌技術大致上又可再細分為溝渠優先(trench_first) 製程、介層洞優先(via-first)、部分介層洞優以及 .自行對準(self-aligned)等不同種類的製程。 睛參閱第1圖至第5圖，其繪示的是習知技藝的部分介層洞 優先(partial-via-first)雙鑲嵌製程之剖面示意圖。首先，如第i圖所 不，基材1上具有一底層或低介電常數介電層1〇。在低介電常數 介電層10中形成有下層銅導線12，並且覆蓋有一蓋層14。接著 依序在蓋層14上形成低介電常數介電層16、矽氧蓋層18、金屬 遮罩層20以及底部抗反射層（b〇tt〇m anti-re£jective c〇ating， BARC)22。然後，在底部抗反射層22上形成光阻圖案30，其具有 7 1282602 一溝渠開口 32 ’定義出鑲嵌導線之溝渠圖案。 如第2圖所示，接著進行-乾餘刻製程，經由光阻圖案％的 溝渠開口 32侧金屬遮罩層20直到石夕氧蓋層18，藉此形成一溝 渠凹口 36。前述的乾蝕刻停止在矽氧蓋層18中。接著，去除剩下 的光阻圖案30以及底部抗反射層22。 如第3圖所示，於基材丨上沈積另—底部抗反射層％，且使 底部抗反射層38填滿溝渠凹口 36。接著，再於底部抗反射層38 上形成一光阻圖案40，其具有一介層洞開口 42，其位置恰好在溝 渠凹口 36的正上方。上述的介層洞開口 42係利用習知的微影技 術形成。 如第4圖所示，利用光阻圖案4〇作為蝕刻硬遮罩，進行乾蝕 刻製程，經由介層洞開口 42蝕刻底部抗反射層38、矽氧蓋層18 以及低介電常數介電層16,藉此在低介電常數介電層16上半部形 成部分介層洞46。接著，利用氧氣電漿等方式去除剩下的光阻圖 案40以及底部抗反射層38。 如第5圖所示，接著利用金屬遮罩層20作為蝕刻硬遮罩，進 行乾钕刻製程，向下蝕刻未被金屬遮罩層2〇覆蓋到的矽氧蓋層18 以及低介電常數介電層16,藉此將先前形成的溝渠凹口 36以及部 分介層洞46轉移至低介電常數介電層16中，形成雙鑲嵌開口 50， 8 1282602 其包括溝渠開口 56以及介層洞開口 66。 介層洞開口 66應該要暴露出位於低介電常數介電層1〇的下芦 銅導線U ’然而，如第5圖所示，隨著介層、;同的臨界尺寸縮減至 90奈未甚至更小’餘刻介層洞開口 66的時候往往會發生介層洞自 我停止侧的問題，而因此無法使下層鋼導線12被導通。這種介 層洞自我停止姓刻的現象在當介層洞為孤立介層洞㈣獅_時 _ 變得更加嚴重。 由上可知，在積體電路製造技術領域中確實需要一種改良之形 成雙鑲嵌結構的方法，以改善這種介層洞自我停止触刻的現象。 【發明内容】 本發明之主要目的即在提供一種改良之雙鑲嵌製程方法，可以 有效地解決習知技藝中所發生的介層洞自我停止钕刻問題。I282602 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to the field of copper interconnect semiconductor manufacturing, and more particularly to a partial-via-first copper dual damascene process, in which In particular, the present invention employs a tetraethyl oxoane (TEOS) rock oxide cap layer having a lower carbon concentration, thereby improving the problem of self-stop etching of the via hole.曰 > [Prior Art] As known to those skilled in the art, inlaid interconnect technology; ^ has become the main production method of copper wire in the semiconductor industry. In short, the damascene interconnect structure is fabricated by etching a circuit pattern on a thin film of dielectric material and then filling the pattern metal into the recess of the pattern. In contrast to the way in which the circuit pattern is etched on the dielectric material film, the dual damascene technique can be subdivided into a trench-first process, a via-first, and a partial via. Different types of processes such as self-aligned. Referring to Figures 1 through 5, there is shown a cross-sectional view of a partial-via-first dual damascene process of the prior art. First, as shown in Fig. i, the substrate 1 has an underlying or low-k dielectric layer 1〇. An underlying copper wire 12 is formed in the low dielectric constant dielectric layer 10 and covered with a cap layer 14. Then, a low-k dielectric layer 16, a tantalum cap layer 18, a metal mask layer 20, and a bottom anti-reflective layer are formed on the cap layer 14 (b〇tt〇m anti-re£jective c〇ating, BARC) )twenty two. Then, a photoresist pattern 30 is formed on the bottom anti-reflective layer 22, which has 7 1282602 a trench opening 32' defining a trench pattern of the damascene. As shown in Fig. 2, a dry-after-etching process is then performed, through the photoresist pattern % of the trench opening 32 side metal mask layer 20 to the rock oxide cap layer 18, thereby forming a trench recess 36. The aforementioned dry etching is stopped in the tantalum cap layer 18. Next, the remaining photoresist pattern 30 and the bottom anti-reflection layer 22 are removed. As shown in Fig. 3, another bottom anti-reflective layer % is deposited on the substrate crucible, and the bottom anti-reflective layer 38 is filled with the trench recess 36. Next, a photoresist pattern 40 is formed on the bottom anti-reflective layer 38, which has a via opening 42 positioned just above the trench recess 36. The via opening 42 described above is formed using conventional lithography techniques. As shown in FIG. 4, the photoresist pattern 4 is used as an etching hard mask to perform a dry etching process, and the bottom anti-reflection layer 38, the tantalum cap layer 18, and the low-k dielectric layer are etched through the via opening 42. 16, thereby forming a portion of the via 46 in the upper half of the low-k dielectric layer 16. Next, the remaining photoresist pattern 40 and the bottom anti-reflection layer 38 are removed by means of oxygen plasma or the like. As shown in FIG. 5, the metal mask layer 20 is then used as an etch hard mask to perform a dry etching process, and the underlying oxide layer 18 and the low dielectric constant not covered by the metal mask layer 2 are etched down. Dielectric layer 16 thereby transferring previously formed trench recess 36 and portion via 46 into low-k dielectric layer 16 to form dual damascene openings 50, 8 1282602 including trench openings 56 and vias Opening 66. The via opening 66 should expose the lower copper conductor U' located in the low-k dielectric layer 1', however, as shown in Fig. 5, with the via, the same critical dimension is reduced to 90% or even A smaller 'replacement hole opening 66 tends to occur at the self-stop side of the via hole, and thus the underlying steel wire 12 cannot be turned on. This phenomenon of self-stopping the surname of the interlayer hole becomes more serious when the interlayer hole is an isolated interlayer hole (four) lion__. It can be seen from the above that in the field of integrated circuit manufacturing technology, an improved method of forming a dual damascene structure is required to improve the self-stopping of the via hole. SUMMARY OF THE INVENTION The main object of the present invention is to provide an improved dual damascene process method that can effectively solve the problem of self-stop engraving of via holes occurring in the prior art.
I 本發明提供一種部分介層洞優先雙鑲嵌製程。首先提供一基 材，其上具有一底層、一形成在該底層中的下層銅導線以及一覆 • 蓋該下層銅導線以及該底層的蓋層；接著於該蓋層上沈積一介電 層；接著於該介電層上沈積一 TEOS矽氧層，且該TEOS矽氧層 具有一濃度低於lxlO19 atoms/cm3的碳含量；接著於該TEOS石夕氧 層上形成一金屬硬遮罩；於該金屬硬遮罩以及該TEOS矽氧層中 蝕刻出一溝渠凹口；接著經由該溝渠凹口，於該TEOS矽氧層中 9 1282602 口以 她刻出—部分介層洞開口;最後將該溝渠凹 層洞開口崎刻方式轉移至該介電層中，藉此形成一 又鑲嵌開π，並且暴露出該下層銅導線。 容^=貝審查委員此更進一步了解本發明之特徵及技術内 料下有關本發明之詳_與_。_所附圖式僅 供參考與辅助說明用，並非用來對本發明加以限制者。 【實施方式】 八人Γ參閱第6圖至第1G圖傭示岐本發明較佳實施例的部 刀）丨層洞優先雙鑲欲萝栽 -立 或類似的_域:如第:圖：:基材::== 。梅繼侧 14 #技"且覆盍有—蓋層14。根據本發明之較佳實施例，蓋層 4係轉雜氮的碳化邦伽)為其成分，厚度約為細至 (angSt_)’較佳約為500埃左右。 、 〜Γ著依序在蓋層14上形成低介電常數介電層16、TE0S矽 2盍曰118、金屬遮罩層2()以及底部抗反射層。根據本發明之 施例’金屬遮罩層2〇以氮化欽㈣為其成分，但不限於 二^ W 20的厚度約介於25〇至45〇埃之間， 至350埃之間。 1282602 根據本發明之較佳實施例，低介電常數介電層16可以是具有 ‘ 有機矽酸鹽玻璃(organosilicate glass，OSG)等成分，這類有機矽酸 ^ 鹽玻璃係在二氧化矽或氧化矽中摻入碳或氫原子，使其具有約介 於2至3之間的低介電常數值。適合作為低介電常數介電層16成 分，例如應用材料(Applied Materials)公司的黑鑽⑼ack Diam〇ndTM) 產品系列或者Novellus公司的珊瑚(CORAL™)產品等等。根據本 發明之較佳實施例，低介電常數介電層16的厚度約介於25〇〇至 φ 4500埃之間，較佳介於3〇00至35〇0埃之間。 根據本發明之較佳實施例，TE〇S矽氧蓋層n8係利用電漿 加強化學氣相沈積(plasma-enhanced chemical vapor deposition， PECVD)技術所沈積而成的，其中使用到四乙基氧石夕烧 (tetraethyl〇rthosilicate，TEOS)作為前驅物以及氧氣，且採用比較高 的氧氣對TEOS比值(O/TEOS ratio)。本發明之主要特徵在於 TEOS石夕氧蓋層118中的碳含量係經過刻意的降低至ιχι〇ΐ9 ® atoms/cm3以下。由於習知技藝中所發生的介層洞自我停止蝕刻問 題可能與習知矽氧蓋層中的碳含量過高有關，實驗結果亦證實， 在將TEOS石夕氧蓋層118中的碳含量降低至ΐχΐ〇19 at〇ms/cm3以下 之後，習知技藝中所發生的介層洞自我停止餘刻問題即可以獲得 明顯的改善。 根據本發明之較佳實施例，具有較低碳含量的TE〇s矽氧蓋 層118其沈積可以利用以下的製程條件完成：壓力介於3至8托 11 1282602 . 耳，較佳約為5托耳；製程溫度在100至450°c之間，較佳在350 / 至400°C之間；高頻無線電波功率(high_frequenCy rf power)約為 200至350瓦特，較佳在250至300瓦特之間，而在280瓦特最佳， 且持續提供約25秒左右；低頻無線電波功率(1〇w-frequency处 power)約為30至70瓦特，較佳在4〇至6〇瓦特之間，而在5〇瓦 特最佳；TEOS前驅物流量約為〇.2gm至5gm ;載氣使用氦氣，而 流量介於7500至9500 seem，較佳為8500至9000 sccm ;氧氣流 Φ 量介於 5000 至 10000 seem，較佳為 8000 sccm。 根據本發明之較佳實施例，本發明採用比較高的氧氣對 * TE〇S比值(〇2/TEOS rati0)。前述的TEOS矽氧蓋層m化學氣相 沈積製程係在較慢的沈積速率下進行，其沈積速率約介於每分鐘 800至侧埃之間。最後沈積的TE〇s石夕氧蓋層118厚度約為· 至1000埃之間，較佳為500埃左右。 _ 請參閱第11圖，其繪示的是本發明TE0S矽氧蓋層118的二 次離子質譜分析圖(SIMS analysis)。由圖中可發現到根據二次離子 質譜分析的結果，本發明TEOS⑦氧歸118中的碳含量低於1χ 10 9 atoms/cm3以下，且較高碳濃度大約發生在離表面較近的位 置，而隨著深度的增加，TEOS矽氧蓋層118中的碳含也隨之降低， 形成一碳濃度梯度現象，這也是本發明的另一主要技術特徵。 回到第7圖，接下來在底部抗反射層22上形成光阻圖案％， 12 1282602 其具有一溝渠開口 32，定義出鑲嵌導線之溝渠圖案。接著進行一 / 乾蝕刻製程，經由光阻圖案30的溝渠開口 32蝕刻金屬遮罩層20 直到TEOS石夕氧蓋層118，藉此形成一溝渠凹口 36。同樣的，前 述乾餘刻停止在TEOS石夕氧蓋層118中。接著，利用氧氣電漿等 方式去除剩下的光阻圖案30以及底部抗反射層22。 如第8圖所示，然後於基材1上沈積另一底部抗反射層38， • 且使底部抗反射層38填滿溝渠凹口 36。接著，再於底部抗反射層 38上形成一光阻圖案4〇，其具有一介層洞開口 42，其位置恰好在 溝渠凹口 36的正上方。上述的介層洞開口 42係利用習知的微影 • 技術形成。 如第9圖所示，接著利用光阻圖案4〇作為蝕刻硬遮罩，進行 乾餘刻製程，經由介層洞開口 42蝕刻底部抗反射層38、TEOS石夕 鲁 氧蓋層以及低介電常數介電層16，藉此在低介電常數介電層 16上半部形成部分介層洞46。接著，利用氧氣電漿等方式去除剩 下的光阻圖案4〇以及底部抗反射層38。另外，亦可以使用h2/N2 • 或Ha/He電漿進行光阻圖案4〇以及底部抗反射層38的去除。 最後’如第10圖所示，利用金屬遮罩層20作為蝕刻硬遮罩， w 進行乾餘刻製程，向下蝕刻未被金屬遮罩層20覆蓋到的TEOS矽 . 氧蓋層118以及低介電常數介電層10，藉此將先前形成的溝渠凹 36以及部分介層洞46轉移至低介電常數介電層16中，形成雙 13 1282602 鑲嵌開口 150，其包括溝渠開口 156以及介層洞開口 166。其中， 介層洞開口 166暴露出位於低介電常數介電層1〇的下層銅導線 12 〇 此外，根據本發明之另一較佳實施例，在沈積TE0S矽氧蓋層 118之後，亦可以再進行一道氧氣電漿處理步驟，使沈積的TE0S 石夕氧蓋層118接觸氧氣電漿，藉此使TE0S矽氧蓋層118的碳含 量更進一步的降低。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第5圖繪示的是習知技藝的部分介層洞優先 (partial-via-first)雙鑲嵌製程之剖面示意圖。 第6圖至第1〇圖繪示的是本發明較佳實施例的部分介層洞優 先雙鑲嵌製程之剖面示意圖。 第11圖繪示的是本發明TE0S_氧蓋層的二次離子質譜分析 圖(SIMS analysis)。 【主要元件符號說明】 1基材 10低介電常數介電層 12下層鋼導線 14蓋層 14 1282602 16 低介電常數介電層 18 石夕氧蓋層 20 金屬遮罩層 22 底部抗反射層 30 光阻圖案 32 溝渠開口 36 溝渠凹口 38 底部抗反射層 40 光阻圖案 42 介層洞開口 46 部分介層洞 50 雙鑲嵌開口 56 溝渠開口 66 介層洞開口 118 TEOS矽氧蓋層 150 雙鑲嵌開口 156 溝渠開口 166 介層洞開口 15I The present invention provides a partial via-first dual damascene process. Firstly, a substrate having a bottom layer, a lower copper wire formed in the bottom layer, and a cap layer covering the underlying copper wire and the bottom layer; and then depositing a dielectric layer on the cap layer; And depositing a TEOS germanium oxide layer on the dielectric layer, wherein the TEOS germanium oxide layer has a carbon content lower than lxlO19 atoms/cm3; and then forming a metal hard mask on the TEOS rock oxide layer; The metal hard mask and the TEOS silicon oxide layer are etched into a trench recess; and then through the trench recess, 9 1282602 in the TEOS silicon oxide layer is engraved by her - part of the via opening; The trench recess is transferred to the dielectric layer in an open manner, thereby forming a mosaic π and exposing the underlying copper conductor. It is further understood that the features and technical contents of the present invention relate to the details of the present invention. The drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Eight persons Γ refer to the figure of Fig. 6 to Fig. 1G for the knives of the preferred embodiment of the present invention.) The layer of the hole is preferentially double-inlaid with a stalk-like or similar _ field: as shown in the figure: : Substrate::== . Mei Jibian 14 #技" and the cover is covered with a cover layer 14. In accordance with a preferred embodiment of the present invention, the cap layer 4 is a component of a carbon-doped carbonized bond, and has a thickness of about angstroms (Angstroms) preferably about 500 angstroms. A low-k dielectric layer 16, a TEOS 矽 2 盍曰 118, a metal mask layer 2 (), and a bottom anti-reflective layer are formed on the cap layer 14 in this order. According to the embodiment of the present invention, the metal mask layer 2 is made of a nitride (4) component, but is not limited to a thickness of about 25 Å to 45 Å to 350 Å. 1282602 According to a preferred embodiment of the present invention, the low-k dielectric layer 16 may have a composition such as 'organosilicate glass (OSG), which is based on cerium oxide or The cerium oxide is doped with carbon or hydrogen atoms to have a low dielectric constant value of between about 2 and 3. It is suitable as a low-k dielectric layer 16 component, such as Applied Materials' Black Diamond (9) ack Diam〇ndTM product line or Novellus's Coral (CORALTM) product. In accordance with a preferred embodiment of the present invention, the low-k dielectric layer 16 has a thickness between about 25 Å and φ 4500 Å, preferably between 30,000 and 35 Å. According to a preferred embodiment of the present invention, the TE〇S oxide cap layer n8 is deposited by plasma-enhanced chemical vapor deposition (PECVD) technology, wherein tetraethylol is used. Tetraethyl〇rthosilicate (TEOS) is used as a precursor and oxygen, and a relatively high oxygen to OOS ratio (O/TEOS ratio) is used. The main feature of the present invention is that the carbon content in the TEOS Oxygen cap layer 118 is deliberately reduced to below ιχι〇ΐ9 ® atoms/cm3. Since the self-stop etching problem of the via hole occurring in the prior art may be related to the excessive carbon content in the conventional oxygen cap layer, the experimental results also confirm that the carbon content in the TEOS Oxygen cap layer 118 is lowered. After 19 to 〇ms/cm3 or less, the problem of the self-stopping of the via hole occurring in the conventional technique can be significantly improved. In accordance with a preferred embodiment of the present invention, the TE〇s oxide cap layer 118 having a lower carbon content can be deposited using the following process conditions: a pressure of between 3 and 8 Torr 11 1282602. Ears, preferably about 5 The processing temperature is between 100 and 450 ° C, preferably between 350 / 400 ° C; the high-frequency radio power (high_frequenCy rf power) is about 200 to 350 watts, preferably 250 to 300 watts. Between 280 watts is best, and lasts for about 25 seconds; low frequency radio wave power (power at 1 〇 w-frequency) is about 30 to 70 watts, preferably between 4 〇 and 6 watts. The best is 5 watts; the TEOS precursor flow rate is about 2.2gm to 5gm; the carrier gas uses helium, and the flow rate is between 7500 and 9500 seem, preferably 8500 to 9000 sccm; the oxygen flow Φ is between 5000. Up to 10000 seem, preferably 8000 sccm. In accordance with a preferred embodiment of the present invention, the present invention employs a relatively high oxygen to * TE〇S ratio (〇2/TEOS rati0). The aforementioned TEOS oxime cap m chemical vapor deposition process is carried out at a slower deposition rate with a deposition rate of between about 800 and angstroms per minute. The final deposited TE〇s Oxygen cap layer 118 has a thickness of between about 10,000 angstroms and about 1000 angstroms, preferably about 500 angstroms. _ Referring to Fig. 11, a second ion mass spectrometry (SIMS analysis) of the TE0S oxygen cap layer 118 of the present invention is shown. It can be found from the figure that according to the results of secondary ion mass spectrometry, the carbon content of TEOS7 in the present invention is less than 1χ10 9 atoms/cm3, and the higher carbon concentration occurs approximately at a position close to the surface. As the depth increases, the carbon content in the TEOS oxygen cap layer 118 also decreases, forming a carbon concentration gradient phenomenon, which is another main technical feature of the present invention. Returning to Fig. 7, a photoresist pattern % is formed on the bottom anti-reflective layer 22, 12 1282602 having a trench opening 32 defining a trench pattern of the damascene. A dry/etch process is then performed to etch the metal mask layer 20 through the trench opening 32 of the photoresist pattern 30 up to the TEOS rock oxide cap layer 118, thereby forming a trench recess 36. Similarly, the aforementioned dryness ceases in the TEOS Oxygen cap layer 118. Next, the remaining photoresist pattern 30 and the bottom anti-reflection layer 22 are removed by means of oxygen plasma or the like. As shown in Fig. 8, another bottom anti-reflective layer 38 is then deposited on the substrate 1, and the bottom anti-reflective layer 38 is filled with the trench recess 36. Next, a photoresist pattern 4 is formed on the bottom anti-reflective layer 38, which has a via opening 42 located just above the trench recess 36. The via openings 42 described above are formed using conventional lithography techniques. As shown in FIG. 9, the photoresist pattern 4 is then used as an etched hard mask to perform a dry process, and the bottom anti-reflective layer 38, the TEOS Shilulu oxide cap layer, and the low dielectric are etched through the via opening 42. The dielectric layer 16 is constant, whereby a portion of the via 46 is formed in the upper half of the low-k dielectric layer 16. Next, the remaining photoresist pattern 4 and the bottom anti-reflection layer 38 are removed by means of oxygen plasma or the like. Alternatively, the photoresist pattern 4A and the bottom anti-reflective layer 38 may be removed using h2/N2 • or Ha/He plasma. Finally, as shown in Fig. 10, the metal mask layer 20 is used as an etching hard mask, w is subjected to a dry etching process, and the TEOS layer not covered by the metal mask layer 20 is etched down. The oxygen cap layer 118 and low The dielectric constant dielectric layer 10, thereby transferring the previously formed trench recess 36 and a portion of the via hole 46 into the low-k dielectric layer 16, forming a double 13 1282602 damascene opening 150, including a trench opening 156 and Hole opening 166. Wherein, the via opening 166 exposes the lower copper conductor 12 located in the low-k dielectric layer 1 〇. Further, according to another preferred embodiment of the present invention, after depositing the TE0S oxide cap layer 118, An oxygen plasma treatment step is further performed to bring the deposited TEOS stone oxide cap layer 118 into contact with the oxygen plasma, thereby further reducing the carbon content of the TE0S oxygen cap layer 118. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 5 are schematic cross-sectional views showing a partial-via-first dual damascene process of the prior art. 6 to 1 are schematic cross-sectional views showing a portion of the via hole preferred dual damascene process of the preferred embodiment of the present invention. Figure 11 is a diagram showing the secondary ion mass spectrometry (SIMS analysis) of the TEOS_oxygen cap layer of the present invention. [Main component symbol description] 1 substrate 10 low dielectric constant dielectric layer 12 lower steel wire 14 cap layer 14 1282602 16 low dielectric constant dielectric layer 18 stone oxide layer 20 metal mask layer 22 bottom anti-reflection layer 30 photoresist pattern 32 trench opening 36 trench recess 38 bottom anti-reflective layer 40 photoresist pattern 42 via opening 46 partial via 50 dual damascene opening 56 trench opening 66 via opening 118 TEOS germanium cap layer 150 double Inlay opening 156 trench opening 166 via opening 15