TWI282136B - Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device ... - Google Patents

Abstract

There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

Description

1282136 玫,发明说明: [Technical field of invention] This rabbit system is about the evaluation of wafer flatness, the method of measuring the life of the wafer, and the method of estimating the a flatness of the evaluation method. The evaluation method of the wafer uses the crystal method of the evaluation method, and the method of using the evaluation method. A semiconductor device manufacturing method for flattening wafers. [Prior Art] As the size of semiconductor device patterns approaches the limit. ^之日(4) 'Polyline degree is also beneficial to the right: In the second generation of the 隹 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The size of the pattern on the photoresist). Due to the focus change factor, the influence of wafer flatness is significant, and thus it is necessary to further increase the wafer flatness. In the conventional manufacturing method of a wafer represented by a broken wafer, the tantalum is sliced by a single crystal ingot, and sequentially subjected to various steps such as oblique cutting and grinding: the cutting step is performed by cutting the thin disc. Then at least one of the main surfaces of the wafer is transferred to the surface or both surfaces to make a type of film, ..., the surface of the mirror, and the mirror is finished to form a wafer (or PW). Wafers used are not mirror-finished, and in some cases, epitaxial crystals with a layer of insect crystals formed on mirror-finished wafers and annealed crystals with thermal sites are used. circle. In addition, in some cases, a wafer having an added value attached to a mirror-finished wafer may be employed, for example, a mirror-finished wafer having an oxide film therebetween may be sliced to form an SOI wafer (each of the above) Wafers are referred to as wafers. 90347.doc 1282136 The wafer is formed by setting the working process (working process conditions), which should be set according to the specifications in the device process, and the σ is supplied to the wafer ασ of the once-drying temple. 'Because the conventional wafer flatness definition sfqr (part flatness quality requirement = total wafer fluctuation range with respect to the focal plane) is derived from the wafer flatness seen from the thickness distribution of the wafer, that is, widely used in The thickness distribution obtained when the wafer is completely sandwiched on an ideal plane. In ^β, the code number 3201 refers to the profile of a part of the free standing state (5), and the code 3202 refers to the profile of the profile obtained when the part 3201 is completely sandwiched on the ideal flat surface. The flatness required in the lithography is from the point of view of the focus estimation, and the exposure device such as the scanner is in the state of the actual exposure as shown in Figs. 33C and 34C, and the state of the sense is rounded on the wafer holder. The flatness of the lower layer (referred to as "SFGQsr," in this book = book). Figures h A to J3C show the location near the center of the wafer (referred to as "complete part" in this book) ;) A cross-sectional view of the profile of the profile. Fig. 33A shows the profile of the entire portion in the free standing state, and Fig. 33B shows the profile of the profile and the flatness SFQR when the entire portion is completely sandwiched on the ideal plane. Further, Fig. 33C shows a cross-sectional view when the entire portion is sandwiched on a pin-out type wafer holder and the scanner senses flatness sfqr^. When the field uses a plug-on wafer holder. Reporting the flatness of the complete portion in the file SFQR is essentially the same as the flatness SFQRsr of the scanner. Figs. 34A to 34C are cross-sectional views showing the profile of a portion located at a position 1282136 (referred to as a "part portion" in the present specification) near the peripheral edge portion of the wafer. Fig. 34A shows the profile of the entire portion in the free standing state, and Fig. 34B shows the profile of the profile and the flatness SFQR when the portion is completely sandwiched on the ideal plane. Further, Fig. 34C shows a cross-sectional view when the portion is sandwiched by a pin-type wafer holder and the scanner senses flatness SFqrsr. Comparing Figs. 34B and 34C, the interaction between the edge shape of the wafer, the surface of the wafer holder and the structure of the sandwich portion has a large influence on some portions. Therefore, the flatness SFQRsr sensed by the scanner is very different from the flatness SFQR when the edge of the wafer is derived and the part is completely clamped to the ideal plane. For example, the flatness of the partial portion is reported in the file 2 as the flatness SFQR, depending on the position of the holding groove in the outermost peripheral portion of the wafer holder platform formed in the wafer. Further, in Table 3, the polishing pressure used in the CMP and the relationship with the center pitch of the wafer, the flatness after the crimping and the edge crimping are described. Document 1: Ding Fujisawa et al., CD-Controlled Wafer Flatness in lithography · Degree Analysis, Proc. SPIE 4691, pp. 802-809, 2002. Document 2: N·Podujen's “edge effect on flatness under 130 nanometer technology”, Proc·SEMI Japan Silicon Wafer Workshop, pp. 101-106, 2001. Document 3: Tetsuo Fukudan JEITA Flatness Study IV and Impact of edge crimping on CMP, 丨, [online] 2002.04.17 <, Advanced Wafer Geometry Task Force 2002 SEMICON/Europe (Munich), [Searched September 3, 2002], 90347.doc -9- 1282136 Internet < http://www.semi.org/web/japan/wstandards.nsfad8d609el7791 40a882567fa0057749a/6450bacea37331549256885001a4b5e/sFILE/020417% 20JEITA%Fltns%20IV.ppt > As mentioned above, the conventional crystals provided at the time of wafer purchase In flatness, the flatness of the holder used at the exposure time and the interaction between the wafer and the holder are not taken into consideration. Therefore, in particular, the flatness of some parts is different from that of the scanner, that is, The flatness of the exposure device is sensed. The result is to evaluate the wafer with high flatness by a conventional evaluation standard such as the SFQR evaluation standard, and the performance is not performed when the wafer is actually clamped on the holder of the exposure device. It is expected that the amount of change in focus is out of the estimation, and thus it is not easy to suppress CD variation within the range allowed. [Invention] The wafer flatness evaluation method according to the first aspect of the present invention includes measuring a wafer before and after Surface appearance; and dividing the front surface of the wafer into a plurality of locations. The flatness calculation method is selected according to the position of the evaluation portion, and the flatness in the surface of the wafer is obtained. The wafer according to the second aspect of the present invention The flatness evaluation device includes a measurement portion that measures a front surface shape of a wafer, and an acquisition portion that divides the front surface of the wafer into a plurality of portions, and selects a flatness calculation method according to the position of the evaluation portion and Obtaining a flatness of a wafer surface. A wafer manufacturing method according to a third aspect of the present invention includes: obtaining a wafer from an ingot according to a set working process condition; measuring a front surface shape of the obtained wafer; The front surface of the wafer is divided into several parts, and a flatness calculation method is selected according to the position of the evaluation part, and the flat surface of the wafer is obtained. 90347.doc -10- 1282136 Whether the flatness of the surface of the obtained wafer conforms to the flatness of the wafer surface of the wafer is in accordance with the estimation of Tianbei, and the fixed conditions of the factory are fixed; and when the surface of the wafer is not f: meal 0士&# 卞 不 不 不 卞 卞 预估 卞 卞 卞 卞 卞 卞 卞 卞 卞 卞 , , , , , , The wafer product method according to the fourth aspect of the present invention includes measuring the surface appearance of the money surface of the wafer; dividing the front surface of the wafer into a plurality of parts: 'according to the position of the portion, utilizing the The measured value of the front surface of the wafer before the wafer is such that the wafer is completely sandwiched on the ideal plane and the thickness distribution is calculated to be the flatness - the calculation method and the wafer retention according to the wafer The second calculation method of the front surface profile of the wafer obtained on the device is selected to calculate the flatness, and the flatness of the wafer surface is obtained by using a plurality of wafer holders; The flatness of the wafer surface of each of the plurality of wafer holders. The method for manufacturing a semiconductor device according to a fifth aspect of the present invention includes: taking out a wafer to be applied after the working process of the semiconductor device and before the lithography process, and measuring the front surface of the wafer before and after the wafer is taken. Dividing the front surface of the wafer into a plurality of parts, selecting a flatness calculation method according to the position of the evaluation part, i obtaining the flatness of the wafer surface; determining whether the flatness of the obtained wafer surface is maintained in accordance with the estimation The value of the demand is maintained at a value that does not cause a problem. When the flatness of the surface of the obtained wafer is maintained at the above value, the working process conditions of the working process and the lithography process are fixed; and when the flatness of the obtained wafer surface cannot be maintained At the above values, at least one of the working process conditions of the working process and the lithography process is changed. A semiconductor device manufacturing method according to a sixth aspect of the present invention includes measuring a 90347.doc -11 - 1282136-bit β/back surface profile, and dividing the front surface of the wafer into a plurality of partial circle-emitted positions Select a flatness calculation method and obtain the crystal. The flatness of the surface; the wafer is judged to be acceptable according to the obtained flatness, and a half conductor device is manufactured using the wafer determined to be acceptable according to the above determination. [Embodiment] The specific embodiments of the present invention are described in the accompanying drawings. In this essay, the similar parts in the drawings are given the general code. (First Embodiment) Before explaining the first embodiment, reference is made to the definition of the terminology and reference examples of the specific implementation of the present invention. 1A to id are plan views of a wafer. The desired person forms an integrated circuit on the entire individual surface of the wafer (7). However, it is practically impossible to form an effective integrated circuit on the entire surface of the wafer 100, as shown in Fig. 1A, which provides an edge exclusion region from the wafer 1 opposite to the sub-meter width. For example, the surface of the edge exclusion area can be used as an effective exposure area, and an effective integrated body can be formed in the effective exposure area. For example, the battery will be set close to the edge of the wafer 100 for flatness evaluation. The edge of the edge is 1 0 1 between the edge exclusion zone and the effective exposure zone. Figure (4) shows several parts divided on the surface before the wafer 100. A total of 56 parts were displayed in the map. For example, the flatness of the wafer 1 (8) is derived for each part. For example, in these parts, the part of the center of the R&D®100 does not cross the boundary line 101 and does not have a cut part ^, L is called a complete part as shown in Fig. 1c. Further, as shown in Fig. 1D, the portion around the edge of the sunken garden 100, the flow of 90347.doc -12-1282136 can be crossed across the boundary, the line 1G1, and the portion having the cut portion are referred to as partial portions. According to the size of the exposed area (or - lens) on the surface just before the wafer, Figure 2 shows the wafer flatness evaluation method associated with a reference example. First, as shown in Fig. 2, the wafer profile in the free standing state is actually measured on the front and back surfaces of the wafer (step 2〇1). Next, the front surface profile obtained when the actually measured wafer is completely clamped or fixed to an ideal plane is calculated (step 2〇2). ~ Then the ideal stratification is performed on the size of the predetermined part, and the estimated SFQR is the maximum value (10) 汴 minimum (10) 阶层 of the stratified residual value (step: 203). For the calculation of SFQR, in part of the calculation In the case of 彳0 + the same process with the same part of the cutting part, the difference is in the removal: the data outside the exclusion zone. ^ Therefore, in this reference example, in some parts, the wafer is not required Side: The interaction between the external shape, the surface of the wafer holder and the structure of the clamping part has a great influence on the flatness. Therefore, the inventor of this application believes that it is necessary to consider the wafer. The surface appearance setting standard is clamped to the wafer holder timepiece of the same type or the same specification as the exposure apparatus of (4), so that the wafer flatness evaluation is suitable for micro==. The evaluation sequence of the first embodiment of the invention is shown in Figure 3. Figure 3 is a flow chart showing the wafer flatness evaluation method according to the first embodiment of the present invention. As shown in Figure 3, the first embodiment is different from the reference example. It is in step 3〇1. In step 301, the method for calculating the flatness of the wafer surface is selected. 00347.doc -13 - 1282136 = that is, the position of the position to be evaluated is selected according to the position of the part to be evaluated: Part of the part or part of the whole part. In the part classified as part of the part, after the transfer and the edge of the wafer, the 'outer shape, the surface of the wafer holder 剞 ^ g 卜 ^ ' and the structure of the sandwich part The relevant assets are calculated, and the wafer edge is calculated after the clamping. 3) 2) The surface of the wafer is removed from the surface of the wafer. Estimate the exposure to break such as scanner sensing, the flatness SFQRsr (step 3〇3). At the same time, the number of types of wafer holders is one, and the number of wafer holders is one. For the port, the SFqRsr is calculated for each of the holders. For example, the worst of the calculated flatness values SFQRSR can be used as the flatness SFQRSR. Alternatively, the flatness SFqrsr can be proposed for each holder. In addition, the flatness SFQRSR is used. , can be used without the calculation, but can use the actual folder The wafer front surface of the wafer holder or the wafer on the same type of wafer holder is actually measured. The front surface of the wafer is selected to be completely sandwiched between the parts classified as the complete part. - The front surface shape calculation method is used on the ideal plane (step 304). Then, the ideal stratification process is performed for the predetermined part size, and the estimated SFQR is the tiered residual value "maximum value (·χ)_minimum Value step 305). Next, it is determined whether the estimated demand related to the change of the focus in the lithography is appropriate for the flatness SFQR and the flatness SFQRsr of the finished portion estimated from the two wafer flatness evaluation results ( Step 3〇6). 90347.doc -14- 1282136 The symbol (οκ) ' is used to ship or use the wafer to fabricate a half device. ^Inconsistent (NG)' then removes or reprocesses the wafer. According to the specific embodiment, the edge of the wafer edge and the mouth used for exposure can be used as part of the interaction. Therefore, when the wafer is sandwiched, the problem of evaluating the expected performance of the I-like method can be solved by using the holder of the exposure apparatus which is not used. In addition, the possibility that the amount of change in focus and enthalpy exceeds the estimate becomes low, and it is possible to suppress (3) from being within the allowable range. As a result, focus errors can be suppressed in a part of the portion, and the manufacturing yield of the semiconductor device can be improved. In the first embodiment, the evaluation site may be classified as a partial site or an intact site along with an example of classification of the evaluation site. However, the classification example is not limited to this situation. For example, as shown in FIG. 4A, it is estimated that the portion to be evaluated 4〇7 (4〇7a, .4〇%) is spaced from the wafer center 408 by D1 (Dla, mb) or the portion to be evaluated 4〇7 and boundary 2 101 The spacing D2 (D2a, D2b) is classified according to the resulting spacing. According to the above classification example, for example, the flatness evaluation of the entire portion can be performed on the same portion as the portion 4〇7c as shown in Fig. 4B. One of the advantages obtained by the above classification examples is explained below. For example, as shown in FIG. 4C, in some cases, when the distance between the portion to be evaluated and the center 408 of the wafer is too long, that is, when the portion is close to the edge of the wafer, the evaluation portion sandwiched on the holder 409 is regarded as crystal. The type of the round holder is in a protruding state. The part set to the highlighted state is represented by the code 41. When the clamped part is in a protruding state, the flatness will be completely different from the wafer's full flatness on the ideal flatness. Therefore, even in the case of the complete part, the flatness sfqr induced by the exposure device after the clamping is different from the flat soil temperature SFQRSR. In this case, 'even if the part is a complete part, the shelling item related to the front surface of the wafer and the surface of the holder is used, and the surface is pushed by the rear fork (3). Estimate the flatness of SFQRsr to assess the site. For example, to achieve the above evaluation, the distance between the estimated position and the center of the wafer 408 or the distance between the evaluation portion and the boundary line is calculated, and it helps to classify the parts according to the calculated distance. (Second embodiment)

In the Mm (4), a method of calculating the flatness SFQRsr of each part and determining the flatness according to the holder structure and the wafer profile measured in steps 3〇2, 3G3 and shown in Fig. 3 is employed. In the second embodiment, the final shape obtained in the wafer fabrication process, such as the free standing edge profile in the wafer surface, is considered relative in the direction of the radius vector (in the direction of the periphery of the wafer) Value. Therefore, the wafer appearance (upper, upper and lower surfaces) in the free standing state is judged, and the flatness of the wafer to be clamped is SFQRsr. The receiver evaluates the flatness SFQRsr of the wafer being sandwiched. Figure 5 is a flow chart showing a wafer flatness evaluation method in accordance with a first embodiment of the present invention. As shown in Fig. 5, the surface appearance of the edge portion of the wafer in the middle of the clamping is modeled (step 5 is called, and has a shirting effect in the lithography process. An example of the modeled appearance is shown in Fig. 6. 90347 .doc ~ 16 - 1282136 Next, when the parameters Zi, Z2, and X2 are changed, the flatness SFQR of the partial portion is calculated for the modeled shape (step 502). Then, the clipped crystal is calculated according to the estimated demand (step 503). The rounded edge appearance tolerance value (step 504). In this case, for a specific example, the flatness set by the estimated demand is set to 0.1 micrometer. If the calculation result shows that the parameter of Fig. 6 is not Ζ:, Z2 'again, The allowable range of X2 meets the following conditions, that is, it can meet the estimated demand. (1) Z60.12 micron (2) 〇$ Ζ2$0·12 micron (3) X23 0 mm (4) X222 mm In addition, standing freely After the lower edge portion, the surface profile is modeled (step 505). Next, it is estimated by simulation that when the wafer having the above-mentioned back surface shape is clamped to the a circle used for holding, it is sandwiched. After the influence on the shape of the front surface (v. 5 0 6). In this case, the formation of the free standing condition The model of the surface appearance after the wafer fabrication process, the measurement data of the wafer edge profile, etc. Figures 7A and 7B show the surface appearance after modeling and the process for performing the steps 505 and 506 of Figure $ Cross-sectional view of the circular holder. Previously known as the wafer manufacturing process, the surface of the wafer was tapered and the front surface was shaped. Therefore, it is assumed that the model of the back surface is tapered. The calculation result of the influence of the taper of the surface on the shape of the front surface after the wafer holder is clamped. 9〇347 d〇c -17- 1282136 ΘThe figure shows the start of the taper and the clip The relationship between the amount of deviation (the amount of taper) of the outermost peripheral portion of the circle formed on the wafer holder. That is, if the amount of taper is smaller than the amount shown in the figure, the wafer is completely clipped. Further, it is known that the amount of right taper is larger than the amount of deviation shown in Fig. 8, the wafer is not completely clamped and is in a 愁/Fu state (similar to a cantilever beam). Figures 9A to 9E show the L2a shown in Fig. 8 The state corresponding to L2e. By comparing the results obtained in steps 504 and 506 by the above procedure (step Step 507), the relationship between the formed profile conforming to the allowable specification of the flatness SFQRsr and the wafer edge profile after the clamping can be clearly understood (step 508). Figure 8-9 does not mean that the package can be clamped. The wafer is assumed to be in the following two states: (State 1) The back side of the wafer is completely attracted to the wafer holder because of the money sucking. In this case, 'determine the surface appearance of the wafer to be wafer and the wafer is completely— The ideal flat suction has the same back side shape. From the thus determined wafer surface appearance, the parameters Zi, z" as shown in Fig. 6 can be obtained. Then, it is determined whether the numbers 4 Ζ 2, χι, and & meet the above conditions (丨) to (4). (State 2) The side of the circle is not attracted by the suction of the six-------------------------------------------------------------------------- In this case, '? The surface of the wafer being sandwiched may be somewhat deformed by the clamping. The surface appearance of the wafer in the self-standing state is the top of the surface appearance of the wafer being sandwiched. Therefore, the surface appearance of the surface of the wafer can be determined by the appearance of the wafer surface under free standing. From the thus determined surface appearance, it can be obtained as shown in Fig. 1 Z2 X丨 and X2. Then judge these parameters Z丨, z2, Xd 90347doc -18-1282136, and the surface type is i=r:(:(4). The zirconium at the wafer table in the free standing state, the degree of influence of the surface appearance of the crucible can be determined from the edge of the wafer: 2. The relationship between the curvature of the wafer being sandwiched is determined. The wafer is in state 1 and state 2. More precisely, it is 'partially engraved—the 曰fan is attracted to the yen holder. If this is the case, then the surface of the squall-refer to the surface and wafer back The side is completely ideal and the timing is the same. i is the surface appearance of the second reference part of the wafer from the free standing surface, and the surface appearance of the free station. In step 5 0 6 , whether the full moon side of the wafer holder is in the state of being attracted to the wafer, and the wafer surface is shaped, depending on the type of wafer holder used. 5) It should be preferred to implement mode management for various types of wafer holders that can be used to hold wafers. In this embodiment, two The wafer holder performs the simulation, that is, the holder A and the holder B. Therefore, the flatness evaluation conforming to the estimated demand can be made by applying the above reference based on the surface appearance of the portion of the edge portion of the wafer. According to the above method, the relationship between the wafer edge appearance and the free standing state of the SFQRsr in accordance with the flatness tolerance specification can be discerned. Next, the flatness evaluation method according to the second embodiment is shown in FIG. The wafer screening method. In the example of the screening method shown in FIG. 10, the wafer edge shape and the free standing shape of the wafer conforming to the allowable specification SFQRsr estimated by the procedure shown in FIG. 5 can be achieved. The relationship between the rounded edges (step 1 〇〇1). In addition, and measure the wafer edge appearance in the free standing state (step 1 002). The amount of device 90347.doc -19- 1282136 γ is necessary to analyze Any measuring device for measuring the appearance of the wafer is not special; it is limited to the optical type 'contact type or electrostatic capacitance measuring type measuring instrument. In the less frequent 1 003, the sweat is estimated to meet the allowable specification of the number of parts and edge division: Zone' and determine the extent of the portion of the wafer that meets the estimated demand. Then select the applicability of the evaluated wafer and the performance in each of the marginal exclusion zones (steps)' and ship or supply the wafer to the re- In the second embodiment, the result of the first embodiment can also be achieved. Further, in the second embodiment, the shape of the 曰曰0 in the free standing state (visible side and back side) is determined. And obtaining the condition standard of the desired flatness SFQRsrg of the wafer to be clamped. Then, the evaluation of the wafer being clamped is evaluated. Therefore, the flatness SFQRSR needs to be estimated for each part, for example, the first embodiment of the disk In comparison, an advantage can be achieved in that the evaluation time can be reduced. (Third embodiment) 曰 = - and - in the second specific embodiment - The method of evaluating the yen flatness is selected according to the position of the portion evaluated. In the second-first/those embodiment, the flatness is not properly evaluated at the specific part of the site. (D) caused by the design of the -0 retainer Figure 11A is the holding of the wafer crying. FIG. 11B is a cross-sectional view taken along line 11B-11B of FIG. 11A. As shown in Figures 11A and 11B, there are three wafer carrying/replacement lift pin holes 1101 at the center of the holder and the clamping of the pin holes (10) is made. To mention:: It will not lead to a partial mention that its system is used as a wafer holding unit. No hooking can occur on the part of the 90347 doc -20 - 1282136 bolt hole 1101. Ten Dan: The part of the town on the lifting plate hole 11.1 is checked and the wafer is flat after the clamping. 曰 Figure 12 shows the flatness of the surface and the position of the position on the hole 1101 after the clamping. , Shi, e catching the relationship between the cattle and the king I m ten candid reduction. As can be seen from the relationship shown in Fig. 12, the degree of flatness attenuation is lower than that of Fig. 12 by the flatness of the lift pin hole 1101. In the big part, it causes trouble, that is, the flatness attenuation of the recording surface is unique. Therefore, in order to correctly evaluate the portion in the above-mentioned knives, in addition to obtaining the crystal 81 outer material, the wafer holder structure was obtained to apply the flatness evaluation method. This is a flat evaluation of the flatness evaluation method based on the assumption that the wafer shape is only based on the full clamping of the wafer type data. Furthermore, in the second specific embodiment, this loyalty can be the same effect. A specific embodiment is further achieved by the third embodiment, for example, not only at a portion but at a portion of a particular portion of the wafer holder, such as at a portion of the lift pin hole. At the same time, the flatness can be evaluated under the similarity of the flatness of the exposure device. As a result, as compared with the case of the first embodiment, the flat soil temperature can be evaluated in a state very similar to the induction flatness of the exposure apparatus. (Fourth Embodiment) In the first to third embodiments, 'interpretation of wafer flatness according to wafer-to-wafer holding: positional relationship can effectively reflect wafer flatness in a sandwiched state evaluation method. In other words, the fourth embodiment relates to the selection of the evaluation method = by paying special attention to the state of the wafer rear surface 90347.doc -21 - 1282136 rather than the positional relationship between the wafer and the wafer holder. In this case, the wafer flatness is correctly obtained under the condition of T and F. The method is detailed below. Figure 13A shows the wafer front surface local flatness (SFQR) measurement of the wafer's back surface. Similarly, Figure UB shows the local flatness measurement of the back surface of the wafer under the front surface of the wafer. In either case, most of the local flatness values are distributed below 5 nanometers and the distribution is very similar. The results obtained by investigating the conditions in more detail are shown in Fig. 14A" 14B. Fig. 14A shows the surface measurement results after the rear surface is clamped, and Fig. 14B shows the surface measurement results after the front surface is clamped. Each display has 64 areas of high flatness in the center of the wafer. For the sake of observation, the axis of Figure 14B is reversed. As shown in Figures 14a and i4B, the two cases are very similar. If the flatness of the above value, that is, the flatness of approximately 1〇〇11111{)邛 in the area of 64 111111 square, it is known that the wafer thickness distribution G is slowly transferred to the front surface even if the rear surface or the front surface is clamped. The same is true. In this case, "p-p " is the peak of the peak and it has the same meaning as the above nSFQR" (Fig. μ). In this experiment, it is known that the wafer holder is not noticeable, and substantially only the flatness of the wafer is measured, even if the X-axis is reversed in Figs. 14A, 14B. Figure 15A shows the free standing state of the wafer, and the flatness of the back surface of the wafer is lower than the front surface of the wafer. This is especially true in the case of a single polished wafer. When the rear surface of the wafer is clamped to the peg, the wafer stops deforming when the balance between the ruggedness of the wafer and the air pressure is reached, as shown in Figure 5B. Therefore, the wafer does not fully reach the height of the top end of the plug. In addition, the front surface of the wafer is flat. 〇347.doc -22 - 1282136 is extremely high. Since only the deformation with long wavelength and the irregular thickness of the wafer appear on the front surface of the wafer, if the front surface is clamped, the front surface of the wafer completely matches the plug, as shown in Fig. 15. If the front surface flatness of the wafer is measured in this case, this measurement is equivalent to the measurement of the wafer thickness distribution. The flatness of the flatness depends on the size and wavelength of the uneven portion on the front and rear surfaces of the wafer. It is seen that the concave and convex portions of the concave and convex portions appearing on the front surface side of the wafer have a long-wavelength deformation pattern and an irregular thickness, and the concave and convex portions such as those having a short wavelength are found on the rear surface of the wafer. Since the concave and convex portions seen on the front surface of the wafer have a long wavelength ', when the rear surface or the front surface of the wafer is sandwiched, it can be completely propagated to the un-sanded surface by the vacuum suction of the inspection. However, in the case where the short-wavelength concave-convex portion is formed on the rear surface of the wafer, the propagation mode end view differs depending on the size of the concave-convex portion, the wavelength, the bolt pitch of the plug, and the annular shape of the annular retainer. Therefore, in order to understand how the back surface flatness propagates to the front surface of the wafer, the wafer needs to be clamped to the wafer holder or simulated. Fig. 14B shows the resulting surface measurement result ' when the front surface of the wafer is fixed or clamped' and the result is substantially equal to the wafer thickness distribution result. As shown in FIGS. 16A to 16C and 17A to 17C, the results obtained by the simulation using the finite element method are used to determine whether or not the pattern of the pattern HB is clamped when the wafer having the surface thickness distribution after FIG. 14B is sandwiched. It is copied on the front surface of the wafer. Figure 16A shows the result of taking out part of the area 8 ηη combat 25 legs from the actual measured value of Figure 14B (33·3 _p_p in this example), attaching it to the ^ _ pitch bolt, and flattening it so The degree distribution is the flatness distribution of the back surface of the wafer (Fig. 16A). Deriving the front surface appearance of the wafer when deformed by atmospheric pressure (Fig. 16B: in this case, 29 legs 90347.doc -23 - 1282136 to the front surface). Similarly, the stress distribution on the plug is derived and the plug is brought into contact with the wafer as shown by the blank (Fig. 16C). Fig. 17A shows the result obtained by multiplying the flatness of Fig. 16A by only four, and estimating the rear surface flatness distribution of the wafer by the same method. The flatness of the 8mm x 25mm area is 133.2 nmp-p, and the pitch of the pitch of the 丨mm plug is set to the flatness of the rear surface of the wafer. The front surface appearance of the wafer obtained when the crystal is changed by atmospheric pressure is derived (Fig. 17B: in this case, 1〇9 8 P-P propagates to the front surface). Similarly, the stress distribution on the plug is derived and the plug is brought into contact with the wafer as shown by the blank (Fig. 17C). Figure 18 shows the relative relationship between the plug contact ratio derived from this method and the flatness of the wafer. In the case where the local flatness in the area of 8x25 mm2 is approximately 3 〇 nm p彳, near-loo% flatness propagates to support the experimental results of Figs. MA and 14B, but the contact rate decreases as the flatness decreases. Fig. 19 shows the flatness propagation rate value of the front surface facing the surface after the flatness value 11111 p_p of the front surface and the front surface are estimated. When the back surface of the wafer is sandwiched, a long-wavelength uneven portion exists on the front surface of the wafer. However, in this case, when it is estimated that the flatness of the rear surface of the wafer propagates to the front surface of the wafer, it can be regarded that 100% of the uneven portion is displayed on the front surface, and the propagation rate becomes a problem. Fortunately, the concavities with short wavelengths are only present on the back surface of the wafer. Therefore, even when the wafer 2 is in a free standing state, the result of measuring the wafer thickness distribution is regarded as the surface flatness distribution after the measurement of the back surface of the wafer when the front surface of the wafer is sandwiched, and no problem occurs (Fig. 13B). That is, even if the surface flatness after the abscissa of Fig. 19 is regarded as the flatness of the wafer thickness shown in Fig. 20, 90347.doc -24 - 1282136 "degrees" is no problem. By reading the flatness in this way, the abscissa is obtained by the general wafer thickness measuring device. In this way, the results can be predicted as a result of measuring the flatness of the surface before the wafer is clamped on the actual wafer holder. In the case of a statement, the latter is able to selectively evaluate the method to reflect the wafer flatness result required for the initial setting obtained under the straits. Figure 21 is the flow of the fourth embodiment of the present day and month. As the wafer thickness data, the thickness data in the free standing state can be used. The local flatness is calculated according to the thickness irregularity data obtained by using the back surface reference of the wafer (assuming that the rear surface of the wafer is completely flat by vacuum clamping) In the case where the result exceeds the reference value, for example, in Fig. 18, the flatness of the rear surface of the wafer exceeds nearly 30. In the case of &, the wafer is applied by the method for the local area = flatness ^ Sandwich simulation. Then calculate the surface shape after the deformation and a Π $ surface, calculate the local flatness according to the front surface appearance of the wafer; and output the final result. For each local area, the judgment exceeds the 'reference value or not, no need Perform FEM simulation on the entire local area. It is better to use the actual measurement or simulation to determine the reference value for each type of wafer. In addition, it can be used before being clamped on the actual wafer holder. For the flatness of the flatness, A is replaced by the non-wafer clamping simulation process in Fig. 21. More specifically, it is not shown in Fig. 22. In this case, as the thickness of the wafer, it is possible to see the color of the film. Thickness data. Based on the back surface of the wafer, the σ卩 flatness is calculated according to the thickness irregularity data (assuming that the back surface of the wafer is completely flat due to vacuum clamping). If the result exceeds the reference value, For example, consider the flatness of the back surface of the wafer in Figure 18. The flatness of the wafer is more than nearly nm. Then the wafer is clamped on the wafer holder, and 90347.doc -25-1282136::曰曰® front surface flatness. The flatness is used to calculate the local flatness, and the sub-charge is used for the final round-off. = According to the Philippine (four) which can be used to measure the entire surface in a short period of time, the flatness measuring device is at least partially out of reference.曰 round clamping 'Asia re-measures the entire wafer surface. It is better to determine the reference value for various types of wafers by actual measurement or simulation. Bu Τ Use the flow chart of Figure 23 to derive the wafer in the sandwiched state. Table: Flatness. In Figure 23, as the wafer thickness, The thickness data used in the free standing state. According to the thickness of the back surface reference, the thickness is not the same, and the partial flatness is determined. Then the conversion constant is determined according to the above result, and the first step as shown in Fig. 20 can be derived. The derived flatness conversion curve can be multiplied by the local flat value of the back surface reference and can be multiplied by ^ji as the final output. In this method, for the flatness of high precision: It is preferable to use a practical measurement or simulation to jointly derive a flatness transfer curve for various wafer and wafer holdings. (Fifth Embodiment) In the fifth embodiment, the wafer flatness according to the present invention is explained. The evaluation method evaluates the flatness flatness evaluation device. Fig. 24 is a block diagram showing a first example of the wafer flatness evaluation device according to the fifth embodiment of the present invention. The first-example configuration of the evaluation device is shown in FIG. Previously, the surface profile measuring device 24〇1 measured the wafer front surface profile evaluated in the free standing state and then the surface profile measuring device employed the measured surface profile.罝 、 、 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 The measurement device and the waiter type material are transferred to and stored in the a circle data storage unit 2403. The stored in the Japanese yen 0 枓 枓 can correspond to a plurality of sheets. In the case of 4 knives, the 曰曰 round is first held. Benefits of platform appearance - material storage in solid (4): (4) W etiquette related to the child's memory 04. The stored data is not limited to one type of holder data, and can correspond to a plurality of types of holder data. Crystal „Materials Department is the calculation unit 24〇5, and Beike Pu to + 呷 呷 邱 ... ... 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对Information on the distribution of parts (2) Γ : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : To estimate the distance = the distance D2 between the boundary UH and classify the part as close to the edge of the wafer according to the calculated distance The position and the portion away from the edge portion of the wafer (refer to the first embodiment, FIG. 4A, 4B). / a 3) classify the data according to whether the portion to be evaluated has an unpinned portion (refer to the second embodiment of the second embodiment) ). The information related to the structure of the clamping portion and the information about the appearance of the wafer holding portion platform are transferred from the holding unit 24 to the flat portion in parallel or in series with respect to the transfer of data from the wafer-poor storage unit 24 () 3 The degree calculation unit 24〇5. The flatness calculating unit 2405 performs the following flatness calculations (1,), (2丨), and (3丨) in accordance with the categories (1), (7), and (3). 90347 doc -27- 1282136 o') By considering the wafer holder ^ M is ^ to the related information of the Bu Li and the related poor gentleman's structure, the singer, the lane 10 W, Feng Xiaodao The part of the part is calculated as the time when the 曰 义 夹 is placed on the wafer holder _ aa® is to induce the exposure for each part I 〇 CF 〇 p clothing such as the flat product induced by the 描 器 ; ;; Calculate the front surface appearance obtained when the: 0 element' is sandwiched on the ideal plane for the part classified as the complete part.曰曰: 2') The essence of the wafer holder platform is related to the information of the external structure of the wafer holder. For the categorized person 尨#尨" π is the part close to the edge of the circle, calculate the 别拉 - 得杰上4 The edge of the wafer is outside the front surface of the wafer. The receiver pushes the warming + for each part to describe the SFQRsr sensed by the scanner. In addition, for Ding Yi, the W will enter the ten, the edge of the circle. The original surface appearance obtained when the 0 yuan king is clamped on the ideal plane. (3) By considering the wafer holding of the GI 外 外 external information and the structure of the clamping part ^, The unfinished portion ms is the front surface of the wafer edge portion when it is sandwiched on the wafer holder: the second connector is used to derive the flatness SFQRSR sensed by the exposure device such as the scanner for each part. If the part is not un-sanded, the front surface is obtained when the wafer is completely lost on the ideal plane. ~ If a wafer holder is used instead of a plurality of wafer holders, the calculation is performed for each holder. Flatness SFQRSR. For example, to calculate the flatness

The worst of the degrees SFQRsr is used as the flatness SFQRsr, or the flatness SFQRSR is derived for each holding Z. The data transfer i thus derived is lost: the determination unit 2406. In the pass/fail determination unit, the optimal stratification 90347.doc -28-!282136 is performed for each part, and the estimated SFQR is the "maximum (Max)_minimum (Mm)" The result refers to whether the thus calculated value will meet the estimated demand output related to the focus culture in the lithography. When the fourth flat embodiment history flatness evaluation method is performed, the flatness calculating unit 24〇5 performs the steps. 21〇3 to 21〇7, 2201, 2202, and 23〇1, as shown in the figure and to ^. According to the first example of the device to be evaluated, the flatness according to the first, third or fourth embodiment may be performed. A flatness evaluation process of the evaluation method. Fig. 25 is a block diagram showing a second example of the wafer flatness evaluation apparatus according to the fifth embodiment of the present invention. The configuration of the second example of the evaluation apparatus is as shown in Fig. 25. The edge front surface measuring device 2501 measures the surface appearance before the edge portion of the wafer to be evaluated in the free standing state, and measures the rear surface appearance of the edge portion with the edge portion rear surface measuring device (4). 2 training, coffee - two = and Given optical type or a contact type step order (with a difference in level) table, the table, or white so prepared, but not to such equipment and can resolve the above-described apparatus ^ "edge profile to the desired amount. The edge portion data is not in the Lr data storage portion 2503. The deposit of the museum, and the first ~ 'in some cases, can correspond to a plurality of tables. Like the A column, the wafer holder platform is firstly related to the following: "The relevant information is stored in the holder data storage. ^: The information stored in the file is not based on the -type holder data. The limit: and the following may correspond to a plurality of retainer data. If necessary, transfer the data stored in the holder data storage unit 2 to the wafer data storage unit 2503, the rod, and the stored material to the flatness calculation unit 90347.doc -29 - 1282136 2505 Retaining = material! In section 25Q5, when the wafer to be evaluated is clipped to the wafer 'day size, the surface appearance before the edge portion is drawn, and the parameters Ζι, 2 Xl, X2 are derived (see Figure 6 Second embodiment. Next, the parameters &, heart, X1, L derived by the flatness calculating unit 25〇5 are transferred to the pass/fail determination unit 25〇6. In the pass/fail determination unit Μ%, The number of parts that meet the permissible specifications, and determine the extent of the part that meets the estimated demand and the output.

In this case, the right use of a plurality of wafer holders instead of using one wafer holding II determines the extent to which each part of the wafer meets the estimated demand for each holder. Therefore, according to the second example of the evaluation device, the flatness evaluation processing according to the flatness evaluation method according to the second limb K can be performed. In the first and second examples, only the m-surround or the U2 wrap portion shown in Fig. 24 or 25 can be placed in the cleaning crucible, and the front surface profile of the wafer can be actually measured therein. The other parts can be placed away from the above parts. For example, the m-surrounding portion or the (four)-wound portion can be placed in the wafer fabrication company' and the buyer retains other portions, and it is determined that the pass/fail of the crystal is to be evaluated. (Sixth embodiment) A wafer manufacturing method using the wafer flatness evaluation method according to the present invention will be explained by way of a specific example. Fig. 6 is a flow chart showing a first example of the wafer manufacturing method of the sixth embodiment. 90347.doc -30- I282136 As shown in Figure 26, 曰m 丨 4 4 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i Forming the wafer' and achieving, for example, the wafer formation of the wafer according to the specific embodiment is determined according to the estimated demand - ... Go to the round #, 斤5 and 疋 疋 工作 工作 工作 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固According to the first implementation: back: in the wafer manufacturing process, the wafer work process 1 results can be achieved, for example, to efficiently manufacture wafers whose flatness meets the estimated demand. A specific example of the circular manufacturing method is shown in Fig. 27. Single crystal such as a stone single crystal As shown in Fig. 27, a semiconductor ingot is formed by a known method (step 2751). A block is then cut from the ingot (step 2752). The peripheral portion of the cut block is then inverted and/or ground to set the block diameter to, for example, 8 inches, 12 inches, etc. (step 2753). After that, the inverted and/or ground blocks are sectioned to obtain a coarse slit (step 2754). The edge of the rough wafer is then beveled and the edge of the rough wafer is applied as a predetermined profile, such as a tapered profile (step 2755). The front and/or back surface of the thus slanted rough wafer is ground and/or ground and/or etched to adjust the thickness of the rough wafer to a predetermined wafer thickness (step 2756). The front surface of the circle and/or the surface of the rough grain 90347.doc -31 - 1282136 which has been subjected to the process of step 2756 is then polished to obtain the final wafer (step 2757). Thereafter, the flatness of the final wafer surface is obtained by the flatness evaluation method of the first embodiment. If the flatness of the final wafer surface does not meet the estimated demand, then at least one of the working process conditions in steps 275 1 through 2757 is changed. For example, as shown in Fig. 28, the above wafer fabrication method can be carried out in accordance with the second embodiment or the third or fourth embodiment. The flatness evaluation information can be obtained by using at least the flatness evaluation method according to one of the second to fourth embodiments, and the evaluation information thus obtained is fed back to each working step of the wafer manufacturing process to achieve the above. The same advantages of wafer fabrication methods. The above wafer fabrication method is one example of a method for forming a wafer having a mirrored surface on one side/double side. However, the wafers produced by the above wafer fabrication method are not limited to wafers having mirrored surfaces on one side/double sides. An example of a fabricated wafer, such as an annealed wafer obtained by heat treatment of a mirrored surface wafer 2901 (FIG. 29A); an epitaxial wafer obtained by forming an epitaxial layer 2903 on a mirrored surface wafer 2901 ( FIG. 29B); or an SOI wafer obtained by sequentially forming an insulating layer 2904 and an SOI layer 2905 on a support substrate, such as a given mirrored surface wafer 2901 (FIG. 29C). Having various types of annealed wafers, as shown in FIG. 29A, may be given a wafer on which a DZ (bare area) layer 2902 is formed by heat treatment, or a diffusion of dopants having diffusion therein by heat treatment. Wafer. In addition, there are various types of SOI wafers, or an adhesive SOI wafer with two lamellae can be given. It is undoubted that the wafer flatness evaluation method of the present invention can be performed on a wafer other than the wafer shown here, and the evaluation method can also be used to form the wafer. 90347.doc 1282136 (Seventh embodiment) A wafer quality assurance method using the wafer flatness evaluation method according to the present invention is explained in the seventh embodiment. In summary, the guaranteed SFQR value, for example, related to flatness, is displayed only on a quality assurance sheet dedicated to displaying wafer quality. In other words, according to the wafer flatness evaluation method of the foregoing specific embodiment, the flatness of, for example, a portion protruding from the upper surface of the substrate or a portion located at a specific position on the wafer surface in the portion of the wafer is evaluated, wherein the wafer is actually Secured to the wafer holder or assumed to be attached to the wafer holder. The wafer surface diameter varies depending on the type of wafer holder. The location of a particular part of the wafer deck also varies with the type of wafer holder. That is, the actual flatness of the portion sensed by the exposure device varies depending on the type of wafer holder. If wafer flatness evaluation is performed on various types of wafer holders, the flatness evaluation process performed is highly accurate. Fig. 30 is a view showing an example of a quality assurance sheet obtained by the wafer quality assurance method according to the seventh embodiment of the present invention. As shown in Fig. 30, for various types of holders (such as holder A, holder B, ..., holder Y, holder Z), the edge exclusion zone will be set to 3 mm, 2 mm, and 1 mm. The guaranteed SFQR value (AAA, ZZZ search) obtained after the system is not particularly marked by the quality assurance morning. The wafer purchaser can detect the type of the holder based on the quality assurance sheet and consider the guaranteed SFQR value specifically marked on the holder type as the flatness of the purchased wafer. Therefore, by guaranteeing the quality of the wafer, for example, guaranteeing the flatness of the wafer surface of various wafer holders, it is ensured that the flat surface of the wafer is flat 90347.doc S -Λ * - 1282136 It is determined to be close to the actual flatness sensed by the exposure device. Since wafer flatness can be ensured for all types of dome holders, it is advantageous for wafer purchasers to manufacture fine semiconductor integrated circuits at a manufacturing yield, such as the semiconductor integrated circuit device of the i00 nano generation. (Eighth Embodiment) The wafer flatness evaluation method shown in the first to fourth embodiments can be similarly applied to a semiconductor device manufacturing method. FIG. 31 is a flow chart of a method for fabricating a semiconductor device according to an eighth embodiment. As shown in FIG. 31, a working step is performed before the lithography process, for example, an oxidation step 3006, chemical vapor deposition (CVD). Step 3〇〇7, electrode formation (e.g., sputtering) step 3008, ion implantation step 3〇〇9. One of the working steps 3006 to 3〇09 and the lithography process 3 are sequentially performed and repeated to fabricate a semiconductor device. The lithography process 3000 begins with a photoresist process (photoresist coating, baking) step 3〇〇1, and an exposure step 3〇〇2 is performed after the reticle alignment step is performed. Then, in the developing step, the exposed photoresist is developed, and the photoresist pattern obtained in the developing step is used as an etching step 3004 (for example, if the next step is an ion implantation step 3009, in some cases, the step may be omitted. In the middle of the mask, the base layer is engraved. Finally, the lithography process is terminated by the two-way peeling of the photoresist stripping step 3〇〇5. Such as Wu

The flatness of the stone wafer, while being set close to the actual flatness sensed by the exposure device, helps to improve the manufacturing yield of the semiconductor device. From a similar point of view, if the evaluation process: the flatness of the base layer, while it is close to the actual flatness induced by the exposure device, it is helpful to improve the manufacturing yield of the semiconductor device. Therefore, as shown in the present example, the wafer being processed is taken out after the working steps 3_ to 3_ and before the lithography process, and for example, the wafer edge inspection step (4) 1G is performed on the wafer to be taken out. In the edge inspection step EM, the wafer edge profile is examined and, for example, the flatness evaluation process not described in the second embodiment described in the fifth embodiment is performed. In the evaluation process, the information available is the flatness of the wafer being processed', for example, whether the flatness of the base layer in the process is maintained at the estimated demand value, or maintained above the estimated demand value without causing There is a problem with the actual manufacturing process. If the base layer in the process is flat: the denier is maintained at an appropriate value or maintained at a value that does not cause problems in the actual manufacturing process, the working process conditions of the steps 3_ to 3_ and the lithography step 3〇〇1 are The working process conditions of 3005 are fixed. In other words, if the flatness of the underlying layer being processed is neither an appropriate value nor a value that does not cause problems in actual manufacturing, then at least change the working steps from 3 to 3 and the lithography step to Na. A working process condition. Therefore, the working process conditions are optimized to maintain an appropriate value or to maintain a value that does not cause problems in the actual manufacturing process. In the κ example, the flatness evaluation method according to the second embodiment is applicable to a semiconductor device manufacturing process, but the flatness evaluation methods according to the first, third, and fourth embodiments are applicable to a semiconductor device manufacturing process. Therefore, if the wafer flatness evaluation method shown in the first to fourth embodiments is applied to the semiconductor device manufacturing method, the manufacturing yield of the semiconductor device can be further improved. The invention has been described with reference to the first to eighth embodiments, but the present invention is not limited to the above specific embodiments, and may be used without departing from the technical scope thereof when utilizing the present invention. Various improvements. Further, the above specific embodiments may be individually performed or may be appropriately combined and implemented. The above specific embodiments are examples, and have substantially the same configuration as the technical concept described in the patent application scope of the present invention. Any type of specific embodiment that provides the same operations and effects is included in the technical scope of the present invention. The invention of each stage is included in the above specific embodiment, and the invention of each stage can be obtained by appropriately combining the plurality of components disclosed in the above specific embodiments. As described above, according to the above specific embodiment, the wafer flatness evaluation method* can evaluate the flatness in the wafer surface, and can be set to be close to the flatness of the exposure* device; the wafer flat performing the evaluation method Degree evaluation device; wafer manufacturing method using the evaluation method; wafer quality assurance method using the evaluation method; semiconductor device manufacturer using the evaluation method, and semiconductor device using the wafer evaluated by the evaluation method掣Method of making. Lu, who is familiar with this artist will easily think about additional advantages and improvements. Therefore, the invention should be broadly modified and not limited to the specific details shown and described herein. Various improvements may be made without departing from the spirit or scope of the overall inventive concept as defined by the accompanying patent application and its special effects. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A, IB, 1C, and 1D are plan views of a wafer; 90347.doc -36 - 1282136 FIG. 2 is a flow chart showing a wafer flatness evaluation method related to a reference example; A flowchart of a wafer flatness evaluation method not according to the first embodiment of the present invention; FIGS. 4A, 4B and 4C are plan views showing wafers of another type of example; FIG. 5 shows a crystal according to a second embodiment of the present invention. Figure 5 shows a surface profile of the edge portion of the formed wafer; Figures 7A and 7B show a cross-sectional view of the surface profile and a wafer holder after modeling; Figure 8 shows FIG. 9A, 9B, 9C, 9D, and 9E respectively show state diagrams of L2a to L2e shown in FIG. 8; FIG. 10 shows a second embodiment according to the present invention. FIG. 11A is a plan view of a wafer holder; FIG. 11A is a plan view taken along line 11B-11B of FIG. 11A; FIG. 12 is shown in a specific portion. Rear surface flatness and flatness attenuation after clamping Figure 13 A shows the measurement results of the local flatness of the wafer (the rear surface is clamped, the front surface is measured); Figure 13B shows the measurement result of the local flatness of the wafer (the front surface is clamped, the back surface is measured) Figure 14A shows the results of the detailed study of the local flatness of the wafer (9 〇 347.doc -37 - 1282136 surface after the measurement, the front surface is measured); Figure 14B shows the detailed research results of the local flatness of the wafer (clip) Figure 1 5 shows the wafer profile in the free standing state; Figure 15B shows the diagram in the state where the back surface of the wafer is clamped to a pinch; Figure 1 5 C Figure 16A, 16B, and 16C show the back surface flatness distribution of the wafer corresponding to a plug position, the simulation result of the modified wafer, and the stress on the plug. Distribution Diagrams; Figures A, 17B, and 17C show the wafer back surface flatness distribution corresponding to a plug position, the simulated wafer simulation results, and the stress distribution on the plug; Figure 18 shows the wafer back surface flatness and Relationship between constant speed; Figure 19 shows crystal Figure 2 shows the relationship between surface flatness and front surface flatness. Figure 20 shows the relationship between the anti-sense ten-degree and the flatness of the surface of the wafer according to the thickness of the wafer. Figure 21 shows the first representation according to the present invention. FIG. 22 is a flow chart showing a second example of a wafer flatness evaluation method according to a fourth embodiment of the present invention; FIG. 2 is a flowchart of a first example of a wafer flatness evaluation method according to a fourth embodiment of the present invention; 3 is a flow chart showing a third example of the method for evaluating the flatness of the flatness of the fourth embodiment of the present invention; FIG. 24 is a view showing the wafer of the fifth embodiment of the present invention. A block diagram of a first example of a flatness evaluation device; FIG. 2 is a block diagram of a second example of a device according to a fourth embodiment of the present invention. 90347.doc -38- 1282136 26 is a flow chart showing a first example of a wafer manufacturing method according to a sixth embodiment of the present invention; and FIG. 27 is a view showing an example of a process of the first example of the wafer manufacturing method according to the sixth embodiment of the present invention. Figure 28 shows the sixth item according to the invention Figure 29A shows a cross-sectional view of an annealed wafer; Figure 29B shows a cross-sectional view of an amorphous wafer; Figure 29C shows a cross-sectional view of an SOI wafer; FIG. 30 is a view showing an example of a quality assurance sheet obtained by a wafer quality assurance method according to a seventh embodiment of the present invention; FIG. 31 is a flow chart showing a method of fabricating a semiconductor device according to an eighth embodiment of the present invention; Figure 3 is a cross-sectional view showing a section of a portion in a free standing state and a section in which the portion is completely cooled on an ideal plane; Figures 33, A, 33B and 33C are sectional views showing a complete portion; And the cross-sectional views of Figs. 34A, 34B, and 34C show a section of a portion. [Description of Symbols] 100 Wafer 101 Boundary Line 102 Edge 103 Effective Exposure Area 104 Edge Exclusion Area 90347 doc -39- 1282136 105 Complete Part 106 Partial Section 407, 407a, 407b Evaluation Area 408 Wafer Center 409 Holder 410 Projection 411 Holder bank 412 Bolt pitch (fixed value) 413 Projection amount (set to fixed value) 1101 Lifting bolt hole 1102 Bolt clamping part 2401 Front surface external measuring device 2402 Rear surface measuring device 2403, 2503 wafer data storage unit 2404, 2504 holder data storage unit 2405, 2505 flatness calculation unit 2406, 2506 pass/fail determination unit 2501 edge portion front surface outer type measuring device 2502 edge portion rear surface outer type measuring device 2901 Mirror surface wafer 2902 exposed area layer 2903 stupid layer 2904 insulating layer 2905 SOI layer 90347.doc -40- 1282136 3001 3002 3003 3004 3005 3006 The wafer rear surface flatness distribution corresponding to the position of the pin clamp is in this case The result is a crystal circular change simulation of 33.3 nm pp FEM (predicted wafer front surface appearance). In this case, 29 nm pp propagates to the front. The surface stress distribution is in this case, almost touching all the plugs = the wafer surface and the holder overlap the wafer post-surface flatness distribution corresponding to the plug position of the plug in this case is the crystal circular change of 133.2 nm pp FEM Simulation results (predicted wafer front surface profile) In this case, 109.8 nm pp propagates to the front surface stress distribution. In this case, 164 plugs are contacted in 225 plugs 90347.doc -41 -

Claims (1)

1282^^第57号 Patent Application Chinese Application Patent Renewal (December 95) Pickup, Patent Application Range: 1. A wafer flatness evaluation method, including: ~ measuring the surface appearance of a wafer before and after; And the front surface of the wafer is a plurality of parts, and the flatness calculation method is selected according to the position of the evaluation part, and the flat surface of the wafer surface is obtained. (4) Material (4) - Part (4) Select the complete part; 4 When the evaluation part is the complete part, select the first-calculation method, which uses the wafer before the surface wafer is completely cooled on a phase plane = the value of the The thickness distribution obtained on the surface of the BU is measured by a thousand t degrees, and when the evaluation part is part of the part, the second is selected: ::?::: The wafer is fixed to the wafer holder When obtained from the top: 忒曰曰0 is the surface appearance distribution, and the flatness is calculated. A wafer flatness evaluation method includes: measuring a front surface shape of a wafer; and dividing the front surface of the wafer into a plurality of parts, selecting a flatness calculation method according to a position of the evaluation part, and obtaining a wafer The distance between the evaluation part of the surface and the center of the crystal, and (4) the part and the edge of the edge of the wafer for the evaluation of the flatness are the distance between the middle and the outer line. # y^ The distance is selected by the calculation method; 1) When the evaluation site is fixed to the wafer holder, the first method is selected, which is obtained when the wafer is fixed on a wafer holder. The surface of the wafer is distributed on the surface, and the flatness is calculated. In the evaluation of 90347-951208.doc 1282136, it is estimated that the wire is fixed on a wafer holder, and the second calculation method is selected, which uses the crystal. Before the circle, the surface of the surface is 1 冽I, and the flatness is calculated according to the assumption that the wafer is completely sandwiched on an ideal plane. 3. A wafer flatness evaluation method, comprising: measuring a front surface shape of a wafer; and dividing the front surface of the wafer into a plurality of parts, according to the evaluation part; Flatness calculation method and obtain the flatness in the wafer surface. 4. A method for evaluating a wafer flatness, comprising: measuring a front surface shape before and after a day of the Japanese yen; and dividing the front surface of the wafer into a plurality of parts 'outside the wafer holder of the evaluation portion The flatness in the surface of the wafer is selected.千坦...method' and obtain 5 如 申请 申请 申请 第 第 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂 夂The value is based on the assumption that the crystal solid element is all clamped to the first calculation method of an ideal flatness, and the calculation of the end of the W ^ is calculated according to the § Hai wafer fixed on a wafer holding gain. In the second calculation method of the wafer, a bomb with a different flatness is selected as the flatness calculation method. 6. In the case of the patent application scope item 5, the date of the thousand-degree evaluation method, j: in the actual fixation of the wafer in a crystal-medium fine measurement, the bucket door is obtained The front surface profile of the wafer obtained in the actual bonded state. Oral-style hand-held office 90347-951208.doc 1282136 7. If the patent application scope is 5th θ θ, the member's day-to-day evaluation method, in which the wafer is virtually fixed on a wafer. Hold on, and hunter by the use of the sandwich feature of the wafer holder, you can get the θ a < β海日 when the wafer is fixed on the wafer holder The surface of the Japanese yen is 5 wai. 8. A method for evaluating wafer flatness, comprising: measuring in a free standing state - thickness variation of a wafer; and assuming that the rear surface of the wafer is corrected to a flat surface according to the measurement result, and is derived under the back surface reference of the wafer The local flatness, · derives the flatness conversion constant corresponding to the local flatness on the basis of the back surface of the wafer; and the value of the conversion constant according to the flatness and the flatness of the flat surface reference Calculate the local flatness of the wafer front surface μ when the wafer holder is clamped. 9. A wafer flatness evaluation method comprising: measuring a thickness variation of a wafer in a free standing state; and assuming that the rear surface of the wafer is corrected to a flat surface according to the measurement result, and deriving under the reference of the rear surface of the wafer Partial flatness; < When the local flatness under the wafer back surface reference does not exceed a preset value, the local flatness portion under the wafer back surface reference is used as the final result, after the wafer The local flatness under the surface reference exceeds the value of the "pre-measurement", that is, the simulation of clamping the wafer on a wafer holder; and the wafer is clamped to the wafer according to the simulation result. The local flatness of the front surface of the wafer on the device. 90347-951208.doc 1282136 ίο, A method for evaluating the flatness of a wafer, including: · Measuring the thickness variation of a wafer in a free standing state; The measurement results correct the back surface of the wafer to a flat load, and derive the local flatness under the back surface reference of the wafer; when the local flatness under the reference of the back surface of the wafer does not exceed , the value of 'will be in the local flatness part of the wafer back surface reference: the final junction S, when the surface under the wafer back surface reference - large λ!, out of the preset value 'that is the crystal The wafer is mounted on a wafer holder and the wafer front surface is calculated according to the state of the wafer. — 11 A wafer flatness evaluation device, comprising: a front surface after measuring a wafer a measuring portion of the type; - dividing the front surface of the wafer into a plurality of parts, a plurality of positions according to the position of the evaluation portion - a flatness calculation method and taking the flatness of the round surface; and a circle-selector for evaluating When the part is a complete part, the different method is selected, which uses the measured value of the front surface of the wafer before the wafer is completely clamped to a phase distribution, and the flatness is calculated; The thickness of the film obtained by the second layer is estimated to be 部分. When part of the 卩 position is selected, the surface of the wafer is affixed to the front surface of the wafer when the wafer is fixed on a wafer holder. 'Calculating flatness. 12·- kinds of wafer flat The evaluation device includes: - measurement - measurement of the front surface of the wafer before and after the surface - dividing the front surface of the wafer into a plurality of parts: the acquisition part, 90347-951208.doc 1282136 The wafer rear surface shape selects a flatness calculation method and obtains the flatness of the wafer surface. 1 3 · A wafer flatness evaluation device, including: · Measurement of the surface appearance of the wafer before and after the wafer And a portion for dividing the front surface of the wafer into a plurality of portions, and selecting a flat second calculation method based on the surface appearance of the wafer holder under the evaluation portion and obtaining the flatness of the wafer surface. 14 · A wafer flatness evaluation device, including: 7 measured in a free standing state - measurement of thickness variation of a wafer: a partial flatness acquisition portion that corrects wafer facets to - flat according to measurement results Subsurface's local flatness under the back surface reference of the wafer; ^Tan conversion constant acquisition unit, which obtains a flatness conversion constant corresponding to the local flatness of the wafer surface: a calculation unit that (4) the flatness conversion f value and the local flatness at the wafer rear surface reference, and calculates the local flatness of the wafer front surface. worship. °上上15· A wafer flatness evaluation device, comprising: a portion; measuring a thickness variation of a wafer in a free standing state, a partial flatness obtaining portion, the rear surface being corrected to a flat surface and a flat portion Degree; it assumes that according to the measurement result, the wafer is taken under the reference of the back surface of the wafer, and the local flatness under the wafer back surface reference does not exceed a preset value. When the local portion of the wafer back surface reference is used as the final result, when the flatness of the flat surface P under the wafer back surface reference exceeds the preset value, the wafer is clamped. The simulation on a wafer holder, and the 曰β10 calculation, based on the simulation results, calculates the local flatness of the front surface of the wafer when the wafer is clamped to the wafer holder. 16. A wafer flatness evaluation apparatus comprising: a measurement of thickness variation of a wafer in a free standing state, a local flatness acquisition section that corrects a surface of the wafer 4 to a flat surface based on a measurement result Lower's local flatness under the wafer back surface reference; a clamping portion, which will be the final result in the crystallographic portion when the wafer rear surface does not exceed a predetermined value, when the width exceeds the preset value, the holder is on; Flatness is the local flatness of the flat surface of the back surface of the flat surface. The local flatness of the wafer is clamped to a wafer. δτπ砟, which is based on the local flatness of the nose in the pinch state. The round manufacturing method includes: = the working process condition of the q is obtained from the ingot; a wafer is obtained from the front surface of the wafer; and the front surface of the wafer is cut into several parts, According to the evaluation part of 90347-951208.doc 1282136, take the flat surface of the wafer = where the flatness calculation method is selected according to the part of the evaluation part -, ^ position, when the evaluation part is the complete part, the second calculation The method 'is to use the wafer before and after the table. ^ ^ p, , -, i / 里 值 而 根据 假 假 假 完全 完全 完全 完全 完全 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Fix the surface profile before the wafer is held on the wafer holder II, and calculate the flatness; determine whether the flatness of the obtained wafer surface meets the estimated requirements:; The working process conditions will be fixed according to the estimated demand; and when the flatness of the surface of the wafer obtained by ρ is not in conformity with the estimated demand, the working process conditions to be set will be changed. 18) a method of wafer fabrication, including: · obtaining from the ingot according to the set process conditions - measuring the front and back surface of the obtained wafer; 卞 = the front surface of the wafer is divided into several parts, According to the evaluation part::: The back surface shape selects a flatness calculation method, and obtains the flatness of the wafer surface; determines whether the flatness of the obtained wafer surface conforms to the estimation. When the obtained wafer surface is flat Compliance with... The working process conditions are fixed; and the time is set to 'set the sound of the flat surface of the wafer surface. The process condition = when it is difficult to meet, the upcoming 90347-951208.doc 1282136 19 · A wafer The manufacturing method includes: ··=: the working process conditions are obtained from the ingot-wafer; the front surface of the wafer is known in the measurement; the front surface of the wafer is divided into several for the knife edge J The position, the flatness of the wafer surface is obtained according to the surface of the wafer holder of the evaluation site 4 - the flatness calculation method 'and determines whether the flatness of the obtained wafer surface meets the estimated demand, · when the obtained wafer The flat surface sweeping zinc-producing cats #11, when the estimated demand is met, the working process conditions will be fixed; and when the flat surface of the obtained wafer is not worth the estimated demand, The process conditions of the upcoming work will change. 20. The wafer manufacturing method according to any one of claims 17 to 19, wherein the wafer is mirrored on a surface wafer, a scorpion day, a solid surface, an annealed wafer, and an SOI wafer. one. 21 - a wafer quality assurance method, comprising: measuring a front surface shape of a wafer; dividing the front surface of the wafer into a plurality of parts, depending on the position of the evaluation part, before utilizing the front surface of the wafer The first calculation method of the thickness distribution 4 different flatness obtained when the wafer is completely cooled on the - ideal plane, based on the assumption. τ外万凌 and a second calculation method for calculating the flatness according to the surface profile distribution of the wafer obtained when the wafer is fixed on a round holder, the method for calculating the flatness is selected, and The flatness of the wafer surface is achieved using a plurality of wafer holders and the flat surface of the wafer surface of each of the plurality of wafer holders is guaranteed to be flat 90347-951208.doc 1282136 degrees. 22· a wafer quality assurance method, comprising: measuring a front surface shape of a wafer; dividing the front surface of the wafer into a plurality of parts, according to the rear surface appearance of the wafer of the evaluation part, The calculation method for calculating the flatness of the thickness distribution obtained from the front surface of the wafer before the wafer is completely sandwiched on an ideal plane, and the method of calculating the flatness according to the wafer In the second calculation of the flatness of the wafer before the wafer is obtained on the wafer holder, the method for calculating the flatness is selected, and the wafer surface is obtained by using a plurality of wafer holders. Flatness; and the flatness of the wafer surface of a plurality of wafers (4) for each material. 23. A wafer quality assurance method, comprising: measuring a front surface shape of a wafer; dividing the front surface of the wafer into a plurality of parts, according to the evaluation part below the outer surface of the φ/yen (10) , the measurement of the back surface before using the wafer! The calculation method is based on the assumption that the thickness of the wafer is completely sandwiched on the surface, and the wafer is obtained by attaching the wafer to a wafer holder: The calculation of the front surface shape distribution is based on the method of using the factory-and the method, and using a plurality of wafer holders to obtain the flatness of the wafer surface; and ensuring the plural The wafer surface of the wafer holder is flat 90347-951208.doc 1282136 degrees. 24. A semiconductor device manufacturing method, comprising: taking out a wafer being applied after a working process of the semiconductor device and before the lithography process; measuring a front surface shape of the wafer before taking the wafer; The front surface is divided into several parts, and the flatness calculation method is adopted according to the position of the evaluation part, and the wafer surface is obtained: the flatness degree is calculated. The flatness calculation method is selected according to the partial part or the complete part of the evaluation part, and is evaluated. When the part is a complete part, the first = calculation method is selected, which uses the measured value of the front surface appearance of the wafer and calculates the thickness distribution obtained by assuming that the wafer is completely sandwiched on an ideal plane. Flatness; when evaluating part of the part, the second method is selected according to the surface profile of the wafer obtained when the wafer is fixed on a wafer holder, and the flatness is calculated. Degree; determine whether the flatness of the surface of the obtained wafer is maintained at a value that meets the estimated demand φ or is maintained at a value that does not cause a problem; when the flatness of the obtained wafer surface is maintained at When the value is about to work fixing process and a lithography process of working the process conditions; and when the flatness of the resultant wafers Si plane was not maintained at the above values, i.e., changing at least one of the working process and a lithography process of working the process conditions. 25. A method of fabricating a semiconductor device, comprising: taking out a wafer being applied after a working process of the semiconductor device and before the lithography process; measuring a front surface shape of the wafer before being taken; 90347-951208.doc 1282136 Dividing the front surface of the wafer into a plurality of parts, selecting a flatness calculation method according to the rear surface appearance of the wafer of the evaluation part, and obtaining the flatness of the wafer surface; The flatness is the value or is maintained at a value that does not cause a problem. When the flatness of the surface of the obtained wafer is maintained at the above value, the working process conditions of the process and the lithography process are fixed; and the flatness of the obtained wafer surface is obtained. When the above values cannot be maintained, at least one of the working process conditions of the working process and the lithography process is changed. 26. A method of fabricating a semiconductor device, comprising: removing a wafer being applied after a working process of the semiconductor device and before the lithography process; and measuring a front surface of the wafer before being taken; The front surface of the 11 is divided into a plurality of parts, and the flatness of the wafer surface is maintained according to the evaluation of the wafer holding 3| The value of the estimated demand is maintained or maintained at a value that does not cause problems; the flatness of the wafer surface obtained by the work is maintained at the above-mentioned process and the lithography process is fixed, and the flatness of the obtained wafer surface is obtained. It is impossible to change at least one of the working conditions of the above-mentioned numerical ridge, that is, the 77- Μ main road (4) process. • The manufacturing method of the seed conductor device includes: measuring the surface appearance of the front surface of the I-wafer; 90347-951208.doc 1282136 cutting into several parts, according to the evaluation part ==: flatness calculation method, and obtaining crystal The method for calculating the flatness of the circle L is based on the evaluation of the partial portion of the portion of the portion of the U-position and the method of calculating the complete portion of the evaluation site, which is based on the measurement of the surface of the back surface before the use of the wafer, according to the assumption that the (10) is completely When calculating the thickness distribution obtained on the ideal plane, calculate the flatness; and when evaluating the ^^ ^ ^ and the basket-呌管士,上廿〆促系口口, select the method, the system The flat sound is calculated according to the surface appearance distribution of the wafer before the wafer is fixed on the wafer holder. The wafer is judged to be acceptable according to the obtained flatness. In this paper, Yan Yan, j疋 疋 疋 可接受 可接受 可接受 可接受 可接受 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The front table Dividing the surface into a plurality of locations 'the selection of the back surface of the wafer according to the evaluation portion - the flatness calculation method, and obtaining the flatness of the wafer surface; determining whether the wafer is acceptable according to the obtained flatness; and A wafer manufacturing-semiconductor device which is determined to be acceptable according to the above determination. A semiconductor device manufacturing method includes: measuring a front surface of a wafer before and after a wafer; The surface is divided into several parts, and a flatness calculation method is selected according to the surface of the wafer holder, and the flatness of the wafer surface is taken, and the flatness of the wafer surface is taken; 90347-951208.doc -12- 1282136 Wafer is acceptable or not; and body = wafer fabrication according to the above determination is acceptable. The manufacturing method of the semiconductor device includes: measuring the thickness variation of a wafer in a free standing state; Under the assumption that the back surface of the wafer is corrected to a flat surface according to the measurement result, the local flatness under the reference of the back surface of the wafer is derived; the derivation corresponds to the crystal The local flatness conversion constant of the local flatness under the circular back surface reference; calculated according to the value of the flatness conversion constant and the flatness under the wafer back surface reference' before the wafer holder is clamped The local flatness of the surface; determining whether the wafer is acceptable or not according to the above calculation; and using the wafer fabrication apparatus determined to be acceptable according to the above determination. 31. A semiconductor device manufacturing method, including: · standing freely Measuring the thickness variation of a wafer under the condition; under the assumption that the back surface of the wafer is corrected to a flat surface according to the measurement result, the local flatness under the reference of the back surface of the wafer is derived; when the surface is under the reference of the back surface of the wafer When the flatness does not exceed a preset value, the local flatness portion under the wafer back surface reference is used as the final result. When the local flatness under the wafer back surface reference starts from the preset value, Performing a simulation of clamping the wafer on a wafer holder; % ° calculating the wafer based on the simulation result when the wafer is held on the crying 90347-951208.doc -13- 1282136 local flatness of the front surface of the wafer; determining whether the wafer is acceptable or not according to the above calculation; and fabricating a semiconductor device using the wafer determined to be acceptable according to the above determination . 32_ — A method of fabricating a semiconductor device, comprising: measuring a thickness variation of a wafer under free standing; and assuming that the back surface of the wafer is corrected to a flat surface according to the measurement result, and deriving under the reference of the back surface of the wafer Partial flatness; when the local flatness under the back surface reference of the wafer does not exceed a preset value, 'will be the final flat portion under the wafer back surface reference as the final result' when under the wafer back surface reference When the local flatness exceeds the preset value, the simulation of clamping the crystal B1 on the -crystal US holder is performed; according to the clamping state, the lower part of the 二m2 is flat 71 ^b (day yen刖 Surface appearance meter has been monthly; ... Determining whether the wafer is acceptable or not based on the above calculations; and using wafer fabrication that is acceptable according to the above determination - semi-conducting 33·-a wafer flatness evaluation device, including: · before measuring a wafer, the first surface of the wafer The flatness of the surface; and the measuring portion of the out-of-plane type; the acquisition portion divided into a plurality of parts, a flatness calculation method and a wafer When the evaluation site is fixed to a wafer holder 90347-951208.doc -14- 1282136, the first calculation method is selected, which is obtained when the wafer is fixed on a wafer holder. The front surface of the wafer is distributed to calculate the flatness and degree. When the evaluation portion is not fixed to a wafer holder, the second calculation method is selected, which uses the measurement of the front surface shape of the wafer before and after the wafer. The value is calculated based on the thickness distribution obtained assuming that the wafer is completely sandwiched on an ideal plane. 34. A method of wafer fabrication comprising: ^ ΘΗ jS) 9 Measuring the front surface of the obtained wafer; dividing the front surface of the wafer into a plurality of parts, selecting a flatness calculation method according to the position of the evaluation part, and obtaining a flatness of the wafer surface; and deriving the evaluation part and the wafer The center-to-center distance and the evaluation site are set to be close to the edge of the wafer for flatness evaluation = one of the distances' and the distance derived therefrom is selected to be fixed at the evaluation site to the wafer holder When you are on, The D-differential method is based on the surface profile distribution of the wafer obtained when the wafer is fixed on the wafer, and the calculation is that the evaluation portion is not fixed to a wafer holder. Degree, ^ calculation method, which uses the wafer before and after the statement::::::-... 2: Determine whether the flatness of the obtained wafer surface, when the flatness of the obtained wafer surface is satisfactory , the fixed working process conditions are fixed; and D and time to seek 'will be set up 90347-951208.doc -15- 1282136 Tianshou Zi yen surface of the flat sweeper #~ 虔 do not pay the estimated demand, such as the face into δ and The working process conditions of the company changed. Μ字所 35. A method of fabricating a semiconductor device, comprising: a wafer for performing a dicing process on a semiconductor device, and a lithography process; and applying the wafer; type; = circle: The front surface is divided into several parts, according to the evaluation of the second set: select a flatness calculation method, and obtain the flat surface of the wafer - set in the trash, "" the center distance between the center, and the evaluation site and. It is close to one of the distances between the edges of the edge of the circle for evaluation of flatness, #^丄, has been calculated by the outside; in the evaluation part, the tamping is fixed on a wafer holder. At the time of selection, a calculation method is based on the surface profile of the wafer obtained by fixing the wafer to the wafer, and calculating the flat surface. :: When the estimated part is not fixed on the wafer holder, the second method is: the method uses the measured value of the front surface of the wafer before the root of the wafer - the wafer is completely sandwiched Calculate the flatness of the resulting sound distribution on an ideal plane; determine whether the flatness of the wafer surface obtained by X is maintained at a value that meets the estimated demand or is maintained at a value that does not cause problems; When the flatness is maintained at the above value, the working process conditions of the working process and the lithography process are fixed; and when the flatness of the obtained wafer surface cannot be maintained at the above value, at least the working process conditions of the working process and the lithography process are changed. one. 90347-951208.doc • 16- 1282136 36. A method for fabricating a semiconductor device, comprising: measuring a front surface shape of a wafer; and selecting a front surface of the wafer The number of the ten-tubes 1 is several, according to one of the evaluation methods, and the flat surface of the wafer is obtained: the distance between the two flat parts and the center of the wafer, and the evaluation site :::: τ The edge of the wafer for the flatness evaluation of the outermost edge: one of the distance 'and the distance derived from the selection of the flatness selection; t: the evaluation site is fixed to the - wafer holder In the above, the method of selecting the method is based on the surface profile of the wafer before the wafer is fixed on the wafer, and the flat surface is calculated. The evaluation site is not fixed. - When the wafer holder is on, select = method, which uses the measured value of the front surface of the wafer before and after the wafer is set: when the wafer is completely sandwiched on the ideal plane, the flatness is calculated.判定 Determine whether the wafer is acceptable or not based on the resulting flatness. A wafer fabrication apparatus that is determined to be acceptable based on the above determination is used.守90347-951208.doc 17-