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TWI282128B - Dielectric layer for semiconductor device and method of manufacturing the same - Google Patents

Dielectric layer for semiconductor device and method of manufacturing the same Download PDF

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Publication number
TWI282128B
TWI282128B TW094102747A TW94102747A TWI282128B TW I282128 B TWI282128 B TW I282128B TW 094102747 A TW094102747 A TW 094102747A TW 94102747 A TW94102747 A TW 94102747A TW I282128 B TWI282128 B TW I282128B
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layer
oxide
dielectric
dielectric layer
metal
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TW094102747A
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Chinese (zh)
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TW200537621A (en
Inventor
Jong-Ho Lee
Nae-In Lee
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Samsung Electronics Co Ltd
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Priority claimed from KR1020040005817A external-priority patent/KR100678626B1/en
Priority claimed from US11/027,256 external-priority patent/US7371633B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200537621A publication Critical patent/TW200537621A/en
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Publication of TWI282128B publication Critical patent/TWI282128B/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Description

1282128 九、發明說明： 【發明所屬之技術領域】 本發明大體而言係關於半導體裝置領域，且更特定言 之’本發明係關於一種多層介電結構及利用該多層介電結 構及其製造方法之半導體裝置。 【先前技術】 隨著每一代金屬氧化物半導體（MOS)積體電路（1C)，敦置 尺寸已持續縮小以提供高密度與高效能之裝置。特定言 之，使閘極介電質之厚度盡可能小，因為M〇s(金屬氧化物 半導體）場效電晶體（FET)中之驅動電流隨閘極介電質厚度 減小而增加。因此，為改良裝置效能而提供極薄、可靠且 低缺陷之閘極介電質變得愈來愈重要。 數十年來，例如二氧化矽（Si〇2)之熱氧化物層已用作閘極 Μ電質，因為二氧化矽熱氧化物層與下層矽基板穩定，且 製造製程相對簡單。 然而 —U馬二氧化矽具有低介電常數（k)(例如3.9)，進一 步縮小二氧切閘極介電質變得愈來愈難。舉例而言，若 二氧切間極介電質之厚度小於4G埃，則可發生直接穿 隧。結果’流經薄二氧化矽閘極介電質之閘極至通道洩漏 電流增大，導致不良功率消耗問題。 此等問題使人考慮替代性介 化石夕厚的料，彳生彳目可形成於比二氧 声、…… 或更好之袭置效能。效能可 表達為等效氧化物厚度（EOT)，，。 已做過各種嘗試來改良介 才枓之裝置特性。舉例而 98898.doc 1282128 曰，吴國專利弟6，G2M24號揭示了—種插人砍基板與^ 介電層之間的氮氧化物層。美國專利第6，013,553號揭示了 -種作為閘極介電質之氮氧化錯層或氮氧化給層。此外， PCT國際專利申請公開案第w〇 〇〇/〇1〇〇8號揭示了 si〇2、氮 化石夕及氮氧化物介面層。美國專利第M2G，243號亦揭示了 一種高介電常數锆（或銓）氮氧化矽閘極介電質。 然而，此等嘗試並未成功解決與習知介電材料相關之問 題。舉例而言，高k介電層與矽基板或多晶矽閘電極之間的 氮化矽層或氮氧化物層導致具有高介面狀態密度的電荷陷 阱，進而減低通道遷移率且亦降低裝置效能。此外，氮氧 化矽層或氮氧化物層之形成需要相對大的熱預算。 相應地，仍需要改良的介電層結構及製造方法來藉由（例 如）減少介電層之等效氧化物厚度及改良介面特性而改良 裝置效能。 【發明内容】 • 在一實施例中，半導體裝置包括一矽酸鹽介面層及一覆 於及矽酸鹽介面層上的高k介電層。該高]^介電層包括金屬 合金氧化物。 【實施方式】 本發明提供一種卓越的介電層結構及其製造方法。在以 下描述中，闡述諸多具體細節來提供對本發明之徹底瞭 解然而，普通熟習此項技術者應瞭解，無需此等具體細 即便可實施本發明。在一些情況下，未詳細展示熟知的處 理步驟、裝置結構及技術以避免混淆本發明。 98898.doc 1282128 參看圖1 ’根據本發明之一實施例，一由矽酸鹽材料形成 之矽酸鹽介面層12可安置於一導電層或諸如矽基板之半導 體基板10上。矽酸鹽介面層12之介電常數較佳大於二氧化 矽、氮化矽或氮氧化矽中任一者之介電常數。較佳地，石夕 酸鹽介面層12具有約為5埃至50埃之厚度。更佳地，矽酸鹽 介面層12具有約為5埃至10埃之厚度（2埃至4埃的EOT(等效 氧化物厚度））。矽酸鹽介面層12較佳係由式Mi xSix〇2所表 示之金屬砍酸鹽材料形成。此處，金屬“M”可為給（Hf)、梦 . (Zr)、鈕（Ta)、鈦（Ti)、銃（Sc)、纪（Y)、鑭（La)及铭⑷）。然 而，並不希望此清單無遺漏或限制本發明。可在本發明的 精神及範轉内使用任何適於本發明之其它金屬。 根據本發明之一態樣，金屬矽酸鹽材料（Ml_xSix〇2)展示 了當值Π1-Χ’’大於或等於約0.1時介電常數之最佳值。較佳 地，值”1-χ”不大於約0.5。更佳地，值”i-x”為約0·2至約〇·4。 此外，一高k介電層14安置於矽酸鹽介面層12上，以形成 φ 一多層介電結構15。高k介電層14之介電常數高於Si〇2之介 電常數。高k介電層14之介電常數宜高於矽酸鹽介面層12之 介電常數。高k介電層也宜具有與下層矽酸鹽介面層12之極 好的連貫性（coherency)，且不與諸如閘電極或控制閘極之 上層結構反應。 在本發明中，矽酸鹽介面層12大體上改良了介面特性。 此係因為矽酸鹽介面層12大體上防止了（例如）高k介電層14 與下層半導體基板10之間或高k介電層與用於形成電容器 之下部電極之間的反應。此外，因為該矽酸鹽介面層12之 98898.doc 1282128 形成能量比二氧卜；^ +以上、Λμ @ 虱化矽之形成能量更為負，其在矽 :學：穩定的’因此有助於形成可靠之半導體裝: ==先前技術方法相比減低7介面_度，且 穴體上改良了介面特性。 ，外=此等^技術方法相比，可保持或減低咖（等 乳化物厚度），因為金屬料鹽介面層12具有約為 之相對高的介電常數。 此外’咸信金屬料鹽介面層12在隨後之熱處理期間， :使在赋高溫下也可保持大體上非晶形之狀態。因此， 在金屬矽酸鹽介面l ，漏電流。面層12中產生更少的晶粒邊界，進而減少 ，現回頭看高k介電層14，其包括金屬合金氧化物。高u :層14之i屬合金氧化物以包含至少兩互相擴散之金屬元 素較佳。高k介電層14之金屬合金氧化物可為至少兩金屬氧 匕物之此口物。该等至少兩金屬元素經均句混合更佳，其 :並以在原子級上均勾混合最佳。然而’視應用而定，該 專至^兩金屬7G辛可去奴< 的A、日人 系j禾、，工均勻化合，但經充分混合以充當 在本發明之精神及範疇内的介電材料。 根據本1明之一悲樣，形成高k介電層Μ之至少兩金屬氧 化物可經選擇成在高k介電層14中具有最小淨固定電荷，例 接近零就此而淪，金屬氧化物可包含但不限於氧化銓、 氧化鍅、氧化鈕、氧化銘、氧化鈦、氧化釔、氧化鳃、氧 化航、氧化鑭或氧化鋇。 在另心樣中，金屬氧化物可描述為铪鋁合金氧化物、 98898.doc 1282128 錯紹合金氧化物、叙銘合金氧化物、鈦銘合金氧化物、紀 鋁合金氧化物或铪錯鋁氧化物。然而，並不希望此清單無 遺漏或限制本發明。可在本發明的精神及範疇内使用任何 • ϋ於本發明之其它金屬。^習此項技術者將瞭冑，金屬銘 _ 5金氧化物可表示為金屬銘酸鹽，例如銘酸铪（HfAi〇)。 包έ金屬合金氧化物之高k介電層14之介電常數可大於 矽酸鹽介面層12之介電常數。 鲁此外，金屬合金氧化物可由式AyBi_y〇z，（〇<y<1)來表示。 較佳地，A與上述M相同或來自與M相同之週期族。換言 之，矽酸鹽介面層12之金屬較佳與金屬合金氧化物之金屬 Uk介電層η)相同。舉例而言’若多層介電結構^包括矽 酸給介面層12,則高k介電層14可包括一給銘合金氧化物 層，例如氧化铪與氧化鋁之混合物。同樣，若矽酸鹽介面 層12包括一矽酸錯介面層12，則高k介電層14包括一鍅鋁合 金氧化物層，例如氧化鍅與氧化鋁之混合物。結果，裝置 • 特性可得以改良。舉例而言，介面特性可由於矽酸鹽^面 層12與上層高k介電層14之間的電連貫性而得以改良。 更佳地，A與ΜΛΐν族金屬，且3為\冚族金屬。舉例而 言，Α為鍅或铪，且β為鋁。 根據-態樣’ ”y”可為約〇.5至約0.9,以具有高介電常數 及兩結晶溫度。 根據另一態樣，A與B之組合比在約丨：i與約5 : i之間。 此係因為A之含量愈高，介電常數愈高’但結晶溫度愈低， 其導致洩漏電流增加。理想地，高k介電層丨4具有大體上非 98898.doc •10- 1282128BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to the field of semiconductor devices, and more particularly to the present invention relates to a multilayer dielectric structure and the use of the multilayer dielectric structure and method of fabricating the same Semiconductor device. [Prior Art] With each generation of metal oxide semiconductor (MOS) integrated circuits (1C), the size of Dunhuang has been continuously reduced to provide a device of high density and high efficiency. In particular, the thickness of the gate dielectric is made as small as possible because the drive current in the M〇s (metal oxide semiconductor) field effect transistor (FET) increases as the thickness of the gate dielectric decreases. Therefore, it has become increasingly important to provide extremely thin, reliable, and low defect gate dielectrics for improved device performance. For decades, a thermal oxide layer such as cerium oxide (Si 〇 2) has been used as a gate Μ dielectric because the cerium oxide thermal oxide layer is stable with the underlying germanium substrate and the manufacturing process is relatively simple. However, U-O2 has a low dielectric constant (k) (e.g., 3.9), and it has become increasingly difficult to further reduce the di- thyristor dielectric. For example, direct tunneling can occur if the thickness of the dipolar interpolar dielectric is less than 4 G angstroms. As a result, the leakage current flowing through the gate of the thin ceria gate dielectric to the channel increases, resulting in poor power consumption. These problems have led to the consideration of alternative materials for the use of Shihua thick, which can be formed in a better performance than dioxin, ... or better. Efficacy can be expressed as equivalent oxide thickness (EOT),. Various attempts have been made to improve the device characteristics of the mediator. For example, 98898.doc 1282128 曰, Wu Guo patent brother 6, G2M24 reveals a kind of nitrogen oxide layer between the substrate and the dielectric layer. U.S. Patent No. 6,013,553 discloses a nitrogen oxidized stagger layer or an oxynitride layer as a gate dielectric. In addition, the PCT International Patent Application Publication No. WO 〇/〇1〇〇8 discloses a si〇2, a nitrogen oxide and an oxynitride interface layer. U.S. Patent No. M2G, No. 243 also discloses a high dielectric constant zirconium (or hafnium) oxynitride gate dielectric. However, such attempts have not successfully addressed the problems associated with conventional dielectric materials. For example, a tantalum nitride layer or an oxynitride layer between a high-k dielectric layer and a germanium substrate or a polysilicon gate electrode results in a charge trap having a high interface state density, thereby reducing channel mobility and also reducing device performance. In addition, the formation of a ruthenium oxynitride layer or an oxynitride layer requires a relatively large thermal budget. Accordingly, there is still a need for improved dielectric layer structures and methods of fabrication to improve device performance by, for example, reducing the equivalent oxide thickness of the dielectric layer and improving interface characteristics. SUMMARY OF THE INVENTION In one embodiment, a semiconductor device includes a caprate interface layer and a high-k dielectric layer overlying the caprate interface layer. The high dielectric layer includes a metal alloy oxide. [Embodiment] The present invention provides an excellent dielectric layer structure and a method of manufacturing the same. In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art In some instances, well known process steps, device structures and techniques have not been shown in detail to avoid obscuring the invention. 98898.doc 1282128 Referring to Figure 1 'according to an embodiment of the present invention, a citrate interface layer 12 formed of a phthalate material can be disposed on a conductive layer or semiconductor substrate 10 such as a ruthenium substrate. The dielectric constant of the citrate interface layer 12 is preferably greater than the dielectric constant of any of cerium oxide, cerium nitride or cerium oxynitride. Preferably, the sulphate interface layer 12 has a thickness of from about 5 angstroms to about 50 angstroms. More preferably, the citrate interface layer 12 has a thickness of about 5 angstroms to 10 angstroms (EOT (equivalent oxide thickness) of 2 angstroms to 4 angstroms). The citrate interface layer 12 is preferably formed from a metal chopate material represented by the formula Mi xSix 〇 2 . Here, the metal "M" may be given (Hf), dream (Zr), button (Ta), titanium (Ti), strontium (Sc), y (Y), yttrium (La), and Ming (4). However, it is not intended that the list be exhaustive or to limit the invention. Any other metal suitable for the present invention can be used within the spirit and scope of the present invention. According to one aspect of the invention, the metal silicate material (Ml_xSix 〇 2) exhibits an optimum value of the dielectric constant when the value Π1-Χ'' is greater than or equal to about 0.1. Preferably, the value "1-χ" is no more than about 0.5. More preferably, the value "i-x" is from about 0·2 to about 〇·4. In addition, a high-k dielectric layer 14 is disposed over the citrate interface layer 12 to form φ a multilayer dielectric structure 15. The dielectric constant of the high-k dielectric layer 14 is higher than the dielectric constant of Si 〇 2. The dielectric constant of the high-k dielectric layer 14 is preferably higher than the dielectric constant of the citrate interface layer 12. The high-k dielectric layer also preferably has excellent coherency with the underlying citrate interface layer 12 and does not react with the upper structure such as the gate electrode or the control gate. In the present invention, the citrate interface layer 12 substantially improves the interface characteristics. This is because the citrate interface layer 12 substantially prevents, for example, the reaction between the high-k dielectric layer 14 and the underlying semiconductor substrate 10 or between the high-k dielectric layer and the electrode used to form the lower portion of the capacitor. In addition, because the ylide interface layer 12 of 98898.doc 1282128 forms energy more than dioxin; ^ + above, Λμ @ 虱 矽 矽 矽 矽 矽 矽 更为 更为 更为 , , , 学 学 学 学 学 学 学 学 学 学 学 学 学 学 学 学 学 学 学In the formation of a reliable semiconductor package: == Compared with the prior art method, the interface is reduced by 7 degrees, and the interface characteristics are improved on the hole body. The outer salt = such a technical method can maintain or reduce the coffee (equal emulsion thickness) because the metal salt interface layer 12 has a relatively high dielectric constant. Further, during the subsequent heat treatment, the salt metal layer interface layer 12 is maintained in a substantially amorphous state at a high temperature. Therefore, in the metal citrate interface l, leakage current. Less grain boundaries are created in the top layer 12, which in turn is reduced. The high-k dielectric layer 14, which now includes metal alloy oxides, is now viewed. High u: The alloy oxide of the layer 14 is preferably a metal element comprising at least two interdiffused metals. The metal alloy oxide of the high-k dielectric layer 14 may be at least two metal oxides. The at least two metal elements are preferably mixed by a uniform sentence, and the : is best mixed at the atomic level. However, depending on the application, the A, the Japanese, and the Japanese, which are dedicated to the two metals, can be uniformly mixed, but are sufficiently mixed to serve as the spirit and scope of the present invention. Electrical material. According to one of the sadties of the present invention, at least two metal oxides forming a high-k dielectric layer can be selected to have a minimum net fixed charge in the high-k dielectric layer 14, for example, near zero, and the metal oxide can be Including but not limited to cerium oxide, cerium oxide, oxidizing button, oxidized, titanium oxide, cerium oxide, cerium oxide, oxidizing cerium, cerium oxide or cerium oxide. In another case, the metal oxide can be described as yttrium aluminum oxide, 98898.doc 1282128 slag alloy oxide, yum alloy oxide, titanium alloy oxide, aluminum alloy oxide or erbium aluminum oxide Things. However, this list is not intended to be exhaustive or to limit the invention. Any of the other metals of the present invention may be used within the spirit and scope of the present invention. ^ This technology will be 胄, metal Ming _ 5 gold oxide can be expressed as metal salt, such as 铭 铪 (HfAi 〇). The dielectric constant of the high-k dielectric layer 14 of the tantalum metal alloy oxide may be greater than the dielectric constant of the tantalate interface layer 12. Further, the metal alloy oxide can be represented by the formula AyBi_y〇z, (〇<y<1). Preferably, A is the same as above M or from the same family of cycles as M. In other words, the metal of the citrate interface layer 12 is preferably the same as the metal Uk dielectric layer η) of the metal alloy oxide. For example, if the multilayer dielectric structure comprises a tantalic acid to the interface layer 12, the high-k dielectric layer 14 may comprise a layer of a given alloy oxide, such as a mixture of cerium oxide and aluminum oxide. Similarly, if the citrate interface layer 12 includes a bismuth silicate interface layer 12, the high-k dielectric layer 14 includes a layer of bismuth aluminum alloy oxide, such as a mixture of cerium oxide and aluminum oxide. As a result, the device • characteristics can be improved. For example, the interface characteristics can be improved by the electrical continuity between the bismuth oxide layer 12 and the upper high-k dielectric layer 14. More preferably, A is a metal of the ΜΛΐν group, and 3 is a metal of the 冚 group. For example, Α is 鍅 or 铪, and β is aluminum. It may have a high dielectric constant and a two crystallization temperature depending on the -state ' y '. According to another aspect, the combination ratio of A to B is between about 丨:i and about 5:i. This is because the higher the content of A, the higher the dielectric constant' but the lower the crystallization temperature, which leads to an increase in leakage current. Ideally, the high-k dielectric layer 丨4 has substantially non-98898.doc •10- 1282128

晶形結晶結構，以減少流經其的洩漏電流。更佳地，A與B 之組合比為約2 : 1，因為所得的高k介電層14之淨固定電芥 可接近零。在此狀況下，A較佳為铪或锆；且3較佳為鋁。 高k介電層14可具有約2埃至60埃之厚度。此處，2埃為一原 子層之基本厚度，且60埃表示在隨後之退火製程期間防止 爆裂現象之厚度上限。如此項技術中已知，在形成期間陷 牌於介電層中的羥基基團可在隨後退火時自介電層爆裂， 瞻從而毀壞介電層，例如在介電層中留下洞。若發生此種爆 裂現象，隨後的處理步驟（諸如閘極多沉積）可受到顯著抑 制。 圖2說明一種製造用於半導體裝置中的上述多層介電結 構15之方法。為清楚與簡明起見，若製造步驟係為習知或 熟知，則省略其細節。 如上所述，矽酸鹽介面層12可形成於導電層或半導體基 板10上。金屬矽酸鹽介面層12較佳係由參看圖丨所述之材料 φ 形成。更佳地，金屬矽酸鹽介面層12可使用ALD(原子層沉 積）技術形成。因此，與需要高熱預算之先前技術方法對 比’低熱預算製程在本發明之情況下係為可能。此外，藉 由使用ALD(原子層沉積）技術，可使用更廣範圍之前軀物， 且可形成一具有受到緊密控制的厚度之膜，傳統化學氣相 沉積（CVD)將不可能形成該膜。 詳言之，如此項技術中已知，可藉由交替且反覆地對金 屬來源、石夕來源及氧來源執行脈動及淨化步驟來執行用於 形成金屬矽酸鹽介面層12之ALD(原子層沉積）技術。在矽酸 98898.doc • 11 - 1282128 鍅介面層12狀況下，ZrCl4可用作金屬來源。類似地，在矽 酸铪介面層之狀況下，HfCl4可用作金屬來源。同樣，矽來 源可包括SiH4或SiCl4H2。氧來源可包括H20、臭氧、氧基、 醇類，諸如IPA、D20或H2〇2。同樣，可在本發明的精神及 範疇内使用其它適用於本發明之前軀物。在表1中說明了此 等例示性前軀物。 表1 铪來源 錐來源 矽來源 鹵化物 HfCl4 ZrCl4 SiCl4 烷氧化物 Hf(OtC4H9)4Hf(OC2H5)4 Zr(OtC4H9)4 Si(OC4H9)4Si- (OCH3)4Si(OC2H5)4 醯胺 Hf(N(C2H5)2)4H- Zr(N(C2H5)2)4_ Si(N(C2H5)2)4· f(N(CH3)2)4， Zr(N9CH3)2)4， Si(N(CH3)2)4， Hf(N(CH3C2H5))4 Zr(N(CH3C2H5))4 Si(N(CH3)2)3H， HfCl2(hmds)2 烷氧胺 ’ (alkoxylamine) Hf(dmae)4 Zr(dmae)4 Si(dmae)4 ETC SiH4, SiCl4H2, Si2Cl6 *dmae(二甲胺)Crystalline crystal structure to reduce leakage current flowing through it. More preferably, the combination ratio of A to B is about 2:1 because the resulting net fixed electric mustard of the high-k dielectric layer 14 is close to zero. In this case, A is preferably hafnium or zirconium; and 3 is preferably aluminum. The high-k dielectric layer 14 can have a thickness of between about 2 angstroms and 60 angstroms. Here, 2 angstroms is the basic thickness of an atomic layer, and 60 angstroms represents the upper thickness limit for preventing bursting during the subsequent annealing process. As is known in the art, the hydroxyl groups trapped in the dielectric layer during formation can burst from the dielectric layer upon subsequent annealing, thereby destroying the dielectric layer, such as leaving holes in the dielectric layer. If such a burst occurs, subsequent processing steps, such as gate deposition, can be significantly inhibited. Figure 2 illustrates a method of fabricating the above described multilayer dielectric structure 15 for use in a semiconductor device. For the sake of clarity and conciseness, if the manufacturing steps are conventional or well known, the details are omitted. As described above, the citrate interface layer 12 can be formed on the conductive layer or the semiconductor substrate 10. The metal citrate interface layer 12 is preferably formed of the material φ as described with reference to Figure 。. More preferably, the metal citrate interface layer 12 can be formed using ALD (Atomic Layer Deposition) techniques. Therefore, in contrast to prior art methods that require a high thermal budget, a low thermal budget process is possible in the context of the present invention. In addition, by using ALD (Atomic Layer Deposition) technology, a wider range of precursors can be used, and a film having a tightly controlled thickness can be formed, which is impossible to form by conventional chemical vapor deposition (CVD). In particular, it is known in the art to perform ALD (atomic layer) for forming the metal citrate interface layer 12 by alternately and repeatedly performing a pulsation and purification step on the metal source, the source of the stone, and the source of oxygen. Deposition) technology. In the case of tantalum 98898.doc • 11 - 1282128 鍅 interface layer 12, ZrCl4 can be used as a metal source. Similarly, HfCl4 can be used as a metal source in the case of a bismuth citrate interface layer. Also, the germanium source may include SiH4 or SiCl4H2. Sources of oxygen may include H20, ozone, oxy, alcohols such as IPA, D20 or H2〇2. Likewise, other precursors suitable for use in the present invention can be used within the spirit and scope of the present invention. These exemplary precursors are illustrated in Table 1. Table 1 铪 Source cone source 矽 source halide HfCl4 ZrCl4 SiCl4 alkoxide Hf(OtC4H9)4Hf(OC2H5)4 Zr(OtC4H9)4 Si(OC4H9)4Si-(OCH3)4Si(OC2H5)4 decylamine Hf(N( C2H5)2)4H-Zr(N(C2H5)2)4_Si(N(C2H5)2)4·f(N(CH3)2)4, Zr(N9CH3)2)4, Si(N(CH3)2 4, Hf(N(CH3C2H5))4 Zr(N(CH3C2H5))4 Si(N(CH3)2)3H, HfCl2(hmds)2 alkoxylamine Hf(dmae)4 Zr(dmae) 4 Si(dmae)4 ETC SiH4, SiCl4H2, Si2Cl6 *dmae (dimethylamine)

或者，若金屬有機化學氣相沉積（MOCVD)技術或反應性 濺鍍技術在厚度或組合物方面提供與ALD(原子層沉積）技 術類似之控制水平，則可使用MOCVD(金屬有機化學氣相 沉積）技術或反應性濺鍍技術來形成矽酸鹽介面層12。可使 用諸如Hf(0-Si-R3)4 或 Zr(0-Si-R3)4,（R=C2H5)之前軀物來執 行MOCVD(金屬有機化學氣相沉積）技術。同樣，可使用諸 如第三丁氧化铪之铪來源、諸如第三丁氧化锆之錘來源， 及諸如四乙氧基原石夕烧（tetraethoxyorthosilane)或原石夕酸四 乙酯（TEOS)之矽來源。 98898.doc -12- 1282128 士接者’如上文參看圖!所述’形成包括金屬合金氧化物之 高k介電層14，以覆於矽酸鹽介面層12上。 更詳細地，根據一態樣，為形成高k介電層14，藉由 ALD(原子層沉積)技術形成一具有一第一金屬元素之第一 層18。然冑，亦藉由ALD(原子層沉積）技術形成一覆於該第 -層18上、具有一第二金屬元素之第二層2〇。第一及第二 金屬元素可為一可形成諸如氧化铪、氧化锆、氧化鈕、氧 化鋁、氧化鈦、氧化釔、氧化锶、氧化钪、氧化鑭或氧化 鋇之氧化物的金屬。 另一方面，若矽酸鹽介面層12係由矽酸鍅形成，則上層 兩k介電層14宜藉由交替地堆疊Zr〇2層與Ai2〇3層，加上以 下將進一步描述之隨後熱處理來形成。在此狀況下，因為 矽酸鹽介面層12之金屬與金屬合金氧化物層（高k介電層14) 中所含的金屬之一相同，介面特性可由於矽酸鹽介面層12 與上層高k介電層14之間的電連貫性而得以改良（如上所 述）。類似地，若矽酸鹽介面層12係由矽酸铪形成，則高k 介電層14宜藉由交替地堆疊Hf〇2層與八丨2〇3層，及以下將進 一步描述之隨後熱處理來形成。 以第一層18具有一第一預定電荷，且第二層2〇具有一與 第一層18之預定電荷相反的第二預定電荷更佳。其中，並 以第一預定電荷為正固定電荷，且第二預定電荷為負固定 電荷最佳。按此思路，第一層18可由氧化銓、氧化鍅、氧 化鈕、氧化鋁、氧化鈦、氧化釔、氧化鳃、氧化銳、氧化 鑭或氧化鋇形成，且第二層2 〇可由氧化銘形成。 98898.doc -13- 1282128Alternatively, if metal organic chemical vapor deposition (MOCVD) techniques or reactive sputtering techniques provide similar levels of control in terms of thickness or composition to ALD (atomic layer deposition) techniques, MOCVD (metal organic chemical vapor deposition) can be used. The technique or reactive sputtering technique is used to form the citrate interface layer 12. The MOCVD (Metal Organic Chemical Vapor Deposition) technique can be performed using a precursor such as Hf(0-Si-R3)4 or Zr(0-Si-R3)4, (R=C2H5). Also, a source of ruthenium such as tributyl ruthenium oxide, a source of a hammer such as a third zirconia, and a source of ruthenium such as tetraethoxyorthosilane or tetraethylorthosulfate (TEOS) may be used. 98898.doc -12- 1282128 stalker' as described above with reference to the figure! The formation of a high-k dielectric layer 14 comprising a metal alloy oxide overlying the citrate interface layer 12. In more detail, according to an aspect, to form the high-k dielectric layer 14, a first layer 18 having a first metal element is formed by ALD (Atomic Layer Deposition) technique. Then, a second layer 2 具有 having a second metal element overlying the first layer 18 is also formed by ALD (Atomic Layer Deposition) technique. The first and second metal elements may be a metal which forms an oxide such as cerium oxide, zirconium oxide, oxidic oxide, aluminum oxide, titanium oxide, cerium oxide, cerium oxide, cerium oxide, cerium oxide or cerium oxide. On the other hand, if the tantalate interface layer 12 is formed of tantalum ruthenate, the upper two-k dielectric layer 14 is preferably formed by alternately stacking the Zr〇2 layer and the Ai2〇3 layer, as will be further described below. Heat treatment to form. In this case, since the metal of the citrate interface layer 12 is identical to one of the metals contained in the metal alloy oxide layer (high-k dielectric layer 14), the interface characteristics may be higher due to the citrate interface layer 12 and the upper layer. The electrical continuity between the k dielectric layers 14 is improved (as described above). Similarly, if the citrate interface layer 12 is formed of bismuth ruthenate, the high-k dielectric layer 14 is preferably stacked by alternately stacking layers of Hf 〇 2 and 丨 2 〇 3, and subsequent heat treatment as described further below. To form. Preferably, the first layer 18 has a first predetermined charge and the second layer 2 has a second predetermined charge opposite the predetermined charge of the first layer 18. Wherein, the first predetermined charge is a positive fixed charge, and the second predetermined charge is a negative fixed charge. According to this idea, the first layer 18 may be formed of ruthenium oxide, ruthenium oxide, oxidized knob, aluminum oxide, titanium oxide, ruthenium oxide, ruthenium oxide, ruthenium oxide, ruthenium oxide or ruthenium oxide, and the second layer 2 may be formed by oxidation. . 98898.doc -13- 1282128

因此，根據本發明之—態樣，使高k介電層14之淨固定電 荷最小化係為可能。就此㈣，在先前技術中，固定電荷 存在@題，其導致會減低通道遷移率之庫侖散射。然而， 在本U <樣中，先前技術之固定電荷問題可藉由以 =如上述乳化給或氧化錯之材料形成之第-層18中之正固 定，荷，補冑由諸如氧化銘之材料形成之第二層2〇中之負 口疋電何來克服，尤其是當金屬氧化物係在原子級上均勻 混合或在隨後的製造製程期間互相擴散時。 第一層20之厚度可約為第一層18之厚度的一半。若第一 ㈣係由諸如氧化铪或氧化錯之材料形《，且第二層肩' 2化_成，則尤其如此，因為咸信氧化財之固定電 荷量大約比氧化铪或氧化錯之固定電荷量多兩倍。舉例而 言，第一層18可形成大約10埃之厚度，且第二層2〇可形成 大約5埃之厚度。 根據本發明之一實施例，所得之結構隨後受到退火或熱 處理，以形成圖1所示之多層介電結構丨5。舉例而言，退火 溫度可大於約900。(：，以使圖2所示之第一層18與第二層2〇 結合或混合而形成包含至少兩互相擴散之金屬元素之高k 介電層14。較佳地，退火溫度約為95〇r。更佳地，退火溫 度足夠高，以使至少兩金屬元素在原子級上在高k介電層14 中句句混合而形成一金屬合金氧化物層。 二看圖3，根據另一態樣，在為進行熱處理或退火以形成 圖1所示之多層介電結構15之前，在所得結構上形成一或多 個額外的第-及第二層18、20。另一導電層24可形成於高k 98898.doc -14- 1282128 =電層14上以形成各種半導體裝置。同樣，在退火之前， 最^可包括氧化鋁以改良高k介電層14與導電層24之 間的介面特性。 在另恶樣中，高k介電層14可由M〇CVD(金屬有機化學 軋相’儿積)技術來形成。較佳地，同時供應兩金屬元素之來 :以形成包括金屬合金氧化物之高k介電層14。或者，金屬 —物層了使用反應性錢鍍技術來形成。反應性賤鍍Therefore, it is possible to minimize the net fixed charge of the high-k dielectric layer 14 in accordance with the present invention. In this regard, in the prior art, the fixed charge has a @ problem, which leads to Coulomb scattering which reduces the channel mobility. However, in the present example, the fixed charge problem of the prior art can be fixed by the positive layer in the first layer 18 formed by the material emulsified or oxidized as described above, such as oxidized The negative polarity of the second layer 2 formed by the material is overcome, especially when the metal oxides are uniformly mixed at the atomic level or mutually diffused during subsequent manufacturing processes. The thickness of the first layer 20 can be about one-half the thickness of the first layer 18. This is especially true if the first (four) is made of a material such as yttria or oxidized, and the second layer is singular, because the fixed charge of the salt oxidized is about fixed to that of yttrium oxide or oxidized. The amount of charge is twice as much. By way of example, the first layer 18 can be formed to a thickness of about 10 angstroms and the second layer 2 can be formed to a thickness of about 5 angstroms. In accordance with an embodiment of the present invention, the resulting structure is subsequently annealed or heat treated to form the multilayer dielectric structure 丨5 of FIG. For example, the annealing temperature can be greater than about 900. (:, to form a high-k dielectric layer 14 comprising at least two interdiffused metal elements by combining or mixing the first layer 18 and the second layer 2〇 shown in FIG. 2. Preferably, the annealing temperature is about 95. Preferably, the annealing temperature is sufficiently high that at least two metal elements are mixed at the atomic level in the high-k dielectric layer 14 to form a metal alloy oxide layer. See Figure 3, according to another In one aspect, one or more additional first and second layers 18, 20 are formed on the resulting structure prior to heat treatment or annealing to form the multilayer dielectric structure 15 of Figure 1. Another conductive layer 24 can be Formed on high k 98898.doc -14 - 1282128 = electrical layer 14 to form various semiconductor devices. Also, prior to annealing, aluminum oxide may be included to improve the interface between high-k dielectric layer 14 and conductive layer 24. In other cases, the high-k dielectric layer 14 can be formed by M〇CVD (metal organic chemical rolling phase) technology. Preferably, two metal elements are simultaneously supplied: to form a metal alloy including oxidation High-k dielectric layer 14. Or, metal-layer layer using reactive money plating technology Formation. Reactive iridium plating

技術係藉由在金屬沉積期間注入氧氣至處理腔室中來執 行0 以上描述的本發明可用於形成如下所述2M〇s(金屬氧 化物半‘體）電晶體。同樣，本發明亦可應用於半導體裝置 之任何介電質，諸如非揮發性記憶體之閘極間介電層或儲 存電谷器之介電層，其全部在本發明精神及範疇内。 洋έ之，參看圖4，一MOS(金屬氧化物半導體）電晶體41 包括一半導體基板100、一形成於基板100上之矽酸鹽介面 φ 層120a，及一形成於矽酸鹽介面層120a之上用以形成閘極 w電層120之咼k介電層120b。石夕酸鹽介面層120a及高k介電 層120b均係由關於圖1所述之介電材料形成。此外，m〇s(金 屬氧化物半導體）電晶體41可進一步包含一閘電極13 〇，該 閘電極包括（例如）一多晶矽層13〇a、一矽化物層i3〇b及一形 成於鄰接閘電極130處的源極/汲極區域。閘電極13〇可由金 屬形成。視需要，可沿著閘電極130之相對側形成一隔片 】5〇，以完成具有一通道區域107之半導體裝置41。 參看圖5，根據另一實施例，一非揮發性記憶體裝置5丄 98898.doc -15- 1282128 包括一半導體基板200、一具有一覆於基板200上之閘極絕 緣層209之浮動閘極21〇、一形成於浮動閘極21〇之上的矽酸 鹽介面層220a ’及一形成於石夕酸鹽介面層220a之上用以形 成閘極間介電層220的高k介電層220b。矽酸鹽介面層220a 及尚k介電層220b均由關於圖1所述之介電材料形成。同 樣’一控制閘極230覆於閘極間介電層220上。如此項技術 中已知，控制閘極230可包括一多晶矽層230a及一矽化物層 230b。可另外形成諸如隔片250及源極/汲極區域2〇6之其它 習知結構以完成具有通道區域207之非揮發性記憶體裝置 5 1。在該實施例中，關於圖1所述之多層介電結構僅可應用 於閘極間介電層220或閘極絕緣層209。或者，該多層介電 結構可應用於閘極間介電層220及閘極絕緣層209。 參看圖6，根據另一實施例，一電容器61包括一下端電極 31〇、一形成於下端電極310之上的矽酸鹽介面層320a，及 一形成於石夕酸鹽介面層320a之上以形成一電容器介電層 320的高k介電層320b。矽酸鹽介面層320a及高k介電層320b 係由關於圖1所述之介電材料形成。電容器6丨另外包含一覆 於電容器介電層320上之上端電極330。電容器61電連接至 一半導體基板300。 應注意，在本發明之精神及範疇内，圖1至圖6所示之基 板10可為半導體或導體’諸如換雜的多晶石夕。同樣，基板 10亦可為單結晶矽基板或絕緣物上矽（SC)I)基板。 圖7為說明對使用參看圖4所述之實施例所形成之結構的 結構分析圖，其中矽酸鹽介面層12〇a可為HfSi02，且高k介 98898.doc -16- 1282128 參看圖7，符號〇指示矽濃度，符號@指示铪濃度，且符 號③指示鋁濃度。較佳地，铪及鋁二者在整個高k介電層 120b中均具有均勻之濃度。矽酸鹽介面層120a可包含自高k 介電層120b擴散之鋁原子，且高k介電層120b可包含自矽酸 鹽介面層120a擴散之石夕原子。 此外，在矽酸鹽介面層120a中，鋁濃度自矽酸鹽介面層 120a之上表面朝基板1〇〇減小，且矽濃度自矽酸鹽介面層 § 120a之上表面朝高k介電層120b之上表面減小。 或者，由式人#1^〇2表示的高k介電層120b中的y值可自矽 酸鹽介面層120a與高k介電層120b之底表面之間的介面朝 高k介電層120b之上表面減小。A之濃度沿著高k介電層120b 之厚度具有一梯度。同樣，在高k介電層120b内，B之濃度 可與A之濃度成反比。換言之，y值可端視閘極介電層ι2〇 之高度而變化。若A與矽酸鹽介面層i2〇a之金屬μ相同，且 φ Β包括與上層電極結構（諸如閘電極、控制閘極或電容器上 端電極）在化學上穩定的材料，則尤其如此。因此，用本發 明之此等實施例可形成可靠之半導體裝置結構。 根據本發明之另一態樣，區段Q中㊁與⑦之濃度可端視閘 極介電層12〇之高度由一些函數來步進或改變。 總之，與諸如併有氮化矽或氮氧化物介面層或無介面層 的矽酸鹽表體層（bulk layer)之先前技術介電層結構相比， 用本發明之實施例可改良介面特性且可保持或減少Ε〇τ(等 效氧化物厚度）。換言之，藉由結合矽酸鹽介面層12與高k 98898.doc 1282128 ;丨電層14，可達成具有改良之介面特性之低EOT(等效氧化 物厚度），該矽酸鹽介面層12之介電常數較佳大於氧化矽、 氮化矽或氮氧化物中任一者之介電常數。 在以本發明之較佳實施例描述及說明其原則之後，應明 白可不脫離此等原則在配置與細節上修改本發明。吾等 主張在下列申請專利範圍之精神及範疇内的所有修改及變 化。 【圖式簡單說明】 圖1為說明根據本發明之一實施例之半導體裝置的橫截 面視圖。 圖2為根據本發明之另一實施例之半導體裝置的橫截面 視圖。 圖3為根據本發明之另一實施例之半導體裝置的橫載面 視圖。 圖4說明用於M0S(金屬氧化物半導體）電晶體中的本發 明之一實施例。 圖5說明用於非揮發性記憶體裝置中的本發明之一實施 例。 圖6說明用於電容器中的本發明之一實施例。 圖7為說明對使用參看圖4所述之實施例而形成之結構的 結構分析。 【主要元件符號說明】 10 半導體基板 12 石夕酸鹽介面層 98898.doc 18 1282128 14 高k介電層 15 多層介電結構 18 第一層 20 第二層 22 最上層 24 導電層 41 MOS(金屬氧化物半導體）電晶體 51 非揮發性記憶體裝置The technique is performed by injecting oxygen into the processing chamber during metal deposition. The invention described above can be used to form 2M 〇s (metal oxide semi-body) transistors as described below. Similarly, the present invention is also applicable to any dielectric of a semiconductor device, such as a dielectric layer of a non-volatile memory or a dielectric layer for storing an electric grid, all of which are within the spirit and scope of the present invention. Referring to FIG. 4, a MOS (metal oxide semiconductor) transistor 41 includes a semiconductor substrate 100, a caprate interface φ layer 120a formed on the substrate 100, and a layer formed on the caprate interface layer 120a. The 咼k dielectric layer 120b is formed over the gate electrode layer 120. Both the silicate layer 120a and the high-k dielectric layer 120b are formed of the dielectric material described with respect to FIG. In addition, the m〇s (metal oxide semiconductor) transistor 41 may further include a gate electrode 13 包括, the gate electrode including, for example, a polysilicon layer 13〇a, a germanide layer i3〇b, and a gate formed on the adjacent gate The source/drain region at electrode 130. The gate electrode 13A may be formed of a metal. If desired, a spacer can be formed along the opposite side of the gate electrode 130 to complete the semiconductor device 41 having a channel region 107. Referring to FIG. 5, according to another embodiment, a non-volatile memory device 5丄98898.doc-15-1282128 includes a semiconductor substrate 200 and a floating gate having a gate insulating layer 209 overlying the substrate 200. 21〇, a tantalate interface layer 220a′ formed on the floating gate 21〇 and a high-k dielectric layer formed on the interlayer interface 220a to form the inter-gate dielectric layer 220 220b. Both the citrate interface layer 220a and the s-k dielectric layer 220b are formed of the dielectric material described with respect to FIG. Similarly, a control gate 230 is overlaid on the inter-gate dielectric layer 220. As is known in the art, control gate 230 can include a polysilicon layer 230a and a vapor layer 230b. Other conventional structures such as the spacer 250 and the source/drain regions 2〇6 may be additionally formed to complete the non-volatile memory device 51 having the channel region 207. In this embodiment, the multilayer dielectric structure described with respect to Figure 1 can only be applied to the inter-gate dielectric layer 220 or the gate insulating layer 209. Alternatively, the multilayer dielectric structure can be applied to the inter-gate dielectric layer 220 and the gate insulating layer 209. Referring to FIG. 6, according to another embodiment, a capacitor 61 includes a lower electrode 31A, a caprate interface layer 320a formed on the lower electrode 310, and a capping layer 320a formed on the layer A high-k dielectric layer 320b of a capacitor dielectric layer 320 is formed. The citrate interface layer 320a and the high-k dielectric layer 320b are formed from the dielectric material described with respect to FIG. The capacitor 6A further includes an upper electrode 330 overlying the capacitor dielectric layer 320. The capacitor 61 is electrically connected to a semiconductor substrate 300. It should be noted that within the spirit and scope of the present invention, the substrate 10 shown in Figures 1 through 6 can be a semiconductor or conductor such as a modified polycrystalline spine. Similarly, the substrate 10 may be a single crystal germanium substrate or an insulator upper (SC) I) substrate. Figure 7 is a structural analysis diagram illustrating the structure formed using the embodiment described with reference to Figure 4, wherein the citrate interface layer 12a can be HfSiO 2 and the high-k 98898.doc -16 - 1282128 is shown in Figure 7. The symbol 〇 indicates the 矽 concentration, the symbol @ indicates the 铪 concentration, and the symbol 3 indicates the aluminum concentration. Preferably, both tantalum and aluminum have a uniform concentration throughout the high k dielectric layer 120b. The citrate interface layer 120a may include aluminum atoms diffused from the high-k dielectric layer 120b, and the high-k dielectric layer 120b may include a schist atom diffused from the citrate interface layer 120a. In addition, in the citrate interface layer 120a, the aluminum concentration decreases from the upper surface of the citrate interface layer 120a toward the substrate 1 ,, and the erbium concentration is from the upper surface of the citrate interface layer § 120a toward the high-k dielectric The upper surface of layer 120b is reduced. Alternatively, the y value in the high-k dielectric layer 120b represented by the formula #1^〇2 may be from the interface between the tantalate interface layer 120a and the bottom surface of the high-k dielectric layer 120b toward the high-k dielectric layer. The surface above 120b is reduced. The concentration of A has a gradient along the thickness of the high-k dielectric layer 120b. Similarly, in the high-k dielectric layer 120b, the concentration of B can be inversely proportional to the concentration of A. In other words, the value of y can vary depending on the height of the gate dielectric layer ι2〇. This is especially true if A is the same as the metal μ of the citrate interface layer i2〇a, and φ Β includes a material that is chemically stable with the upper electrode structure such as the gate electrode, the control gate or the upper electrode of the capacitor. Thus, reliable semiconductor device structures can be formed using such embodiments of the present invention. In accordance with another aspect of the invention, the concentration of two and seven in segment Q can be stepped or varied by some function depending on the height of the gate dielectric layer 12A. In summary, embodiments of the present invention may improve interface characteristics as compared to prior art dielectric layer structures such as a tantalum nitride or oxynitride interface layer or a non-interface layer of a bismuth carbonate layer. Ε〇τ (equivalent oxide thickness) can be maintained or reduced. In other words, by combining the citrate interface layer 12 with the high-k 98898.doc 1282128; the ruthenium layer 14, a low EOT (equivalent oxide thickness) with improved interface properties can be achieved, the citrate interface layer 12 The dielectric constant is preferably greater than the dielectric constant of any of cerium oxide, cerium nitride or oxynitride. Having described and described the principles of the preferred embodiments of the invention, it should be understood that We have all the modifications and variations in the spirit and scope of the following patent applications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. 2 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. Figure 3 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. Figure 4 illustrates an embodiment of the invention for use in a MOS (metal oxide semiconductor) transistor. Figure 5 illustrates an embodiment of the invention for use in a non-volatile memory device. Figure 6 illustrates an embodiment of the invention for use in a capacitor. Figure 7 is a structural analysis illustrating the structure formed using the embodiment described with reference to Figure 4. [Main component symbol description] 10 Semiconductor substrate 12 Asperate interface layer 98988.doc 18 1282128 14 High-k dielectric layer 15 Multi-layer dielectric structure 18 First layer 20 Second layer 22 Uppermost layer 24 Conductive layer 41 MOS (metal Oxide semiconductor) transistor 51 non-volatile memory device

61 電容器 100 半導體基板 107 通道區域 120 閘極介電層 120a 石夕酸鹽介面層 120b 高k介電層 130 閘電極 130a 多晶矽層 13 0b 石夕化物層 150 隔片 200 半導體基板 206 源極/汲極區 207 通道區域 209 閘極絕緣層 210 浮動閘極 220 閘極間介電層 98898.doc -19- 1282128 220a 石夕酸鹽介面層 220b 高k介電層 230 控制閘極 230a 多晶矽層 230b 矽化物層 250 隔片 300 半導體基板 310 下端電極 320 電容器介電層 320a 石夕酸鹽介面層 320b 高k介電層 330 上端電極61 Capacitor 100 Semiconductor Substrate 107 Channel Region 120 Gate Dielectric Layer 120a Oleate Interface Layer 120b High-k Dielectric Layer 130 Gate Electrode 130a Polysilicon Layer 13 0b Si Xi Compound Layer 150 Septum 200 Semiconductor Substrate 206 Source/汲Polar region 207 channel region 209 gate insulating layer 210 floating gate 220 inter-gate dielectric layer 98898.doc -19- 1282128 220a lithium salt interface layer 220b high-k dielectric layer 230 control gate 230a polysilicon layer 230b Substrate 250 spacer 300 semiconductor substrate 310 lower electrode 320 capacitor dielectric layer 320a silicate interface layer 320b high-k dielectric layer 330 upper electrode

98898.doc -20-98898.doc -20-

Claims (1)

秦（月V日修Qin (month V repair 利申請案 • f文申#專利關替換本(96年元月） 十、申請專利範圍： 種用於一半導體裝置之多層結構，其包括： 一石夕酸鹽介面層；及 覆於該石夕酸鹽介面層上之高k介電層，該高k介電層 包括金屬合金氧化物。 2·如明求項1之多層結構，其中該等金屬合金氧化物包含至 少兩互相擴散之金屬元素。 3.如請求項1之多層結才冓，其中該等至少兩金屬a素係在一 原子級上均勻混合。 4·如μ求項i之多層結構，其中該等金屬合金氧化物包括至 少兩不同金屬氧化物之一混合物。 5·如明求項4之多層結構，其中該等金屬氧化物係經選擇以 具有該高k介電層之一最小淨固定電荷。 6·如明求項4之多層結構，其中該等金屬氧化物包括氧化 铪、氧化鍅、氧化鈕、氧化鋁、氧化鈦、氧化釔、氧化 銷、氧化銃、氧化鑭或氧化鋇。 7·如明求項1之多層結構，其中該金屬合金氧化物包括給銘 :金氧化物、锆鋁合金氧化物、鈕鋁合金氧化物、鈦鋁 合金氧化物、釔鋁合金氧化物或铪鍅鋁氧化物。 8·如睛求項1之多層結構，其中該高k介電層具有一大於該 矽酸鹽介面層之介電常數的介電常數。 9·如晴求項1之多層結構，其中該矽酸鹽介面層具有一大於 氮化矽、氧化矽或氮氧化矽中任一者之介電常數的介電 98898-960102.doc 1282128 10 ·如§青求項1之客庶 只Κ夕層結構，其中該矽酸鹽介面層具有一約為 5埃至50埃之厚度。 U·如明求項1〇之多層結構，其中該矽酸鹽介面層具有一約 為5埃至1〇埃之厚度。 12·如明求項1之多層結構，其中該矽酸鹽介面層係由一由一 分子式MhxSixO〗表示之金屬矽酸鹽材料所形成。 13·如請求項12之多層結構，其中該金屬，，M&quot;係選自於由铪 _ (Hf)、錘（zr)、钽（Ta)、鈦（Ti)、銃（Sc)、釔（Y)、鑭（La) 及鋁（A1)組成之群。 ‘ 14.如請求項12之多層結構，其中1-x大於或等於約n。 / 15.如請求項12之多層結構，其中1-x不大於約〇.5。 r 16·如請求項12之多層結構，其中1-χ為約〇·2至約〇,4。 17·如請求項13之多層結構，其中該金屬合金氧化物係由一 分子式AyBbyOz來表示，且其中〇&lt;y&lt;l。 18·如請求項17之多層結構，其中八與]\4相同或來自與μ相同 • 之週期表群族。 19.如請求項17之多層結構，其中a及μ為一 ιν族金屬且β為 一 ΧΠΙ族金屬。 20·如請求項17之多層結構，其中Α為锆或铪；且β為鋁。 21·如請求項17之多層結構，其中y為約〇·5至約〇 9。 22.如請求項17之多層結構’其中Α與Β之一組合比係在約i ·· 1與約5 : 1之間。 23·如請求項22之多層結構，其中A與B之該組合比約為2: i。 24·如請求項23之多層結構，其中A為鈐或锆；且8為鋁。 98898-960102.doc -2 - 1282128 25.如請求項24之多層結構，其中該矽酸鹽介面層包含自該 咼k介電層擴散之銘原子。 26·如請求項17之多層結構，其中y之值自該矽酸鹽介面層與 。亥局k;丨電層之一底表面之間的一介面朝該高&amp;介電層的 一上表面減小’且其中A之濃度沿著該高k介電層之該厚 度具有一梯度。 27·如請求項17之多層結構，其中在該高k介電層内，b之濃 &gt; 度與A之濃度成反比。 28.如請求項17之多層結構，其中該高k介電層包含自該矽酸 鹽介面層擴散之矽原子。 29·如請求項1之多層結構，其中該高k介電層具有一大體上 非晶形結晶結構。 30. 如請求項1之多層結構，其中該高k介電層係形成一約為2 埃至60埃之厚度。 31. —種形成一用於一半導體裝置之多層結構之方法，其包 .括 形成一矽酸鹽介面層；及 形成一覆於該矽酸鹽介面層上之高k介電層，該高k介 電層包括金屬合金氧化物。 32·如清求項31之方法’其中該形成該南k介電層之步驟包 括： 由ALD(原子層沉積）形成一具有一第一金屬元素之第 一層； 由ALD(原子層沉積）形成一覆於該第一層上且且有一 98898-960102.doc -3- 1282128 第二金屬元素之第二層；及 在一允許該第一今麗-主 、疋素，、δ亥弟一金屬元素互相擴散 之溫度下，退火所得結構。 、 33. 如請求項32之方法，其中該退火溫度大於約9〇代。 34. 如請求項32之方法，复 甲遠弟一層具有一第一預定電 且该第二層具有~ ^ ^ ta ，、忒弟一層之預定電荷相反之第二 定電荷。 碑 35. :請求項34之方法’其中該第一預定電荷為一正固定電 何且该第二預定電荷為一負固定電荷。 36·如睛求項32之方法，在該退火步驟之前，其進—步包括 形成一或多個額外之第一及第二層之步驟。 37·如請求項36之方法，其中最上層包括氧化鋁。 38·如請求項32之方法，其中該第二層約為該第—層 的一半。 又 39.如請求項38之方法，其中將該第_層形成為一約1〇埃之 厚度且將該第二層形成為一約5埃之厚度。 4〇. ^請求項32之方法，其中該第一層係由又氧化給、氧化錯、 氧化ί一氧化鋁、氧化鈦、氧化釔、氧化锶、氧化銃、 氧化鑭或氧化鋇形成；且該第二層係由氧化銘形成。 W.如請求項31之方法，其中該石夕酸鹽介面層係由一金屬石夕 酸鹽材料（MhSixOd形成。 42.如請求項41之方法，其中該1-χ約為〇1至〇5，且其中該 金屬&quot;M”係選自由給（Hf)、結（Zr)、组（Ta)、欽㈤、邮小 紀（Y)、鑭（La)及鋁（A1)組成之群。 98898-960102.doc -4- 1282128 43·如4求項42之方法，其中該l-χ約為〇·2至ο/。 如請求項31之方法，其中該形成該矽酸鹽介面層之步驟 係由一 ALD(原子層沉積）技術、一 M〇cVD(金屬有機化學 氣相 &gt;儿積）技術或一反應性丨賤艘技術來執行。 45·如請求項31之方法，其中該高k介電層具有至少兩互相擴 放之金屬元素，其中該高k介電層係由一 MOCVD(金屬有 機化學氣相沉積）技術或一反應性濺鍍技術來形成，且其 % 中同時供應該等兩金屬元素之來源以形成該高k介電層。 46·如請求項31之方法，其中該等金屬合金氧化物包含至少 •兩互相擴散之不同金屬元素。 ’ 47·如請求項46之方法，其中該等至少兩不同之互相擴散之 # 金屬元素係在一原子級上均勻混合。 48·如請求項31之方法，其中該高k介電層具有一大於該矽酸 鹽介面層之介電常數的介電常數。 49·如巧求項31之方法，其中該高k介電層之一厚度在一約2 修埃至60埃之範圍内。 50· —種半導體裝置，其包括： 一基板； 一形成於該基板之上的矽酸鹽介面層；及 一形成於該石夕酸鹽介面層之上的高k介電層，該高k介 電層包括金屬合金氧化物； 一閘電極；及 一形成於鄰接該閘電極處的源極/汲極區域。 51·如請求項50之半導體裝置，其中該高k介電層具有一大於 98898-960102.doc -5- 1282128 該矽酸鹽介面層之介電常數的介電常數。 52·如請求項51之半導體裝置，其中該閘電極係由一金屬或 多晶矽形成。 53· —種非揮發性記憶體，其包括·· 一基板； 一閘極絕緣層； 一覆於該基板上之浮動閘極； 一形成於該浮動閘極之上的石夕酸鹽介面層； 一形成於该矽酸鹽介面層之上的高k介電層，該高k介 電層包括金屬合金氧化物；及 一覆於該高k介電層上之控制閘極。 54·如請求項53之非揮發性記憶體，其中該高k介電層具有一 大於該矽酸鹽介面層之介電常數的介電常數。 55·如請求項53之非揮發性記憶體，其中該閘極絕緣層包括 一額外之石夕酸鹽介面層及一形成於該額外之石夕酸鹽介面 層之上之額外的鬲k介電層，該高k介電層包栝金屬合金 氧化物。 56· —種非揮發性記憶體，其包括： 一基板； 一形成於該基板之上的石夕酸鹽介面層； 一形成於該矽酸鹽介面層之上的高k介電層，該高k介 電層包括金屬合金氧化物； 一覆於該基板上之浮動閘極； 一閘極間介電層；及 98898-960102.doc -6 - 1282128 /覆於該閘極間介電層上之控制閘極。 57·〆種用於一半導體裝置之電容器，其包括： /下端電極； ’該面k介 一形成於該下端電極之上的矽酸鹽介面層； 一形成於該矽酸鹽介面層之上的高k介電層 電層包括金屬合金氧化物；及 一上端電極。 大於該石夕 58·如請求項57之電容器，其中該高k介電層具有， &gt; 酸鹽介面層之介電常數的介電常數。Application for the application • f Wenshen #Patent closure replacement (January, 1996) X. Patent application scope: A multilayer structure for a semiconductor device, comprising: a layer of a silicate layer; and covering the stone eve a high-k dielectric layer on the acid salt interface layer, the high-k dielectric layer comprising a metal alloy oxide. 2. The multilayer structure of claim 1, wherein the metal alloy oxides comprise at least two interdiffused metal elements. 3. The multi-layer knot of claim 1 wherein the at least two metal a species are uniformly mixed at one atomic level. 4. A multilayer structure as in item i, wherein the metal alloy oxide comprises a mixture of at least two different metal oxides. 5. The multilayer structure of claim 4, wherein the metal oxides are selected to have a minimum net fixed charge of one of the high-k dielectric layers. 6. The multilayer structure of claim 4, wherein the metal oxide comprises ruthenium oxide, ruthenium oxide, ruthenium oxide, aluminum oxide, titanium oxide, ruthenium oxide, ruthenium oxide, ruthenium oxide, ruthenium oxide or ruthenium oxide. 7. The multilayer structure of claim 1, wherein the metal alloy oxide comprises: gold oxide, zirconium aluminum alloy oxide, button aluminum alloy oxide, titanium aluminum alloy oxide, niobium aluminum alloy oxide or tantalum Aluminum oxide. 8. The multilayer structure of claim 1, wherein the high-k dielectric layer has a dielectric constant greater than a dielectric constant of the tantalate interface layer. 9. The multilayer structure of claim 1, wherein the citrate interface layer has a dielectric greater than a dielectric constant of any of tantalum nitride, hafnium oxide or hafnium oxynitride 98898-960102.doc 1282128 10 For example, the guest of the claim 1 has only a layer structure, wherein the caprate interface layer has a thickness of about 5 angstroms to 50 angstroms. U. The multilayer structure of the present invention, wherein the citrate interface layer has a thickness of from about 5 angstroms to about 1 angstrom. 12. The multilayer structure of claim 1, wherein the citrate interface layer is formed of a metal silicate material represented by a molecular formula MhxSixO. 13. The multilayer structure of claim 12, wherein the metal, M&quot; is selected from the group consisting of 铪_(Hf), hammer (zr), tantalum (Ta), titanium (Ti), strontium (Sc), strontium ( A group consisting of Y), lanthanum (La) and aluminum (A1). ‘ 14. The multilayer structure of claim 12, wherein 1-x is greater than or equal to about n. / 15. The multilayer structure of claim 12, wherein 1-x is no greater than about 〇.5. r 16· The multilayer structure of claim 12, wherein 1-χ is from about 〇·2 to about 〇, 4. 17. The multilayer structure of claim 13, wherein the metal alloy oxide is represented by a molecular formula of AyBbyOz, and wherein 〇&lt;y&lt;l. 18. The multi-layer structure of claim 17, wherein eight are the same as or equal to [\4] or are from the same periodic table group as μ. 19. The multilayer structure of claim 17, wherein a and μ are a metal of the group λ and β is a lanthanide metal. 20. The multilayer structure of claim 17, wherein the niobium is zirconium or hafnium; and the beta is aluminum. 21. The multilayer structure of claim 17, wherein y is from about 〇·5 to about 〇9. 22. The multilayer structure of claim 17 wherein the combination of one of Α and Β is between about i··1 and about 5:1. 23. The multilayer structure of claim 22, wherein the combination ratio of A to B is about 2: i. 24. The multilayer structure of claim 23, wherein A is hafnium or zirconium; and 8 is aluminum. 25. The multilayer structure of claim 24, wherein the citrate interface layer comprises a Ming atom diffused from the 咼k dielectric layer. 26. The multilayer structure of claim 17, wherein the value of y is from the citrate interface layer. An interface between one of the bottom surfaces of the tantalum layer decreases toward an upper surface of the high &amp; dielectric layer and wherein the concentration of A has a gradient along the thickness of the high-k dielectric layer . 27. The multilayer structure of claim 17, wherein the concentration of b &gt; is inversely proportional to the concentration of A in the high-k dielectric layer. 28. The multilayer structure of claim 17, wherein the high-k dielectric layer comprises germanium atoms diffused from the tantalate interface layer. The multilayer structure of claim 1, wherein the high-k dielectric layer has a substantially amorphous crystalline structure. 30. The multilayer structure of claim 1, wherein the high-k dielectric layer forms a thickness of between about 2 angstroms and 60 angstroms. 31. A method of forming a multilayer structure for a semiconductor device, comprising: forming a caprate interface layer; and forming a high-k dielectric layer overlying the caprate interface layer, the high The k dielectric layer includes a metal alloy oxide. 32. The method of claim 31, wherein the step of forming the south k dielectric layer comprises: forming a first layer having a first metal element by ALD (atomic layer deposition); by ALD (atomic layer deposition) Forming a second layer overlying the first layer and having a second metal element of 98988-960102.doc -3- 1282128; and allowing the first Jinli-main, 疋素, δ海弟一The resulting structure is annealed at a temperature at which the metal elements diffuse from each other. 33. The method of claim 32, wherein the annealing temperature is greater than about 9 generations. 34. The method of claim 32, wherein the first layer of the first layer has a first predetermined electric quantity and the second layer has a lower predetermined electric charge of a predetermined electric charge of a layer of ~ ^ ^ ta. The method of claim 34, wherein the first predetermined charge is a positive fixed charge and the second predetermined charge is a negative fixed charge. 36. The method of claim 32, prior to the annealing step, further comprising the step of forming one or more additional first and second layers. 37. The method of claim 36, wherein the uppermost layer comprises alumina. 38. The method of claim 32, wherein the second layer is about one half of the first layer. 39. The method of claim 38, wherein the first layer is formed to a thickness of about 1 angstrom and the second layer is formed to a thickness of about 5 angstroms. The method of claim 32, wherein the first layer is formed by oxidizing, oxidizing, oxidizing alumina, titanium oxide, cerium oxide, cerium oxide, cerium oxide, cerium oxide or cerium oxide; This second layer is formed by oxidation. The method of claim 31, wherein the layer is formed of a metal silicate material (MhSixOd. 42. The method of claim 41, wherein the 1-χ is about 〇1 to 〇 5, and wherein the metal &quot;M" is selected from the group consisting of (Hf), knot (Zr), group (Ta), chin (5), postal (Y), 镧 (La), and aluminum (A1) </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The step is performed by an ALD (Atomic Layer Deposition) technique, a M〇cVD (Metal Organic Chemical Vapor Phase) technique, or a reactive helium technology. The method of claim 31, wherein The high-k dielectric layer has at least two mutually extended metal elements, wherein the high-k dielectric layer is formed by an MOCVD (Metal Organic Chemical Vapor Deposition) technique or a reactive sputtering technique, and The source of the two metal elements is simultaneously supplied to form the high-k dielectric layer. The method of claim 31, wherein the metal alloy oxide comprises A method of claim 46, wherein the at least two different interdiffused metal elements are uniformly mixed at one atomic level. 48. The method of claim 31, Wherein the high-k dielectric layer has a dielectric constant greater than a dielectric constant of the tantalate interface layer. 49. The method of claim 31, wherein one of the high-k dielectric layers has a thickness of about 2 a range of angstroms up to 60 angstroms. A semiconductor device comprising: a substrate; a citrate interface layer formed on the substrate; and a high layer formed on the silicate layer a k dielectric layer, the high-k dielectric layer comprising a metal alloy oxide; a gate electrode; and a source/drain region formed adjacent to the gate electrode. 51. The semiconductor device of claim 50, wherein The high-k dielectric layer has a dielectric constant greater than the dielectric constant of the citrate interface layer of 98898-960102.doc -5 - 1282128. The semiconductor device of claim 51, wherein the gate electrode is made of a metal Or polycrystalline germanium. 53· a non-volatile a body comprising: a substrate; a gate insulating layer; a floating gate overlying the substrate; a layer formed on the floating gate; a tantalum formed on the a high-k dielectric layer over the salt interface layer, the high-k dielectric layer comprising a metal alloy oxide; and a control gate overlying the high-k dielectric layer. 54. Non-volatile as claimed in claim 53 The memory, wherein the high-k dielectric layer has a dielectric constant greater than a dielectric constant of the citrate interface layer. 55. The non-volatile memory of claim 53, wherein the gate insulating layer comprises an additional layer of silicate layer and an additional layer formed on the additional layer of the silicate layer The electrical layer, the high-k dielectric layer is coated with a metal alloy oxide. 56. A non-volatile memory comprising: a substrate; a layer of a silicate layer formed on the substrate; a high-k dielectric layer formed over the citrate interface layer, The high-k dielectric layer comprises a metal alloy oxide; a floating gate overlying the substrate; an inter-gate dielectric layer; and 98898-960102.doc -6 - 1282128 / overlying the inter-gate dielectric layer The upper control gate. 57. A capacitor for a semiconductor device, comprising: / a lower electrode; 'the surface k is formed by a caprate interface layer formed on the lower electrode; a layer formed on the tantalate interface layer The high-k dielectric layer includes a metal alloy oxide; and an upper electrode. The capacitor of claim 57, wherein the high-k dielectric layer has a dielectric constant of a dielectric constant of the &lt;acid salt interface layer. 98898-960102.doc98898-960102.doc
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