1281259 15674twfl .doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晝素結構（pixel structure )的製 作方法，且特別是有關於一種利用四道光罩 (four_photomask )之晝素結構的製作方法。 【先前技術】 薄膜電晶體液晶顯示器（thin fllm transistor liquid crystal display，TFT_LCD )主要由薄膜電晶體陣列基板、彩 色，光陣列基板和液晶層所構成，其中薄膜電晶體陣列基 板是由多個以陣列排列之薄膜電晶體，以及與每-薄膜電 置之-晝素電極(P一雜組成而】 包娜、通道層、汲極與源極讀 來作為=顯示單元的開關元件。 ―曰曰體用 程的ί目製造::二=:，最重要的考量之-就是減少製 需的光罩數目 衣作之成本。特別是若能減少製程所 率，四道光I製程:新=二昇驗 美國專利ΙΚ Α 日體之製作的趨勢。 膜電晶體之製t _ ，028提出一種利用四道光罩進行薄 之步驟流裎剖面圖。 々白夭衣作溥胺電晶體 請參照圖，、， 再依序形成H f基板1GG上形成-職11〇， 開、、、巴緣層m、-通道材質層13〇、—歐姆接 5 1281259 15674twfl .doc/006 觸材質層140、一金屬層15〇以及一光阻層働。 。月爹,、’、圖1B ’接著對光阻層16()進行曝光以及顯影， 以形成-ffi形化光阻層職。此圖形化光阻層⑽a覆蓋 在即將形成薄膜電晶體之—主動區域17()上。值得注音的 是，此圖形化光阻層160a是使用一半透光（half_t〇iJ光 罩進订曝光，因此圖形化光阻層16Qa之中間厚度di較兩 侧厚度d2薄。 ^圖2繪不為半透光光罩之示意圖。請參照圖2，半透 光光罩200上包括了透光區A、非透光區B與半透光區c。 其中在非透光I1B與半透光區c中的基板別上設計有遮 光圖木220。§利用此光罩2⑻進行曝光製程時，半透光 區C是對應圖1B緣示之圖形化光阻層16〇a覆蓋之主動區 ^ 170的中間位置。因為半透光區^之曝光強度較非透光 區B的曝光強度高，且半透光區c之曝光強度較透光區A 白^曝光強度低，所以在曝光以及顯影後便可形成如圖ΐβ 繪不之具有不同厚度的圖形化光阻層160a。 、請繼續參照圖1C，以圖形化光阻層16此為蝕刻罩 幕’進行一蝕刻製程以移除主動區域17〇外之金屬層15〇, 而形成一圖形化金屬層15〇a。 一請參照圖1D，繼續以圖形化光阻層16〇a為蝕刻罩 幕拼進行另一钱刻製程移除主動區域170以外的歐姆接觸 材質層140與通道材質層13〇，而形成歐姆接觸層14加與 通逼層130a。於此同時，因為位於主動區域17〇上之圖形 化光阻層160a之中間厚度dl較薄，所以圖形化光阻層 1281259 15674twfl .doc/006 160a的中間部分與位於其底下的圖形化金屬層㈣&會同 B守被移除，而定義出源極l5〇a，與汲極。 請參照目1E，再繼續進行一敍刻製程，移除位於源極 150a與汲極15〇a”之間的歐姆接觸層】術與部分厚度之通 道層130a後，再移除圖形化光阻層副&，即形成一薄膜 電晶體300。 然而’在上述之薄膜電晶體300的製作過程中，需使 用到半透絲罩2GG之作法，不但會增加光罩設計上之難 度。而且在半透光光罩2〇〇之遮光圖案22〇的邊緣，容易 於曝光時產生繞射現象，而使曝光圖案的精度降低。此外， 僅利用圖形化光阻層！60a進行多次侧製程，對於薄膜電 晶體300在製作過程中的保護有可能不足夠，因而造成薄 膜電晶體300與利用其製作之畫素結構（未繪示)的製作 良率下降。 又 【發明内容】 本^明的目的就是在提供一種利用四道光罩製程之 晝t、?!·的製作方法，其適於降低製程所需之光罩數目， 亚提昇薄膜電晶體與其製作之畫素結構的製作良率。 本發明提出一種晝素結構的製作方法，其先在美板上 ίίΐ序形成一圖形化半導體層與-圖形化 ^層。在基板上形成第—絕緣層以覆蓋圖形化 。 ，者’圖形化第-絕緣層暴露出部分圖形化金屬斧。之= 板上形成—晝素，且此晝素電極與被暴露出之圖 1281259 15674twfl .doc/006 形化金屬層接觸，並同時移除了位於閘極上方之圖形化金 屬層與部分厚度的圖形化半導體層，以定義出一源極、一 汲極以及一通道層，且晝素電極會與汲極電性連接，而閘 極、源極與汲極係構成一薄膜電晶體。 本發明又提出一種四道光罩晝素結構的製作方法， 其包括下列步驟。首先，進行一第一道光罩製程，以在一 基板上形成一閘極。接著，在基板上形成一閘絕緣層以覆 蓋閘極。繼之，進行一第二道光罩製程，以於閘絕緣層上 • 及閘極上方依序形成一圖形化半導體層與一圖形化金屬 層。再來，在基板上形成一第一絕緣層以覆蓋圖形化金屬 層。繼之，進行一第三道光罩製程，以圖形化第一絕緣層， 進而暴露出部分圖形化金屬層。之後，進行一第四道光罩 製程，以在基板上形成一晝素電極，且晝素電極與被暴露 出之圖形化金屬層接觸，並同時移除了位於閘極上方之圖 形化金屬層與部分厚度的圖形化半導體層，以定義出一源 極、一汲極以及一通道層，且晝素電極會與汲極電性連接， φ 而閘極、源極與汲極構成一薄膜電晶體。 在本發明之實施例中，例如更包括在薄膜電晶體上形 成另一絕緣層。在薄膜電晶體上形成另一絕緣層之方法例 如為先在基板上形成一第二絕緣層，其覆蓋上述之薄膜電 晶體與晝素電極。接著，於第二絕緣層上形成一光阻層。 然後，對光阻層進行一背面曝光製程以及一顯影製程，以 形成一圖形化光阻層，此圖形化光阻層覆蓋住薄膜電晶 體。之後，利用圖形化光阻層做為一蝕刻罩幕，以移除覆 8 1281259 15674twfl.d〇c/〇〇6 電極上之第二絕緣層，而保留下覆蓋在薄膜電晶 體上之弟二絕緣層。 ^本發明之實施例中，上述之圖形化半導體層例如包 括一圖形化通這材質層與一圖形化歐姆接觸材質層，且圖 形化通道材質狀材質·為非㈣，而_化^ 材質層之材質例如為經摻雜的非晶;5夕。 明之實施例中’上述之在基板上形成晝素電極 之方法包括進行一濺鍍製程與一圖形化製程。 林發日狀實關巾，上叙晝素=之财例如為 銦錫1物（indium ti讀ide, IT〇)或銦鋅氧 zinc oxide, IZO ) 〇 璃。在本發狀實施射，上述之基板之㈣例如為玻 在本發明之實施例中，上述 u 氮化石夕或氧化石夕。 之閘、、、巴、、彖層之材質例如為 為金^本發明之實施例中，上述之_料層之材質例如 本發明採用四道光罩之製程，相 ▲ 製程不但可節省光罩之成本，且不;目光罩 法，可幫助製程良率之提昇。此外 光光罩之作 罩衣程，本發明之方法較不會_膜電f 先 與通道層（半導體層）造絲刻傷害。W之絲、沒極 為讓本發明之上述和其他目的、 易懂’下文特舉較佳實施例，並配合=2，更明顯 I口所附圖式，作詳細說 9 1281259 15674twfl.doc/006 明如下。 【實施方式】 本發明所提出之薄膜電晶體液晶顯示器之晝素結構 的製造方法完全不需使用半透光光罩，即可利用四道光罩 完成晝素結構之製作。而所製成之具有多個晝素結構的基 板可以用任何方式與彩色濾光基板及液晶層搭配，以構成 一薄膜電晶體液晶顯示面板。以下之說明為本發明之較佳 實施例，但並非用以限定本發明。 圖3A〜31VU會示為本發明一較佳實施例中一種畫素結 構的製作方法之步驟流程剖面示意圖。 首先在一基板400上形成一閘極410,(如圖3C所示）。 在一實施例中，形成閘極41〇，的方法例如是採用圖3八〜 圖3C之步驟。請先參照圖3A，在基板4〇〇上形成_閘極 材料層410，其中，形成閘極材料層之方法例如為濺 鍍（sputtering)。而基板4〇〇之材質例如為玻璃 材料層410之材質例如為金屬。 甲1極 接著如圖3B所繪示，進行第一道光罩製程，以在閘 極材料層410上形成一圖形化光阻層42〇。之後，利用 形化光阻層420作為罩幕進行一蝕刻製程，以圖形化此二 極材料層410而形成閘極41〇，，如圖3C所示。上述之二 刻製程例如是乾式侧製程或糾侧製程。在形托 410後’再移除圖形化光阻層42q。 " 之後，請參照圖3D，在基板4⑻上形成一閘 43〇以覆盍閘極410,。在-較佳實施例中，形成此間絕^ 1281259 15674twf 1 .doc/006 層430之方法例如為化學氣相沉積法(chemica[柯 deposition，CVD)，且間絕緣層43〇的材質例如為氮化 或氧化石夕。 接著，於閘絕緣層430上及閘極410,上方依序形成一 圖形化半導體層與一圖形化金屬層（如圖3G所示）。在 一實施例中，形成之方法例如是採用圖3E〜圖3G之步驟。 請先參照圖3E，於閘絕緣層43〇上依序形成一半導體 層440與一金屬層450。在一較佳實施例中，形成此半導 體層440之方法例如為化學氣相沉積法，且半導體層物 例如包括一通道材質層442與一歐姆接觸材質展441。通 道材貝層442之材質例如為非晶矽，而歐姆接觸材質層私4 之材質例如為經摻雜的非晶矽。而形成金屬層45〇之方法 例如為濺鑛。 、 然後，圖形化此金屬層450與半導體層44〇以形成一 圖形化金屬層450’與一圖形化半導體層44〇，(如圖3〇所 示）。在一實施例中，上述之圖形化步驟如圖3F〜3G所繪 不。請先參照圖3F，在一實施例中，進行一第二道光罩製 程，以在金屬層450上形成一圖形化光阻層422。接著衣 以圖形化光阻層422為钱刻罩幕，對金屬層45〇與半導體 層440進行一蝕刻製程。之後，再移除圖形化光阻層422^ 而形成如圖3G所繪示之圖形化金屬層45〇，與圖形化半導 體層440，。其中，圖形化半導體層44〇，包括一圖形化通道 材質層442’與一圖形化歐姆接觸材質層444,。 接著，請參照圖3H，在基板400上形成一絕緣層46〇 11 1281259 15674twfl.doc/006 以=圖形化金屬層45G，。在—實施例中，形成絕緣層46〇 =例如為化學氣相沉積法，而絕緣層楊之材質例如 為氧化發。 、 再來，對絕緣層460進行圖形化製程。在一實中， 圖形化絕緣層460之步赞如_ ^例中 31，進扞笛-、首本^ 圖 所綠示。請先參照圖 ^ /弟―返先罩製程以形成-圖形化光阻層424，其 圖形化光阻層424暴露部分之絕緣層46q , 圖形化光阻層似具有開口他與開口 424Λ=口 =立L是，後續形成的薄膜電晶體二 汲極上幵方。驗£是對縣後續形成的薄膜電晶體的 寞’請再參照圖31 ’以圖形化光阻層424為钱刻罩 幕，，緣層_進行—，以形成圖形=2 楊，，其具有開口 462與開口偏，且開口俯巴口象^ H圖形化金屬層450，。之後，移除圖形化光J ，而得到如圖3J所繪示之結構。 ® 然後，在基板4〇〇上形成一畫素電極，且圭 被暴露出之圖形化金屬層情接觸，在—較佳實於电=與 於基板彻上形成晝素電極之方法包括進行—’ -圖形化製程’其形成之方法例如是〜與 步驟。 川口从圖3JV[之 首先，請參照圖3Κ，在基板上形成 首 層470，且透明導電層47〇會與被暴 圖形化$電 彻，接觸。在-較佳實施例中，在基板4。。】形 12 1281259 15674twfl .doc/006 電層470之方法包括進行一濺鍍製程，且透明專電層47〇 之材質例如為銦錫氧化物（indium tin oxide，ITO)或銦鋅 氧化物（indium zinc oxide, IZO)。值得注意的是，上述之 透明導電層470會藉由開口 462與開口 464而與圖形 屬層450’電性接觸。 ^1281259 15674twfl .doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a pixel structure, and more particularly to a method using four reticles (four_photomask) The method of making the prime structure. [Previous technology] A thin film transistor liquid crystal display (TFT_LCD) is mainly composed of a thin film transistor array substrate, a color, a photo array substrate and a liquid crystal layer, wherein the thin film transistor array substrate is composed of a plurality of arrays. Arranged thin film transistors, and per-membrane-electrical-electrode electrodes (P-hetero-combination), Baona, channel layer, drain and source are read as the switching elements of the = display unit. The use of the process of manufacturing:: two =:, the most important consideration - is to reduce the cost of the number of masks required for manufacturing. Especially if the process rate can be reduced, four light I process: new = two test The trend of the production of the US patent ΙΚ Α 膜 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Then, the Hf substrate 1GG is formed on the surface of the 1st surface, the opening, the opening, the edge layer m, the channel material layer 13〇, the ohmic connection 5 1281259 15674twfl .doc/006 the contact material layer 140, a metal layer 15 〇 and a photoresist layer働爹,, ', Figure 1B' then exposes and develops the photoresist layer 16() to form a -ffi-formed photoresist layer. The patterned photoresist layer (10)a covers the film transistor to be formed. - On the active area 17 (). It is worth noting that the patterned photoresist layer 160a is half-transparent (half_t〇iJ mask exposure exposure, so the intermediate thickness di of the patterned photoresist layer 16Qa is thicker than the sides D2 is thin. ^ Figure 2 depicts a schematic view of a semi-transmissive reticle. Referring to Figure 2, the semi-transmissive reticle 200 includes a light transmissive area A, a non-transmissive area B and a semi-transmissive area c. The light-shielding wood 220 is designed on the substrate in the non-transparent I1B and the semi-transmissive region c. When the photomask 2 (8) is used for the exposure process, the semi-transmissive region C is a patterned photoresist layer corresponding to the edge of FIG. 1B. The intermediate position of the active area ^ 170 covered by 16〇a. Because the exposure intensity of the semi-transmissive area is higher than that of the non-transparent area B, and the exposure intensity of the semi-transmissive area c is higher than that of the transparent area A. The strength is low, so that after exposure and development, a patterned photoresist layer 160a having different thicknesses as shown in Fig. β can be formed. Continuing to refer to FIG. 1C, an etch process is performed to pattern the photoresist layer 16 as an etch mask to remove the metal layer 15A outside the active region 17 to form a patterned metal layer 15A. FIG. 1D, continuing to remove the ohmic contact material layer 140 and the channel material layer 13 以外 outside the active region 170 by using the patterned photoresist layer 16 〇 a as an etch mask to form an ohmic contact layer 14 And the pass layer 130a. At the same time, since the intermediate thickness dl of the patterned photoresist layer 160a located on the active region 17A is thin, the intermediate portion of the patterned photoresist layer 1281259 15674twfl .doc/006 160a is located at The bottom of the graphical metal layer (4) & will be removed with the B guard, and define the source l5〇a, and the bungee. Please refer to item 1E, and then continue the etching process to remove the ohmic contact layer between the source 150a and the drain 15A" and remove the patterned photoresist. The layer pair &, that is, a thin film transistor 300 is formed. However, in the fabrication process of the above-mentioned thin film transistor 300, the use of the semi-transparent wire cover 2GG is required, which not only increases the difficulty of the reticle design, but also The edge of the light-shielding pattern 22 of the semi-transmissive mask 2 is easy to cause a diffraction phenomenon during exposure, and the accuracy of the exposure pattern is lowered. Further, the patterning photoresist layer 60a is used for the multiple-side process. The protection of the thin film transistor 300 during the manufacturing process may not be sufficient, thereby causing a decrease in the yield of the thin film transistor 300 and the pixel structure (not shown) produced by the thin film transistor 300. Further, the invention provides The purpose is to provide a manufacturing method using a four-mask process, which is suitable for reducing the number of masks required for the process, and the fabrication yield of the sub-lifted thin film transistor and the pixel structure produced thereby. invention A method for fabricating a halogen structure is disclosed, in which a patterned semiconductor layer and a patterned layer are formed on the substrate, and a first insulating layer is formed on the substrate to cover the pattern. The insulating layer exposes a portion of the patterned metal axe. = The plate forms a halogen, and the halogen electrode is in contact with the exposed metal layer of the exposed picture 1281259 15674twfl .doc/006 and is simultaneously removed from the gate. The patterned metal layer and the partially patterned patterned semiconductor layer define a source, a drain and a channel layer, and the halogen electrode is electrically connected to the gate, and the gate, the source and the gate are connected. The pole system constitutes a thin film transistor. The invention further provides a method for fabricating a four-mask photoreceptor structure, which comprises the following steps. First, a first mask process is performed to form a gate on a substrate. Forming a gate insulating layer on the substrate to cover the gate. Then, performing a second mask process to sequentially form a patterned semiconductor layer and a patterned metal layer on the gate insulating layer and above the gate .again Forming a first insulating layer on the substrate to cover the patterned metal layer. Then, performing a third mask process to pattern the first insulating layer to expose a portion of the patterned metal layer. The fourth mask process is to form a halogen electrode on the substrate, and the halogen electrode is in contact with the exposed patterned metal layer, and at the same time, the patterned metal layer and the partial thickness pattern above the gate are removed. The semiconductor layer is defined to define a source, a drain, and a channel layer, and the germanium electrode is electrically connected to the drain, and the gate, the source and the drain constitute a thin film transistor. In an embodiment, the method further includes forming another insulating layer on the thin film transistor. The method of forming another insulating layer on the thin film transistor is, for example, forming a second insulating layer on the substrate, which covers the thin film electricity. Crystal and halogen electrodes. Next, a photoresist layer is formed on the second insulating layer. Then, a photoresist process and a developing process are performed on the photoresist layer to form a patterned photoresist layer covering the thin film transistor. Thereafter, the patterned photoresist layer is used as an etching mask to remove the second insulating layer on the electrode of the 81281259 15674twfl.d〇c/〇〇6 layer, while retaining the second layer covered on the thin film transistor Insulation. In the embodiment of the present invention, the patterned semiconductor layer includes, for example, a patterned material layer and a patterned ohmic contact material layer, and the patterned channel material is non-(four), and the _ chemical layer The material is, for example, doped amorphous; In the embodiment of the present invention, the method for forming a halogen electrode on a substrate includes performing a sputtering process and a patterning process. Linfa is a real-purpose towel, and the above-mentioned 昼 昼 = = = = = = = = = = = = = = = = = = = = = = = = = = = In the present invention, (4) of the above substrate is, for example, glass. In the embodiment of the present invention, the above-mentioned u nitride or oxidized oxide is used. The material of the gate, the bar, the bismuth layer, and the bismuth layer is, for example, gold. In the embodiment of the present invention, the material of the material layer is, for example, the process of using the four-mask of the present invention, and the phase ▲ process can save the reticle. Cost, and not; eye mask method, can help improve the process yield. In addition, the method of the present invention is less than the method of the invention, and the method of the invention is less than the film layer (the semiconductor layer). The wire of W, does not make the above and other objects of the present invention easy to understand. The following is a preferred embodiment, and with = 2, more obvious I port figure, for details 9 1281259 15674twfl.doc / 006 See below. [Embodiment] The method for manufacturing a halogen structure of a thin film transistor liquid crystal display according to the present invention can complete the fabrication of a halogen structure by using a four-pass mask without using a semi-transmissive mask. The substrate having a plurality of halogen structures can be combined with the color filter substrate and the liquid crystal layer in any manner to constitute a thin film transistor liquid crystal display panel. The following description of the preferred embodiments of the invention is not intended to limit the invention. 3A to 31V are cross-sectional views showing the steps of a method for fabricating a pixel structure in accordance with a preferred embodiment of the present invention. First, a gate 410 is formed on a substrate 400 (as shown in Fig. 3C). In one embodiment, the method of forming the gate 41 is, for example, the steps of FIGS. 3-8 to 3C. Referring first to Figure 3A, a _ gate material layer 410 is formed on the substrate 4, wherein the method of forming the gate material layer is, for example, sputtering. The material of the substrate 4 is, for example, a material of the glass material layer 410, for example, a metal. A pole 1 Next, as shown in FIG. 3B, a first mask process is performed to form a patterned photoresist layer 42 on the gate material layer 410. Thereafter, an etching process is performed using the patterned photoresist layer 420 as a mask to pattern the diode material layer 410 to form a gate electrode 41, as shown in FIG. 3C. The above-mentioned two-step process is, for example, a dry side process or a rectification process. The patterned photoresist layer 42q is removed after the carrier 410. " Thereafter, referring to Fig. 3D, a gate 43 is formed on the substrate 4 (8) to cover the gate 410. In the preferred embodiment, the method for forming the layer 4301259 15674 twf 1 .doc/006 430 is, for example, a chemical vapor deposition method (CVD), and the material of the interlayer insulating layer 43 is, for example, nitrogen. Or oxidized stone evening. Then, a patterned semiconductor layer and a patterned metal layer are sequentially formed on the gate insulating layer 430 and the gate 410 (as shown in FIG. 3G). In one embodiment, the method of forming is, for example, the steps of Figures 3E to 3G. Referring to FIG. 3E, a semiconductor layer 440 and a metal layer 450 are sequentially formed on the gate insulating layer 43. In a preferred embodiment, the method of forming the semiconductor layer 440 is, for example, a chemical vapor deposition method, and the semiconductor layer includes, for example, a channel material layer 442 and an ohmic contact material layer 441. The material of the channel material layer 442 is, for example, amorphous germanium, and the material of the ohmic contact material layer 4 is, for example, a doped amorphous germanium. The method of forming the metal layer 45 is, for example, sputtering. Then, the metal layer 450 and the semiconductor layer 44 are patterned to form a patterned metal layer 450' and a patterned semiconductor layer 44A (as shown in FIG. 3A). In one embodiment, the graphical steps described above are depicted in Figures 3F-3G. Referring first to FIG. 3F, in an embodiment, a second mask process is performed to form a patterned photoresist layer 422 on the metal layer 450. Then, the patterned photoresist layer 422 is used as a mask for etching, and the metal layer 45A and the semiconductor layer 440 are subjected to an etching process. Thereafter, the patterned photoresist layer 422 is removed to form a patterned metal layer 45A as illustrated in FIG. 3G, and a patterned semiconductor layer 440. The patterned semiconductor layer 44A includes a patterned channel material layer 442' and a patterned ohmic contact material layer 444. Next, referring to FIG. 3H, an insulating layer 46 〇 11 1281259 15674 twfl.doc/006 is formed on the substrate 400 to form a patterned metal layer 45G. In the embodiment, the insulating layer 46 is formed = for example, a chemical vapor deposition method, and the material of the insulating layer is, for example, oxidized hair. Then, the insulating layer 460 is patterned. In a real world, the step of the patterned insulating layer 460 is like the green image of the _ ^ example 31, the 捍 flute -, the first ^ picture. Please refer to FIG. 2 to form a patterned photoresist layer 424. The patterned photoresist layer 424 exposes a portion of the insulating layer 46q. The patterned photoresist layer has an opening and an opening 424. = Li L is the subsequent formation of the thin film transistor on the second pole. The test is the 薄膜 of the thin film transistor formed in the county. Please refer to Figure 31 again. The patterned photoresist layer 424 is used as a mask for the money, and the edge layer _ is performed to form a pattern = 2 yang, which has The opening 462 is offset from the opening, and the opening is like a patterned metal layer 450. Thereafter, the patterned light J is removed to obtain a structure as shown in FIG. 3J. ® Then, a pixel electrode is formed on the substrate 4, and the exposed metal layer is exposed, and the method of forming the halogen electrode on the substrate is performed. The method of forming a 'graphical process' is, for example, a ~ and a step. Kawaguchi from Fig. 3JV [First, please refer to Fig. 3, a first layer 470 is formed on the substrate, and the transparent conductive layer 47 is electrically connected to the image. In the preferred embodiment, on the substrate 4. . Shape 12 1221259 15674twfl .doc/006 The method of the electric layer 470 includes performing a sputtering process, and the material of the transparent electric layer 47 is, for example, indium tin oxide (ITO) or indium zinc oxide (indium zinc). Oxide, IZO). It should be noted that the transparent conductive layer 470 is electrically connected to the patterned layer 450' through the opening 462 and the opening 464. ^
之後，對透明導電層470進行一圖形化製程。在一齒 施例中，圖形化透明導電層470之步驟如圖3L〜3M所二 =請先參關3L，進行-第四道光罩·，以在透明^ 47〇上形成一圖形化光阻層426，其中圖形化光阻層 層會對應於_匕躲 為飾功丨w- 、 接者以此圖开》化光阻層426 ㈣鶴了二:：=a透：^層 厚=:半導體層 道層44Π， 及極450 b以及_通 而閘極410’’且^電極佩會與没極45〇，b電性連接， 500，如圖與汲極侧構成一薄膜電晶體 此薄臈電日日接者再移除此圖形化光阻層426。 且薄膜電曰曰:ί5〇〇Γ:ί控制晝输470a之開關元件， 由所：H素電極條構成—晝素結構。 結構的製作。二利用四道光罩即可完成晝素 透光光罩，目此可卩^製財，㈣^使用半 外低先罩設計所需之成本，而且各製程 13 腫 中所使用之圖形化光阻層並沒有局部厚度較薄的情形 而可充分發揮餘刻罩幕之功能，以免於在韻刻步驟 經形成之結構造成钱刻傷害。所以本發明之方法較不合董 薄膜電晶體之源極、汲極與通道層（半導體層）造成^ 傷害，故有助於良率之提昇。 ^ 此外，在本發明之一較佳實施例中，於形成薄膜電曰曰 體5〇〇之後，更包括在薄膜電晶體5〇〇上形成另一絕緣曰曰 復盍另:絕緣層之製作流程的剖面示意圖。 明芩,、?、圖4A’首先，在基板4〇〇上 一 =上㈣__財她二a:=:彖 如為化學氣相沉積法，且絕緣層6㈣ ㈣。:：:層：:：t $ 成-― 一銪岑制# / 運仃一月面曝光製程630以及 曰^奴，以形成如圖4B綠示之圖形化光阻声62〇，及 此3化光阻層咖，覆蓋住薄膜電晶體 / 崎二’利用圖形化光阻層62〇,作為 上之絕緣層61G，而伴留%^移//蓋在晝素電極· __層⑽，二晶體獅上之經 點：綜上所述’本發明晝素結構的製作方法包括下列優 ⑴本發明利用四道光罩即可製作晝素結構，相較 1281259 15674twfl .doc/006 於習知的五道光罩製程可簡化製程，並降低光罩之成本。 (2) 本發明不需使用半透光光罩，所以可避免在半 透光光罩上之圖案的邊緣產生曝光精度較差的問題。 有助於製程良率之提昇。 (3) 本發明之製程對於賴電晶體之雜、 通道層（半導體層）能夠提供更好之保護。 〃 雖然本發明已以較佳實施例揭露如上，然其並非用以 限疋本發明，任何熟習此技藝者，在不脫離本發明之浐抽 和範圍内，當可作些許之更動與潤飾，因此本發明之ς罐 範圍當視後附之ψ料纖騎狀者鱗。 …又 【圖式簡單說明】 圖1Α〜1Ε繪示為習知中製作薄膜電晶體之步驟漭 剖面圖。 mil枉 圖2緣示為半透光光罩之示意圖。 圖3A〜3M繪示為本發明一較佳實施例中一種查 構的製作方法之步驟流程剖面示意圖。 ^ 圖4A〜4C繪示為本發明一較佳實施例中在薄膜帝曰 體上覆盍另-絕緣層之製作流程的剖面示意圖。、、私曰曰 【主要元件符號說明】 100 :基板 110 :閘極 120 :閘絕緣層 130 :通道材質層 130a ·通道層 15 1281259 15674twfl .doc/006 140 :歐姆接觸材質層 140a :歐姆接觸層 150 :金屬層 150a :圖形化金屬層 150a’ ：源極 150a” ··汲極 160 :光阻層 160a :圖形化光阻層 _ 170 :主動區域 200 :半透光光罩 210 ··透明基板 220 :遮光圖案 300 :薄膜電晶體 400 :基板 410 :閘極材料層 410 ’ ：閘極 φ 420、422、424、426 :圖形化光阻層 424a、424b、462、464 :開口 430 :閘絕緣層 440 :半導體層 440’ ：圖形化半導體層 440’a :通道層 442 :通道材質層 442’ ：圖形化通道材質層 16 1281259 15674twfl.doc/006 444 :歐姆接觸材質層 444’ ：圖形化歐姆接觸材質層 450 :金屬層 450’ ：圖形化金屬層 450’a :源極 450’b :汲極 460 :絕緣層 460’ ：圖形化絕緣層 _ 470 :透明導電層 470a :晝素電極 500 :薄膜電晶體 610 :絕緣層 610’ ：經蝕刻的絕緣層 620 :光阻層 620’ ：圖形化光阻層 630 :背面曝光製程 φ dl、d2 :厚度 A :透光區 B :非透光區 C ·半透光區 17Thereafter, a transparent process is performed on the transparent conductive layer 470. In a tooth embodiment, the step of patterning the transparent conductive layer 470 is as shown in FIGS. 3L to 3M = please first participate in 3L, and then - a fourth mask to form a patterned photoresist on the transparent ^ 47 〇 Layer 426, wherein the patterned photoresist layer corresponds to _ 匕 为 饰 饰 饰 - - - 、 、 、 、 、 》 》 》 》 426 426 426 426 426 426 426 426 426 426 426 426 426 426 426 : : : : : : : : : : : : : : : The semiconductor layer layer 44 Π, and the pole 450 b and the _ pass gate 410 ′′ and the electrode electrode and the electrodeless 45 〇, b electrically connected, 500, as shown in the figure and the drain side constitute a thin film transistor The patterned photoresist layer 426 is removed again. And the thin film electric 曰曰: ί5 〇〇Γ: ί control 昼 470a switching elements, consisting of: H element electrode strip - halogen structure. The production of the structure. Second, the use of four masks to complete the alizarin light-transmissive mask, which can be used to make money, (4) ^ the cost of using a semi-outer low-cap design, and the pattern of photoresist used in each process 13 swollen The layer does not have a thin partial thickness and can fully exert the function of the residual mask to avoid damage caused by the structure formed in the rhyme step. Therefore, the method of the present invention is less effective than the source, the drain and the channel layer (semiconductor layer) of the thin film transistor, thereby contributing to the improvement of the yield. In addition, in a preferred embodiment of the present invention, after the formation of the thin film electrical body 5〇〇, the formation of another insulating layer on the thin film transistor 5〇〇: the fabrication of the insulating layer is further included. A schematic cross-section of the process. Alum, ??, Fig. 4A' First, on the substrate 4, a = upper (four) _ _ _ her two a: =: 彖 as the chemical vapor deposition method, and the insulating layer 6 (four) (four). :::Layer:::t $ 成-― 一铕岑制# / 仃 仃 面 面 exposure process 630 and 曰^ slave, to form a graphical resistive sound 62〇 as shown in Figure 4B green, and 3 The photoresist layer covers the thin film transistor / Saki II' using the patterned photoresist layer 62〇 as the upper insulating layer 61G, with the %^ shift//cover on the pixel electrode __ layer (10), The point on the two-crystal lion: In summary, the method for producing the halogen structure of the present invention includes the following advantages: (1) The present invention can produce a halogen structure by using four masks, compared with 1281259 15674 twfl.doc/006. The five-mask process simplifies the process and reduces the cost of the mask. (2) The present invention does not require the use of a semi-transmissive reticle, so that the problem of poor exposure accuracy at the edge of the pattern on the translucent reticle can be avoided. Helps improve the process yield. (3) The process of the present invention can provide better protection for the impurity and channel layers (semiconductor layers) of the Lai electric crystal. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the scope of the invention. Therefore, the range of the crucible cans of the present invention is attached to the scale of the fiber-like rider. ...also [Simple description of the drawings] Fig. 1Α~1Ε is a cross-sectional view showing a step of fabricating a thin film transistor in the prior art. Mil枉 Figure 2 shows a schematic view of a semi-transmissive reticle. 3A to 3M are cross-sectional views showing the steps of a method for fabricating a configuration according to a preferred embodiment of the present invention. 4A to 4C are cross-sectional views showing a process of fabricating a double-insulating layer on a thin film emmore body in accordance with a preferred embodiment of the present invention. , private 曰曰 [Main component symbol description] 100 : Substrate 110 : Gate 120 : Gate insulating layer 130 : Channel material layer 130a · Channel layer 15 1281259 15674twfl .doc / 006 140 : Ohmic contact material layer 140a : Ohmic contact layer 150: metal layer 150a: patterned metal layer 150a': source 150a" · drain 160: photoresist layer 160a: patterned photoresist layer _ 170: active region 200: semi-transmissive mask 210 · transparent substrate 220: light shielding pattern 300: thin film transistor 400: substrate 410: gate material layer 410': gate φ 420, 422, 424, 426: patterned photoresist layer 424a, 424b, 462, 464: opening 430: gate insulation Layer 440: semiconductor layer 440': patterned semiconductor layer 440'a: channel layer 442: channel material layer 442': patterned channel material layer 16 1281259 15674twfl.doc/006 444: ohmic contact material layer 444': patterned ohmic Contact material layer 450: metal layer 450': patterned metal layer 450'a: source 450'b: drain 460: insulating layer 460': patterned insulating layer _470: transparent conductive layer 470a: halogen electrode 500: Thin film transistor 610: insulating layer 610': Etched insulating layer 620: photoresist layer 620': patterned photoresist layer 630: backside exposure process φ dl, d2: thickness A: light transmissive region B: non-transmissive region C · semi-transmissive region 17