TWI278115B - Semiconductor device and production method thereof - Google Patents

Abstract

A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Description

1278115, ' Λ • IX, invention description: Technical field of C invention 3 Cross-reference to related application This patent application is based on the transcript priority 5 patent application No. 2005-182382 submitted on June 22, 2005 The entire content of the case is incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a high operating speed due to stress application and a method of fabricating the semiconductor device. C. Prior Art 3 Background of the Invention Semiconductor components are manufactured on ever smaller scales to increase their speed of operation and to expand their functions. To date, large transistors having a gate length of less than 100 nanometers (nm) have been fabricated. Size integrated circuit (LSI). As the electro-crystals are increasingly miniaturized following a scaling rule, the operating speed of the semiconductor components is also increased. However, when the gate length becomes extremely short, the low limit voltage is reduced, that is, a so-called "short path" effect occurs. Various methods have been proposed to reduce the short path effect, but the effects of these methods have become more and more limited. On the other hand, because the mobility of the hole is lower than that of the electrons in the sputum, the operation speed of the P-channel MOS (metal-oxide-oxide) transistor is increased in the related art (where the hole is used as a carrier) Becoming a major discussion 1278115· - The p-channel M0S electro-crystal system is a component of a CMOS (Complementary MOS) inverter circuit that is a basic component of a logic circuit. Therefore, if the p-channel MOS transistor cannot operate at a high speed, the speed of the CM 〇s inverter circuit cannot be increased, so the speed of the LSI cannot be improved. 5 A method of improving the mobility of a hole by applying a compressive stress to a passage area of a stone substrate. Figure 1 is a cross-sectional view of a P-channel MOS transistor 1 包含 containing compressive stress. As shown in Fig. 1, a gate electrode 103 is arranged on the 石 基材 substrate 1 〇 1 10 with a gate insulating film 102 therebetween. On the side wall of the gate electrode 103, sidewall insulating films 104 and 〇43 are provided to cover the surface of the ruthenium substrate 1〇1. In the crucible substrate 101, a via region is formed under the gate electrode 1?3. Further, in the crucible substrate 101, a source extension region 101A and a drain extension region 1018 in which a p-type impurity element is implanted are formed on both sides 15 of the gate electrode 1?. Further, a source region i〇is and a φ φ polar region 101D in which a P-type impurity element is implanted are formed on the outer side of the source extension region 101A and the drain extension region 101B. The hole extends from the source region 101S through the source extension 101A, the pass region, and the drain extension 101B, and finally reaches the drain region 101D. The magnitude of an electrical 20-hole flow is controlled by the gate voltage applied to one of the gate electrodes 103 in one of the via regions. Further, in the p-channel MOS transistor 100, the SiGe mixed crystal layers 105A and 105B are formed in the region outside the sidewall insulating films 1 〇 4 8 and 1 〇 4 矽 in the 矽 substrate 1 〇 1 . The SiGe mixed crystal layers 105A and 105B are formed in the tantalum substrate 101 by epitaxial growth. Since the lattice constant of the SiGe mixed crystal layer 105A and 1278115·105B is larger than the lattice constant of the tantalum substrate 1〇1, the KSiGe mixed crystal layer is formed in a horizontal direction as indicated by an arrow “a” in FIG. A compressive stress is induced in 105A and 105B. Due to this compressive stress, the lattice structure of the SiGe mixed crystal layers 105A and 105B is as indicated by the arrow "b" in the second figure, which is shown to be stretched in a vertical direction, that is, a lattice distortion occurs. Due to this distortion, The passage zone of the Shixi substrate 101 embedded in the SiGe mixed crystal layer 1〇5-8 and 1〇56, in response to the stretching of the sand mixed crystal layer ship and the lattice structure of 105B, the lattice of the 1⁄1 substrate of Shixi substrate The structure such as the arrow 第" of the is| is stretched in the vertical direction. As a result, in the passage region of the stone substrate 101, a uniaxial compressive stress is induced in the horizontal direction as shown in the front head "d" of Fig. 1, Fig. 15 is shown in Fig. 1 In the channel M0S transistor, the symmetry of the crystal in the channel region is locally adjusted due to the uniaxial I·compressive stress in the channel region. In response to the symmetry variation in the channel region, the valence band and light weight of the heavy hole The degradation of the hole price band is removed. As a result, the hole mobility increases in the channel region and the operating speed of the transistor increases. In particular, in the channel region, the local p also attracts hair due to ink shrinkage stress. The resulting hole activity is increased, and the second::::100 nm open length of the transistor has a significant increase in the operating speed of the transistor. - For details of the relevant technology, refer to the US Patent 6 6 2 (3) No. (hereinafter referred to as "reference file 1,"). SUMMARY OF THE INVENTION The general object of the present invention is to solve one or more of the related art 20 127 81 154 problems. The effect and the improved tailoring are specifically to provide a semiconductor element capable of suppressing the activity of the manufacturing of the short via 2, and the semiconductor component 5 10 15 - the first aspect, the semiconductor component is provided. The first region is formed on the sidewall of the first electrode; the first sidewall is formed on the sidewall of the first electrode; the gate electrode is formed in the via region of the shirt material; the gate electrode corresponds to the via insulating film, and the first sidewall is formed on the sidewall of the first electrode; a second sidewall insulating film, a stretching region, and a side surface of the palpebral wall; - a source extension region and a finite electrode extension having a spurt to form a stone on the side of the diffusion electrode a substrate region is embedded in the substrate; a source region 2 and a drain region are formed from a diffusion region having a predetermined conductivity type, and the diffusion region is formed in the stone substrate outside the second sidewall insulation film and The disk source extension region and the drain extension region are respectively in contact; and a semiconductor mixed crystal layer is formed on the outer layer of the second sidewall insulating film and the insect crystal grows on the stone substrate. The crystal layer is a self-SiGe mixed junction when the predetermined conductivity type is P-type. Formed, or formed from a SiC mixed crystal when the predetermined conductivity type is n-type, the semiconductor mixed crystal layer includes - an impurity having a predetermined conductivity type, and the semiconductor mixed crystal layer is grown to a stone substrate and a gate insulating film Between the different levels of the interface, the semiconductor mixed crystal layer has an extension between a bottom surface of the second sidewall insulating film and a surface of the germanium substrate, the extension contacting the surface extension and the drain Part of the extension. According to the present invention, since a semiconductor mixed junction 20 1278115· 5 10 15 with a predetermined conductivity type grows on the side of the path ^, a single w force is induced in the via region, and the passage region is greatly improved. The activity of the carrier. The semiconductor composite layer 0% layer has an extension between the bottom surface of the second sidewall film and a surface of the stone substrate, and is in contact with the portion of the body According to the extension of the H-conductor mixed crystal layer, just below the body-mixed crystal layer, a stress is induced relative to the uniaxial η-magnet force in the plane of the substrate in the stone substrate, and is in the channel region. On the eve of the crystal, the material is grounded in the same direction as the uniaxial force. Since this stress is located in the same direction as the early stress, it tends to increase the stress in the passage region, which further increases the mobility of the carrier. · #如' When the semiconductor component is a _ρ via m〇s transistor, the semiconductor = crystalline layer is formed from a mixed crystal layer, and the stress along the hole is moved from both sides of the via region. The SiGe mixed crystal layer is applied as the extension of the s 1G e mixed crystal layer contacts an extension of the source extension region of the source region of the source region, and the extension of the mixed crystal layer will - Tensile stress is applied to the source extension or the non-polar extension. In this example, since the source region and the secret region are subjected to the mixed crystal layer, the tearing age layer is stretched and deformed in the source extension region and the secret extension region in contact with the extension portion, and (4) the variable consumption The county receives the lion-mail combination = the relative stress in the crystallization of the stone. As a result, it is possible to connect the deformation generated by the mixed crystal layer in the 2-zone region, and the compression should be applied to the channel region. This further increases the mobility of the carrier. ^ 20 1278115. 、 On the other hand, when the semiconductor component is an η-channel MOS transistor, the semiconductor-contained crystal layer is formed from a mixed crystal layer and is induced on the via region along the electron transfer direction. Extensive stress. In this shot, because of the extension of the 5 mixed crystal layer, a gradual stress is applied to the source extension region and the drain extension region of the access region 57, and the residual stress can be effectively & In the It Road area, Qian-Step increases the activity of the system of the access area. And 'because the semiconductor mixed crystal layer includes conductive impurities and contacts to the one of the source extension region and the electrode extension region, the stray resistance (10) ay resistance can be greatly reduced, and this can improve the semiconductor device 10 Drive current. According to a second aspect of the present invention, there is provided a method for fabricating a semiconductor component comprising a semiconductor mixed crystal layer on a side of a via region to induce a stress in the via region, comprising the steps of: forming a gate a pole insulating film is disposed on the stone substrate; a pole electrode is formed on the substrate of the Shixi 15 and a gate insulating film is disposed corresponding to the via region; and the first diffusion region is formed on each side of the intermediate pole The top substrate has a predetermined conductivity type; a first sidewall insulating film is formed on the sidewalls of the gate electrode and the gate insulating film, and a portion of the first sidewall insulating film extends on the germanium substrate; forming a first Two sidewall insulating films are on the side surface of the first sidewall; a second diffusion region is formed in the germanium substrate outside the second sidewall insulating film and has a predetermined conductivity type, and the second diffusion regions form a source a region and a drain region; corresponding to the source region and the drain region, the channel is formed in the germanium substrate by etching, so that the side surface and the bottom surface of the trench are continuously covered by the first expansion region, The channel has a side defined by the section Removing a portion of the first sidewall insulating film; forming a 1278115·long semiconductor mixed crystal layer by epitaxial growth to fill the channel, and the semiconductor mixed crystal layer is grown between the germanium substrate and the gate insulating film One of the interfaces is different in height, wherein in the removing step, a portion of the first sidewall insulating film between a bottom surface of the second sidewall insulating film and a surface of the germanium substrate is removed to form a space In the step of growing the semiconductor mixed crystal layer, the semiconductor mixed crystal layer fills the space. According to the present invention, a channel is formed, and a portion of the first sidewall insulating film between a bottom surface of the second sidewall insulating film and a surface of the germanium substrate is removed and a space is formed, and the semiconductor mixed crystal layer is exposed. Crystal growth to fill 10 channels and space. The semiconductor mixed crystal layer grows in the space from the surface of the tantalum substrate, and the semiconductor mixed crystal layer fills the space and grows along the second side wall insulating film. Therefore, in the treatment using HF, the semiconductor mixed crystal layer and the second side wall insulating film are in close contact with each other, and the space is filled. This prevents HF from entering the space between the half-conductor mixed crystal layer and the second side wall insulating film, and prevents the first side wall insulating film from being directly exposed. As a result, it is possible to prevent the first sidewall insulating film from being partially removed to expose the germanium substrate, and in the step of forming a germanide layer, the germanide layer can be prevented from impairing the germanium substrate as a spear. These and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a p-channel MOS transistor 100 including a compressive stress; Fig. 2 is a cross-sectional view of a MOS transistor disclosed in Reference 2

11 1278115· < FIG. 3 is a cross-sectional view showing an example of a semiconductor element according to a first embodiment of the present invention; FIGS. 4A to 4C are cross-sectional views showing a portion of the semiconductor element 10 in FIG. To show a method for fabricating the semiconductor device 10 according to one embodiment of the present invention; FIGS. 5A and 5B are cross-sectional views showing a portion of the semiconductor device 10 in FIG. 3 continuing from FIG. 4C to show the present invention. The method for fabricating the semiconductor device 10 of the present embodiment; 10 FIG. 6 is a cross-sectional view showing an example of the semiconductor device 30 according to the second embodiment of the present invention; FIGS. 7A and 7B are diagrams showing the sixth A cross-sectional view of a portion of a semiconductor device 30 in the drawing to show a method for fabricating a semiconductor device 30 according to a second embodiment of the present invention; 15 FIG. 8 is a view showing a semiconductor device according to a third embodiment of the present invention. A cross-sectional view of an example; FIGS. 9A to 9C are cross-sectional views showing a portion of the semiconductor element 40 of FIG. 8 to show a semiconductor element 40 for fabrication according to a third embodiment of the present invention. 20 is a cross-sectional view showing an example of a semiconductor device 50 according to a fourth embodiment of the present invention; and FIGS. 11A to 11C are cross-sectional views showing a portion of the semiconductor device 50 in FIG. 10 to show A method for fabricating a semiconductor device 50 according to a fourth embodiment of the present invention; 1278115· FIGS. 12A to 12C are cross-sectional views showing a portion of the semiconductor device 50 in FIG. 10 continued from the 11th CC to show the present invention according to the present invention. The method for fabricating the semiconductor device 50 of the embodiment; FIG. 13 is a cross-sectional view showing a portion of the semiconductor device 50 from the continuation of the 12th CC, showing a method for fabricating the semiconductor device 50 according to the embodiment of the present invention; Figure 14 is a cross-sectional view showing an example of a semiconductor device 60 according to a fifth embodiment of the present invention; and Figure 15 is a cross-sectional view showing an example of a semiconductor device 10 65 according to a sixth embodiment of the present invention; 16 is a cross-sectional view showing an example of a semiconductor device 70 according to a seventh embodiment of the present invention; and FIG. 17 is a view showing an eighth embodiment according to the present invention. 1 is a cross-sectional view showing an example of a semiconductor device according to a ninth embodiment of the present invention; and FIG. 19 is a view showing a semiconductor device according to a tenth embodiment of the present invention. 20 is a cross-sectional view showing an example of a semiconductor element 20 according to an eleventh embodiment of the present invention; and FIG. 21 is a view showing a semiconductor device according to a twelfth embodiment of the present invention. A cross-sectional view of an example. [Embodiment 3] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 13 1278115* Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The inventors of the present invention have discovered the following new technical subjects that have not been disclosed so far. It is known that when the compressive stress induced in the via region of a circuit wafer is increased, the hole mobility in the via region is increased and the driving current of the transistor is increased. However, as shown in the figure}? In the channel M〇s transistor, when the &Ge mixed crystal layer 105A and 1 〇5B have a large interval, the vertical stretching system at the center of the via region of the tantalum substrate 1〇1 becomes small, so It is impossible to induce a large compressive stress in the passage zone. In order to increase the compressive stress, it is effective to reduce the interval between the siGe 1 〇 mixed crystal layers 105A and 1 〇 5B. However, in a transistor having a very short gate length, the source extension region 1〇1A and the drain extension region 1〇1B on both sides of the via region, and the source extension region 1〇1A and the immersion The capsule region (not shown) on the inner side of the extension region 1〇1B has a function of suppressing the short channel effect. Since the siGe mixed crystal layers 15 1 〇 5 Α and 105 B are formed after the impurities are implanted in the source extension region 101A, the drain extension region 101B, and the capsular region, it is necessary to form a channel in close proximity to these impurity regions. Therefore, when attempting to reduce the interval between the siGe mixed crystal layers 1〇5a & 1〇5B, when the channel is formed, the impurity profile is disturbed, and the roll-off characteristic of the low limit voltage is deteriorated. The leakage current increases, that is, 20 short path effects occur. It is easy to say that when attempting to increase the compressive stress and thus increase the drive current by reducing the interval between the SiGe mixed crystal layers 105A and 105B, consideration should be given to the trade-off relationship with the suppression of the short path effect. For example, 'this topic is discussed in "T Timpson et al., 14 1278115 · IEEE Transactions on Electrons Device, Vol. 51, No. ll, November 2004, ρρ·1790_1797, (hereinafter referred to as "Reference 2" Fig. 2 is a cross-sectional view of one of the m〇S transistors disclosed in reference 2. The M0S electromorph system is modified by one of the MOS transistors 100 of Fig. 1, and therefore, the same number is assigned to The same components are shown in Fig. 1 and the repeated description is omitted. As shown in Fig. 2, the SiGe mixed crystal layers ι〇5Α and 105B are again epitaxially grown to form the channel formed in the ruthenium substrate 101. 5Aa and 105Ba fill 10 to a height L shown by a broken line in Fig. 2. As shown in Fig. 2, the height L· is higher than the interface between the base material 101 and the gate insulating film 102. In Fig. 2, A germanide layer 106 is formed on the sSiGe mixed crystal layers 105A and 105B; in fact, a nickel germanide layer is used in a 9 Å nanometer or a 90 nm semiconductor element. When a nickel bismuth layer is formed, hf is used. (hydrogen 15 fluoro acid) is pretreated to remove the surface of the SiGe mixed crystal layers 105A and 105B a native oxide film. In this process, if there is a space between the SiGe mixed crystal layers 105A and 105B and the outer surfaces of the sidewall insulating films 1A and 4B, due to the cross section of the SiGe mixed crystal layers 105A and 105B, The gate insulating film 102 formed by the hafnium oxide film or the sidewall insulating films ι〇4Α and 104B is dissolved by HF 2〇, and a part of the surface of the tantalum substrate 1〇1 is finally exposed. If the telluride layer 106 is in such conditions Formed underneath, the germanide layer 106 may break the pn junction formed between the source extension 101 and the drain extension 101B and the n-type germanium substrate 101 as a spear, and extend to the substrate ιοί The η well region causes a strong junction leakage. 15 As described below, the present invention provides a semiconductor element and a method of manufacturing the body element to solve the problems. First Embodiment FIG. 3 is a view showing a first embodiment according to the present invention. A cross-sectional view of an example of a semiconductor device. The semiconductor device 10 shown in Fig. 3 is a P-channel MOS transistor, and the device region 11 defined by a component isolation region 12 is formed in one or two. As the main plane (1(8) a single crystal stone substrate 11 on the crystal plane. Corresponding to the element region 11A which is a type 1 semiconductor region, a type I Si well 11n is formed in the tantalum substrate U. The base layer including the n-type element region ha On the material π, a gate insulating film 13 is formed on the germanium substrate corresponding to a via region in the germanium substrate. For example, the gate insulating film 13 can be a self-thermal oxide film, a nitrided nitride, or a nitrogen. Formed by oxidized stone or other objects. In this example, it is assumed that the gate insulating film 13 is formed of a hafnium oxynitride film having a thickness of 1.2 nm. On the gate insulating film 13, a gate electrode 14 is formed from a polysilicon film including boron or other p-type impurities. On the side walls of the laminated structure of the gate insulating film 13 and the gate electrode 14, the first side wall insulating films 16 and 16 are formed, for example, by CVD from a hafnium oxide film. The first side wall insulating films 16A and 16B cover a portion of the germanium substrate adjacent to the gate insulating film 13 and cover the side walls of the gate insulating film 13 and the gate electrode 14. The second side wall insulating films 18A and 18B are formed, for example, from a tantalum nitride film on the side surfaces of the side walls 16A and 16B. 1278115. In the tantalum substrate 11, the channels 111A and 111B are formed outside the second side wall insulating films 18A and 18B, respectively. The siGe mixed crystal layers 19A and 19B including p-type impurities are epitaxially grown in the trenches 111A & 111B to fill the trenches 111A and 111B, respectively. The siGe mixed crystal 5 layers 19A and 19B which are epitaxially grown on the tantalum substrate have a lattice constant larger than the base material η, and as described above with reference to Fig. 1, a uniaxial compressive stress It is applied to the via region below the gate electrode 14 in the tantalum substrate. The second side wall insulating films 18A and 18B cover portions of the SiGe mixed crystal layers 19A and 19B and cover side surfaces of the first side walls 16 A and 16B. In the P-channel MOS transistor 10 shown in Fig. 3, the n-type capsule implant region 11pc is formed in the element region iiA on both sides of the gate electrode 13. For example, the η-type cyst implantation region llpc is formed from obliquely implanted Sb or other n-type impurities. Further, a source extension region 11ΕΑ and a drain extension region ι1 are formed to partially overlap the n-type capsule implant region iipC. 15 source extension region 1 and the extension region 11EB belong to the p-type, and respectively contact the p-type diffusion regions llSp and llDp, which respectively form a source region 11S of the p-channel m〇s transistor 10 and a Bungee area 11D. The p-type diffusion regions 11 and llDp surround the SiGe mixed crystal layers 19A and 19B, respectively, and are part of the source region 11S and the drain region 11D. With this structure, the p 2 〇 type SiGe mixed crystal layers 19A and 19B having a small band gap do not directly contact the n-type well 1 ηη, and this reduces the pn junction at the interface between Si and SiGe. Leakage current in. The telluride layers 20A and 20B are formed on the SiGe mixed crystal layers 9a and 19B, respectively, and a germanide layer 20C is formed on the gate electrode 13. Because Shi Xi 17 1278115·chemical layers 20A, 20B, 20C are actually the reaction products between the metal and SiGe mixed crystal layers 19A and 19B, the vaporized layers 20A, 20B, 20C include metal-germano-telluride and metal- Niobium oxide. Hereinafter, for convenience of description, only the telluride layers 20A, 20B, and 20C are formed from "telluride". 5 Although not shown, a tantalum layer including p-type impurities is formed on the SiGe mixed crystal layers 19A and 19B, and a germanide layer may be formed on the tantalum layer, that is, the surface of the chopped layer is converted into a lithiated layer. The Ge-free layer is superior to the above-mentioned telluride layer of the SiGe mixed crystal layers 19A and 19B. In the p-channel MOS transistor 10 shown in Fig. 3, each of the SiGe mixed crystal layers 19A and 19B has a side surface 19b and a bottom surface 19c for defining the SiGe mixed crystal layers 19A and 19B. The side surface 19b or the bottom surface 19c is a flat cross section. The bottom surface 19c is located in a (100) plane parallel to the major plane of the crucible substrate 11, while the side surface 19b is nearly perpendicular to the bottom surface 19c. Therefore, the side surface 19b of the SiGe mixed crystal layer 19A facing each other and the side surface 19b of the SiGe mixed junction layer 19B are nearly perpendicular to the main plane of the crucible substrate 11, and this structure can effectively restrict the passage. Uniaxial compressive stress in the zone. Since the Ge concentration is more than 20 atom%, a strong compressive stress is applied to the via region, and the Ge concentration in the SiGe mixed crystal layers 19A and 19B is in the range of 20 atom% to 40 atoms, and the ruthenium group can be prevented. The dislocation defect on the interface between the material mixed crystal layers 19A and 19B. According to the experimental results in the present invention, the component area of the semiconductor element is defective! In A, it is found that even when the thickness of the semiconductor layer (formed in a region having a limited area) for constituting the SiGe mixed crystal layers 19A and 19B is grown to be larger than the thickness of the film of 18 1278115, sometimes the semiconductor layer is grown. The quality has not deteriorated. This is different from a model of two-dimensional continuous epitaxial growth. Further, it was found that even when the Ge concentration was increased above the critical concentration and it was considered that the critical concentration may cause a poor discharge defect, sometimes the quality of the grown semiconductor layer did not deteriorate. Further, it has been found that the effective critical film thickness is increased when the growth temperature is lowered, and in the present invention, the deformation can be effectively applied by the film of the SiGe mixed crystal layers 19A and 19B which are selectively grown locally at a low temperature. On the path. From this experiment, it was found that when the Ge concentration in the SiGe mixed crystal layers 19A and 19B was low at or equal to 40 atom%, the SiGe mixed crystal layers 19A and 19B were epitaxially grown to 10 lengths. It is known that in the SiGe mixed crystal layers 19A and 19B having a high Ge concentration, the solubility limit of boron is increased, and the impurity concentration can be as high as 1 χ 1 〇 22 cm _3. The impurity concentration in the SiGe mixed crystal layers 19 ι and ι 9 设定 was set to be in the range of from 3 × 10 19 cm to 3 x 1 〇 21 cm. Therefore, the electric resistance of the SiGe 15 mixed crystal layers 19A and 19B can be lowered. The SiGe mixed crystal layers 19A and 19β have extension portions 19Aa and 19 such that the extension portions 19Aa and 19Ba are formed on respective sides of the first side wall insulation films 16A and 16B below the bottom surface of the second side wall insulation films 18A and 18B. Upper and covering the surface of the crucible substrate 11. The extensions 19Aa and 19Ba are in contact with the source extension 20 region 11EA and the non-polar extension region Ueb, respectively. As described below, since the mixed crystal layers 19A and 19B are low-resistance CVD films including high-activity p-type impurities due to the extension portions 19 and 19, the stray resistance is largely lowered. As a result, the short path effect does not occur and the current driving ability of the modified channel M〇s transistor 1〇 is 0 19 1278115. The extending portions 19Aa and 19Ba are epitaxially grown on the germanium substrate 11 just below the extending portions i9Aa and 19Ba. In the experiments conducted by the present invention, the inventors of the present invention found that by the convergence electron diffraction and the deformation analysis of the corresponding high-order diffraction electron beam, a tensile stress is just in the gate length direction under the SiGe mixed crystal 5 layers 19A and 19B. It is applied to the stone substrate 11. Therefore, it is highly desirable that the extension portions 19Aa and 19Ba induce a tensile stress in the gate length direction of the crucible base material 11 just below the extension portions 19Aa and 19Ba. In this example, since the side surface 19b is fixed by the SiGe mixed crystal layers 19A and 19B, the extension portions of the Saxon SiGe mixed crystal layers 19A and 19B induce tensile deformation in the source extension ιιεα and the drain 10 extension 11EB. And the tensile deformation produces a stress in the passage region which is opposite to the crystal of the stone. As a result, in the p-channel MOS transistor 10 shown in Fig. 3, since the extension portions 19Aa and 19Ba which are in contact with the source extension region 11EA and the drain extension region 11EB, the hole mobility can be further increased. The extending portions 19Aa and 19Ba are formed to fill a space between the second side wall insulating films 18A 15 and 18B and the surface of the crucible substrate 11. Further, the SiGe mixed crystal layers 19A and 19B are continuously grown from the extending portions 19Aa and 19Ba on the outer surfaces of the second side wall insulating films 18A and 18B because of the extending portions 19Aa and 19Ba. Therefore, the SiGe mixed crystal layers 19A and 19B closely contact the second side wall insulating films 18A and 18B, and the extension portions 20 19Aa and 19Ba of the SiGe mixed crystal layers 19A and 19B cover the end portions of the first side wall insulating films 16A and 16B. . Therefore, the first side wall insulating films 16A and 16B are not invaded during the HF process in the step of forming a vapor film, and the chipping spears can be prevented from being formed in the crucible substrate 11. In particular, when nickel is used to form the telluride layer, it is difficult to induce nickel telluride on SiGe compared to the telluride reaction on Si. However, due to the extension portions 19Aa and 19Ba, it is possible to effectively prevent nickel from diffusing to the source extension region 11EA and the drain extension region 11EB. Therefore, direct contact between the secondary layer 20A and 20B and the n well 1 In can be prevented, and leakage current can be reduced. The extension portions 19Aa and 19Ba preferably have a distance from the via region and the gate insulating film 13 just above the via region. When the extensions i9Aa and 19Ba of the SiGe mixed crystal layers 19A and 19B are in close proximity to the via region and the gate insulating film 13 just above the via region, the Ge atoms in the SiGe mixed crystal layers 19A and 19B are in a heat treatment for subsequent processing. Diffusion in the via region, and perhaps 1 〇 will cause the dispersion of the path current. Further, the Ge atoms in the SiGe mixed crystal layers 19A and 19B can diffuse into the gate insulating film 13, and the reliability of the gate insulating film 13 can be lowered. The extension portions 19Aa and 19Ba can be appropriately determined in consideration of stray resistance, or stress amount value, protection for the first side wall insulating films 16 A and 16B during HF processing, and element deterioration due to diffusion of Ge atoms. The longitudinal length and the distance between the extending portions 19Aa and 19Ba and the gate insulating film 13.

The SiGe mixed crystal layers 19A and 19B are grown to be 5 nm to 40 nm higher than the interface between the ruthenium substrate and the gate electrode and the insulating film 13. Therefore, the compressive stress can be effectively induced. 20 When the telluride layers 20A and 20B are formed from nickel telluride, the tensile stress tends to counteract the compressive stress because the nickel telluride layer generally induces a compressive stress in the via. However, since the telluride layers 20A and 20B are formed on the SiGe mixed crystal layers 19A and 19B and at a position far above the interface between the germanium substrate and the gate insulating film 13, the germanium layers 20A and 20B are caused. The tensile force should be 21 1278115. The force cannot cancel the compressive stress induced in the passage zone. The gate electrode 14 preferably extends in the direction < ι 〇 〇 延伸 on the 矽 substrate 11, but the gate electrode 14 can also extend in the direction <1 〇〇>. In the 1) channel %08 transistor 1 所示 shown in Fig. 3, when the ruthenium substrate is 5 so-called (100) substrate, it can be noted that the hole is caused by the compressive stress applied to the via region. The mobility is enhanced, and the gate length direction on the crucible substrate 11 is along the <11〇> direction or <100> direction, especially when located in the <11〇> direction. Here, the <100> direction includes the [100] direction and the direction equivalent to the [100] direction in a diamond structure. For the same reason, the direction of <11〇> is also established. A method of manufacturing one of the semiconductor elements 10 in Fig. 3 will be described below with reference to Figs. 4A to 4C and Figs. 5A and 5B. 4A to 4C are cross-sectional views showing a portion of the semiconductor element 10 in Fig. 3, showing a method for fabricating the half 15 conductor element 10 according to one embodiment of the present invention. In the step shown in Fig. 4A, on the p-type germanium substrate η, the element region 11A is defined by the ST1-type component separation region 12; the n-type impurity is implanted in the device region 11Α, thus corresponding to the device The area 11Α is formed to form the η plastic Si well 11η. Next, in the step shown in FIG. 4, on the germanium substrate 11, corresponding to the 20 element region 11A, the gate insulating film 13 and the gate electrode 14 are uniformly formed on one of the SiON substrates 11 from SiON. The film and a polycrystalline film are patterned to form. Then, using the gate electrode 14 as a mask, sb or other n-type impurities are obliquely implanted into the element region 11A, thereby forming the capsule region 11pc as shown in Fig. 3. In the Fig. 4B and subsequent figures, the capsule region 1 lpc is not shown.

22 1278115. Then, the gate electrode 14 is used as a mask, boron (B) or other p-type shell implant component £11A, thereby forming a source extension 11 ea and a drain extension 11EB. Then, the first side walls 16A and 16B and the second side walls IgA and 18B are formed on the gate electrode 14. Further, boron (B) or other p-type impurities are implanted, and the p-type diffusion regions 11Sp and 11Dp are formed outside the first side wall insulating films 18 A and 18B in the element region UA of the tantalum substrate. Next, in the step shown in FIG. 4C, in the stone substrate, a part of the element region 11A located outside the second side wall insulating films 18A and 18B is etched to 60 nm by 10 dry etching. a depth. Due to this etching process, the channels 111A and 111B are formed in the element region defined by the side surface 19b which is nearly perpendicular to the main surface of the stone substrate η and the side surface 19c which is nearly parallel to the main surface of the ruthenium substrate 11. 11A. Figs. 5A and 5B are rib sectional views showing a portion of the semiconductor element 15 member 10 in Fig. 3 continued from Fig. 4C to show a method for manufacturing the semiconductor device 10 according to the present embodiment of the present invention. In the step shown in Fig. 5A, the portions of the first side wall insulating films 16A and 16B formed from the hafnium oxide film are removed by the isotropic residue, and the bottom surfaces of the second side wall insulating films 18A and 18B are removed. Below, the surface of the substrate is exposed to form a space 16A1 and 16B1 which is like a slit along the width of the gate. Here, in the isotropic etching, an aqueous solution of HF (e.g., HF concentration of 5 vol%) or HF vapor is used. Here, as long as the first side wall insulating films 16A and 16B can be selectively removed by isotropic etching, there is no limitation on the conditions for the isotropic touch 23 1278115. During the isotropic etching, the first sidewall insulating films 16A, 16B on the gate electrode 14 are also etched, and openings 16A2 and 16B2 are formed. The spaces 16A1 and 16B1 are preferably formed by isotropic etching, so that a large portion of the surface 5 of the germanium substrate n which can be formed by the source extension region 11EA and the drain extension region 11EB is exposed through the space spaces 16A1 and 16B1. The spaces 16A1 and 16B1 do not touch the gate insulating film η. For example, the first side wall insulating films 16A, 16B in the "Fig. 5A" may be formed in a sigmoid shape and cover the side surfaces of the gate electrode 14 and the gate insulating film 13. In the isotropic etching, the removal amount 10 of the first side wall insulating films 16A, 16B depends on the etching time or the HF concentration, and the isotropic etching does not allow the side of the gate electrode 14 and the gate insulating film 13 The surface is exposed. In the isotropic etching, the native oxide film on the channel is also removed. Next, in the step shown in FIG. 5B, the substrate on which the structure of 15 in the first drawing is formed is introduced - filled with helium, nitrogen or argon, nitrogen or other inert gas, and maintained at 5 to 133 MPa pressure in low pressure CVD components. Then, the temperature was increased to -4 〇5 Torr in the -hydrogen environment (after rc, the pressure was maintained in the range of 5 to 1330 Pa for 5 minutes to perform baking of the substrate in the hydrogen environment 20. The corpse then, at 4 〇〇 to 55 (TC substrate temperature and the partial pressure of gas, nitrogen, or gas, helium or other inert gas is in the range of 5 to 1330 Pa, to supply the following gas to a period of 40 knives 4) gas in the range of 1 to Pa range (as (four) gas phase material), in the qi to the job 24 1278115 circumference of tetrahydrogen hydride (GeH4) gas (as a gas phase material of Ge), in lxl 〇-5 to lxl〇-3 Pa range of diborane (Β#6) gas (as a dopant gas), and HC1 (hydrogen chloride) gas at a partial pressure of 1 to 10 Pa (as enhanced selectivity) In this case, the p-type SiGe mixed crystal layer 19Α and the 19Β system 5 doped crystals are grown in the channels 111A and 111B. At the same time, the extension portions 19 of the SiGe mixed crystal layers 19A and 19B are 18, 19Ba Formed in the spaces 16A1 and 16B1 below the bottom surface of the second side wall insulating films 18A, 18B, and the SiGe mixed crystal layers 19A and 19B grow up Closely contact the second sidewall insulation films 18A, 18B of the side surface.

10 Next, after the step of FIG. 5B, the surfaces of the SiGe mixed crystal layers 19A and 19B are converted into a vaporized layer. In particular, the surface of the structure in Figure 5B is treated with HF to remove the native oxide film on the surface. Then, for example, a nickel film is formed by sputtering to cover the structure in Fig. 5B. Then, an RTP (rapid thermal process) component is used to perform a heat treatment (at 4 〇〇 to 5 〇〇 15 ° C) to initiate the source region 19A, the drain region 19B, and the gate electrode 14

The SiGe mixed crystal layer 19C is reacted, for example, to form a nickel-lithium layer having a thickness of 20 nm (including germano.). Then, the unreacted nickel film is etched by wet etching using a mixture of ammonia and hydrogen peroxide (first treatment), and a mixture of sulfuric acid and hydrogen peroxide is further engraved by wet etching. Second treatment), thereby removing the untreated nickel film. One or more wet etch steps may be omitted as desired. Then, an RTP element is used for heat treatment at 400 to 500 ° C as needed. Here, if a nickel vapor film is not used, a Co, Ta, Ti or Pt telluride film can be formed. 25 1278115 In this manner, the p-channel MOS transistor 10 in FIG. 3 is fabricated. In the method of the present embodiment, since the SiGe mixed crystal layers 19A and 19B are formed by CVD using a p-type impurity as a dopant, the activation rate of the impurity is close to 1% by mass even without heat treatment. This ratio is higher than the activation rate of the implanted impurities in the ion implantation. Therefore, the SiGe mixed crystal layers 19A and 19B have low resistance, and the extension portions 19Aa and 19Ba are in contact with the source extension regions ιιεΑ and the drain extension regions 11EB, respectively, so that the stray resistance can be greatly reduced, and the p-channel M〇s transistor is greatly reduced. The current drive capability of 10 has been improved. In the step of forming a germanide layer to remove the native oxide film on the SiGe mixed 10 crystal layers 19A and 19B by the treatment using HF, the extension portions l9Aa and 19Ba of the SiGe mixed crystal layers 19A and 19B can be prevented from coming into contact with A side wall insulating film 16A and 16B; therefore, the first side wall insulating films 16a and 16B are not eroded, and the surface of the ruthenium substrate 11 is not exposed. Further, when the telluride layer is formed from the nickel telluride, it is difficult to initiate the reaction of the nickel on the nickel as compared with the telluride reaction of the nickel on the Si. Therefore, it is possible to prevent the shredder from being formed in the n-well 11n. In the step shown in Fig. 5B, the above-described treatment is not used, and in the initial stage of growth of the mixed crystal layers 19A and 19B, the partial pressure of tetrahydrogenated (GeH4) gas (as a gas phase material of Ge) must be set to be relatively Lower, and as the 20 SiGe mixed crystal layers 19A and 19B grow, the partial pressure of the tetrahydrogen hydride (Gefj4) gas can be successively increased. Thus, the difference in the interface between the tantalum substrate u and the siGe mixed crystal layers 19A and 19B can be prevented, and horizontal compression deformation can be effectively formed inside the siGe mixed crystal layers 19A and 19B. After the step shown in Fig. 5B, a p-type semiconductor layer mainly comprising Si may be deposited on the 8^ mixed crystal layers 19A and 19B before the step of forming a vaporized film. By deuterating one mainly includes 81? The type of semiconductor layer can prevent deterioration of the thermal resistance or type (m〇rph〇1〇gy) which is liable to occur in the deuteration process when the SiGe mixed crystal layers 19A and 19B have a high Ge concentration. 5 In detail, 'at the temperature equal to or lower than one of the SiGe mixed crystal layers 19A and 19B, a decane (siH4) gas having a partial pressure of 1 to ίοPa, and a χ1 (Γ4 to lxl (T2 Pa range) a diborane (B2H6) gas and a HC1 (hydrogen chloride) gas system having a partial pressure of 10 Pa are supplied together, and a p-type semiconductor layer having a thickness of less than 2 nm is formed in the SiGe mixed crystal layer 19A and 19B 10. Since the p-type semiconductor layer is provided in consideration of the subsequent step, the p-type semiconductor layer is preferably a p-type layer which can be easily formed by the lithotripsy, but the p-type semiconductor layer may include the SiGe layer. The Ge concentration in the mixed crystal layers 19A and 19B has a lower concentration of Ge. When the p-type semiconductor layer includes Ge, the p-type semiconductor layer has a length of 15 and a GeHe4 having a partial pressure of 〇_〇_4 Pa can be supplied. As described above, in the p-type MOS transistor 1 in Fig. 3, since the psSiGe mixed crystal layers 19A, 19B are epitaxially grown on the side of the via region, a uniaxial compressive stress is applied to the via. On the surface of the surface layer 1A of the mixed crystal layer 19A and the SiGe mixed crystal layer 丨9B The surface 20 i9b is nearly perpendicular to the main plane of the crucible substrate 11, and can effectively induce compressive stress in the via region. Further, since the SiGe mixed crystal layer 19A, 19B has contact with the source extension region 11EA and the non-polar extension region iieb The extensions i9Aa and 19Ba, it is expected that the extensions 19Aa and 19Ba can reduce the extension resistance, and the extensions 丨98 & and 丨9Β& 27 1278115 are just closed on the Shixi substrate below the extension service level (4) The tensile stress is applied in the longitudinal direction. Therefore, it is expected that a compressive stress is indirectly applied to the = road region, so that the compression applied to the passage region is further enhanced, and the σ fruit can improve the P-pass M〇S transistor. Current Driving Capability of 10. Fifth Embodiment FIG. 6 is a cross-sectional view showing an example of a semiconductor element 30 according to a second embodiment of the present invention. In the following description, the same number is assigned to the description of the previous embodiment. The same components are omitted, and the repeated description is omitted. 10 The semiconductor device 30 shown in Fig. 6 is a P-channel MOS transistor. The p-channel MOS transistor 3 is basically connected to the p-channel of the first embodiment. The M〇s transistor is the same, but the difference is that the side surface of the channel 1ua & 111b in the tantalum substrate is formed from a cross section along a Si (llll) plane. In the P via MOS transistor 30, the tantalum substrate Each of the channels 111A and 15 1UB in 11 includes a bottom surface 19c which is nearly parallel to the main plane of the stone substrate 11, and a 56 which is opposite to the bottom surface 19c. The angle is self-broken along the Si(11) plane. The side surface 19d formed by the face. The P-type SiGe mixed crystal layers 19A and 19B are epitaxially grown in the trenches 111a and 111B to fill the trenches iiiA and 111B, respectively. 20, as in the first embodiment, the SiGe mixed crystal layers 19A and 19B have extension portions 19Aa, 19Ba which cover the surface of the portion of the base material 11 where the source extension region ιιεα and the drain extension region 11EB are formed. The SiGe mixed crystal layers 19A and 19B are grown up along the outer surfaces of the second side wall insulating films 18A and 18B. 28 1278115 p-channel MOS transistor 30 has the same effect as the p-channel m〇s transistor in the first embodiment; moreover, in the P-channel MOS transistor 30, because of the section along the Si(llll) plane The source region iis and the bungee region iid, and the source extension region 1 EB and the bony extension region 11EB have an impurity concentration of 50 Å, and the SiGe mixed crystal layers 19A and 19B are formed adjacent to the via region and are disturbed at the same time. The impurity concentration profile. Therefore, the compressive stress can be induced more effectively in the passage region. Hereinafter, a method for manufacturing the semiconductor device 30 of Fig. 6 will be described with reference to Figs. 7A and 7B. 10A and 7B are cross-sectional views showing a portion of the semiconductor element 3A of Fig. 6, showing a method for fabricating the semiconductor element 30 according to a second embodiment of the present invention. In the steps shown in Fig. 7A, the processes shown in Figs. 4a to 4 and Fig. 5a are performed. In the structure manufactured so far, each of the channels H1A and 111B includes a bottom surface 19c and a side surface 19b which is nearly perpendicular to the bottom surface i9c; spaces 19A1 and 19B1 are formed under the bottom surfaces of the second side wall insulating films 18A and 18B and The surface of the substrate 11 is formed; and the openings 16A2 and 16B2 are formed beside the upper portion of the gate electrode 14. Further, in the step shown in Fig. 7A, the vertical side surface 19b is etched to a 56 with respect to the main plane of the crucible substrate 11. The angle forms a section in the Si (l 11) plane. In this etching process, wet etching is performed using an organic strong alkali etchant (e.g., tetramethylammonium hydroxide such as TMAH, choline) or ammonium hydroxide. Alternatively, at 80 (TC) in a hydrogen and HCl atmosphere by a heat treatment to etch 29 1278115 engraving process. The cross-section is formed such that the upper end of the side surface 19d does not touch the gate insulating film 13. Based on this use, the side surface 19d is formed as a line 19e from the bottom surface 19c and the vertical side surface 19b of the channels 111A and 111B extends upward and obliquely at an angle of 56° with respect to the bottom surface 5 19c. Therefore, in the step of FIG. 4C The position for forming the vertical side surface 19b is appropriately selected. The side surface 19d is located at a position surrounded by the source region 丨丨s and the drain region 1 id, and the source extension region 11EA and the drain extension region 11EB. The n-well 11n is penetrated. 10 Next, in the step shown in Fig. 7, the SiGe mixed crystal layers 19A and 19B are formed in the same manner as shown in Fig. 5B. Then, a deuteration step is performed as described above. The p-channel transistor 30 in Fig. 6 is fabricated. In the method of this embodiment, the SiGe mixed crystal layers 19A and 19B fill the 15 channel 111 and 1118, forming the extensions 19 && 198 & The SiGe mixed crystal layers 19A and 19B which grow up are closely The outer surfaces of the second side wall insulating films 18A and 18B are touched. Therefore, it is possible to prevent the exposure of the surface of the crucible substrate 11 during the deuteration step processing, and it is possible to prevent the spear formation spears from being formed in the n-well 11n in the stone etching step. Moreover, when the telluride layer is formed of nickel, it is difficult to initiate the nickel compound reaction on the SiGe compared to the germanium telluride reaction on the Si, so that the telluride spear in the n-well lln can be effectively prevented. Third Embodiment Fig. 8 is a cross-sectional view showing an example of a semiconductor element 40 according to a third embodiment of the present invention. 30 1278115' In the following description, the same number is assigned to the same as described in the previous embodiment. The components are omitted, and the semiconductor element 40 shown in Fig. 8 is a p-channel MOS transistor. The P-channel MOS transistor 40 is basically the same as the p-channel M〇s of the first embodiment. The crystals 10 are the same, but differ in that one side surface 19d and one side surface 19f of the channels 111A and 111B in the crucible substrate 11 are formed from the Si(m) planes in different orientations. P-channel MOS transistor 4 In the crucible, each groove in the substrate 11 111A and Π1Β comprise a bottom surface 19c, and 10 which are nearly parallel to the main plane of the 矽 substrate η, with a 56 with respect to the bottom surface 19c. The side surface 19d which is formed from the section and extends inwardly, and a relative side The bottom surface 19c has a side surface 19f formed by a section from a Si(iii) plane at an angle of 124. The side surface 19f extends inwardly from the surface of the base material u, and is also a base material n and The interface between the gate insulating films 13. The side surface 19d and the side surface 19f intersect to form an inwardly facing wedge shape. The P-type SiGe mixed crystal layers 19A and 19B are epitaxially grown in the channels lnA and 111B to fill the channels 11 ία and 111B, respectively. Similarly to the first embodiment, the SiGe mixed crystal layers 19A and 19B have extension portions 19Aa, i9Ba, 20 which cover the surface of the portion of the tantalum substrate 11 where the source extension region 11EA and the electrode extension region iieb are formed. The SiGe mixed crystal layers 19A and 19B are in contact with the bottom surfaces of the sidewall insulating films 18A and 18B, and are grown up along the outer surfaces of the second sidewall insulating films 18A and 18B. In the SiGe mixed crystal layers l9A and 19B, a front end 19g which is a wedge shape which is a line of intersection of the side surface 19d and the side surface 19f of the side 31 1278115 is formed at a position inside one of the outer surfaces of the second side wall insulating film 18A or 18B. While the SiGe is mixed, the SiS layers 19A and 19B are close to the via region just below the gate electrode 14. However, the tapered front end 19g is formed so as not to penetrate from the source region us and the drain region 11D 5 to the inside of the n-well 11n; therefore, the interval between the SiGe mixed crystal layers 19A and 19B is smaller than in the previous embodiment. The p-channel MOS transistor 40 has the same effect as the p-channel M 〇s transistor 10 in the first embodiment; further, in the p-channel MOS transistor 40, a p-channel MOS transistor 10 can be induced in the via region. And 30 more strong pressure 10 shrinkage stress. Therefore, it is possible to further increase the hole mobility and improve the current drive capability of the p-channel MOS transistor 40. Hereinafter, a method for manufacturing the semiconductor device 40 of Fig. 8 will be described with reference to Figs. 9A to 9C. 9A to 9C are cross-sectional views showing a portion of the semiconductor element 40 in Fig. 8, which shows a method for fabricating the semiconductor element 40 according to a third embodiment of the present invention. In the step shown in Fig. 9A, the processes shown in Figs. 4A to 4C in the first embodiment are performed. In the structure manufactured so far, in the element regions of the outer side 20 of the second side wall insulating films 18A and 18B, the respective channels 111A and 111B include a bottom surface 19c and a side surface 19b which is almost perpendicular to the bottom surface 19c. At this stage, the intersection position between the side surface 19b and the bottom surface 19c of the channels 111A and 111B is defined, and the positions of the end points 19h of the first side wall insulating films 16A and 16B are defined. Because these locations define the break in the two different Si(111) planes formed in the next step.

32. The smear-side side surface 19b and the bottom surface 19c are formed so as to form a desired side surface in the next step. It should be noted that the side surface 19b does not need to be perpendicular to the bottom surface 19c; therefore, the starting position of the section in the Si(ul) plane can be extracted from the boundary. In the step shown in Fig. 9A, the vertical side surface 19b is etched to form a side surface 19d and a side surface 19f which are formed from two cross sections. As in the step of Fig. 7A, in the etching process, an organic strong alkali etchant (譬, aerobic tetramethylammonium such as TMAH, a test) or a hydrogen peroxide is used for two cycles. Alternatively, the etching process may be performed by a heat treatment in (10) in a hydrogen gas atmosphere. As a result, the side surface 19d and the side surface 19 are formed from the fracture surface in the Si (ll) plane, but the side surface 19d is made at a % with respect to the main surface of the crucible substrate u. angle

The Si (lll) plane is formed from a cross section, and the side surface is 124 with respect to the main surface of the stone substrate 11. The angle is formed from a section in a si (111) plane. Since the side surface 19d is formed from a section in the Si (111) plane, once the position of the intersection 19e of the bottom surface 19c and the vertical side surface 19b (refer to the fourth (:) is bounded, the side surface 19d can be controlled. On the other hand, since the side surface 19f is also formed from a section in the Si (111) plane, once the position of the end point 19h of the first side wall insulating films 16A and 16B is defined, the side surface 19f can be controlled. Therefore, the front end 19g of the side surface 19d and the side surface 19f is formed in a controlled manner, and the front end 19g of the wedge shape can be prevented from penetrating from the source region 11S and the drain region 11D. To the inside of the η well l〇n, and to prevent disturbing the impurity profile of 1278115. Next, in the step shown in Fig. 9B, the positions of the first sidewall insulating films 16A, 16B are in the same manner as shown in Fig. 5B by The etch is removed. 5 Next, in the step shown in Fig. 9C, the SiGe mixed crystal layers 19A and 19B are formed in the same manner as shown in Fig. 5B. The siGe mixed crystal layers 19A and 19B are filled in the trenches, respectively. Lanes 111A and 111B, at the same time utilizing the first embodiment The same manner nearly fills the space between the bottom surface of the second side wall insulating films 18A, 18B and the surface of the ruthenium substrate 11 by 16 people 1 and 16B1, and grows along the outer surfaces of the 10 second side wall insulating films 18A and 18B. Then, the vaporized layers 2a to 20C are formed in the same manner as described above. In this manner, the p-channel transistor 4 of Fig. 8 is fabricated in the method of the present embodiment because the bottom surface 19c and the vertical are included. The channels ι 11 Β and 111 侧 of the side surface 19b are formed to define an initiation position of the etch, and 15 is etched to selectively expose the Si(m) plane, and the side surface of the protrusion-shaped wedge facing inward may be controlled in a controlled manner Therefore, the short path effect can be prevented while the compressive stress is increased; therefore, the hole mobility in the via region can be increased and the current driving activity of the P via MOS transistor 40 can be improved. Fourth Embodiment 20 FIG. 10 is a view A cross-sectional view of an example of a semiconductor device 50 according to a fourth embodiment of the present invention. In the following description, the same reference numerals are assigned to the same components as those described in the previous embodiment, and the repeated description is omitted. The semiconductor device 50 shown in Fig. 10 is a body of a -p via M 〇s transistor 34 1278115. The P via MOS transistor 50 is substantially the same as the p via MOS transistor 10 of the first embodiment 'but the difference is that - the component The structure of the separation region is different. In the P-channel MOS transistor 50, a component separation region 52 includes an HF resistance film 52C formed on a surface of a component isolation trench 112, covering the HF resistance film 52C. And filling the cvd oxide film 52B of the part isolation trench 丨丨2, and the % of the resistive film covering the CVD oxide film 5邡. • The HF resistance films 52C and 55 may be SiN films, SiOCN films, or SiCN films. In particular, it prefers to use a SiOCN film or a 10 SiCN film because of its superior resistance to HF. In the component separation region 52, since the HF resistance films 52C and 55 cover the entire CVD oxide film 52B for removing a native oxide film, it is possible to prevent the ruthenium substrate 丨1 from being removed by repeated execution. The immersion of the component separation zone caused by HF treatment of one of the primary oxide films. As described in the method of manufacturing a semiconductor element in the previous embodiment, portions of the first side insulating film 16A, 16B are removed by HF treatment, and HF treatment may be excessive in this process. In the present embodiment, the intrusion of the component separation region 52 can be prevented in the p-channel MOS transistor 50 even when the HF treatment is excessive. Therefore, it is possible to prevent the telluride layer of the source or the drain from contacting the n well 1 in the substrate 11 20 and prevent the junction from leaking. Hereinafter, a method for manufacturing the semiconductor device 50 of Fig. 10 will be described with reference to Figs. 11A to 11C, 12A to 12 and 13. 11A to 11C are cross-sectional views showing a portion of the semiconductor element 50 in Fig. 10, showing a method for fabricating the semiconductor device 50 of 35 1278115 according to a fourth embodiment of the present invention. Here, it is assumed that the HF resistance films 52C and 55 are SiOCN films or SiCN films. In the step shown in Fig. 11A, on the tantalum substrate 11, a sacrificial oxide film 53 is formed to a thickness of 10 nm, and then a SiN film is bonded at a substrate temperature of 775 ° C by thermal CVD on the sacrificial oxide film. 53 is formed to a thickness of 105 nm.

The SiN film 54 is patterned. By using the obtained SiN pattern 54 as a mask, a component separation trench 112 is formed in the germanium substrate 11 to define the element region 11A. Next, in the step shown in Fig. 11B, a thermal oxide film 52A is formed to a thickness of 3 nm on the side surface and the bottom surface of the component separation trench 112. 10 Then, as one of the HF resistive films 52C, the SiOCN film or the SiCN film is formed by using LTBAS (bis(T-Butylamino)) as a raw material by lpcvD (low pressure CVD) to a thickness of 20 nm. The element isolation trench η is a thermal oxide film 52A on the side surface and the bottom surface. The chemical formula of BTBAS is as follows:

SiH2[NH(C4H9)]2 Η H CH3 H — Si—N — C—CHq I I 6 N—H CH 3 H 3 C — C — CH 3 ch 3 15 In LPCVD, a reaction as expressed in the following reaction formula occurs. SiH2[NH(C4H9)]2 + 〇2 ^ SiOxCyNz or

SiH2[NH(C4H9)]2 + N20 + SiOxCyNz and forms one Si0CN film described by SiOxCyNz. The SiOCN film obtained in this manner obtained by 36 20 1278115 includes c having a higher concentration than the dopant concentration.譬 For example, according to the analysis results of the obtained SiOCN film, it was found that the ratio of Si, 〇, N and C in the obtained SiOCN film was 2:2:2:1. If ammonia is used in place of 〇2 or N20 in the above reaction, the following reaction occurs.

SiH2[NH(C4H9)]2 + NH3 SiCxNy and forms a siCN film of SiCxN3^g. Further, in the step shown in Fig. 11B, the CVD oxide film 52B is deposited on the HF resistance film 52C by the high-density plasma cvD to fill the element 10 from the trench 112. Then, the CVD oxide film 52B deposited on the SiN pattern 54 is polished and removed by CMP (Chemical Mechanical Polishing); therefore, the height of the cvd oxide film 52B is the same as that of the SiN pattern 54. Next, in the step shown in Fig. 11C, the CVD oxide film 52B is subjected to HF treatment, that is, the CVD oxide film 52B is etched by wet etching for 15 times with HF, and as a result, the CVD oxide film 52B is lowered by 80 nm to 12 〇 nano. 12A to 12C are cross-sectional views showing a portion of the semiconductor element 50 in the first drawing from the 11th CC, showing a method for fabricating the semiconductor device 50 according to the embodiment of the present invention. Then, in the step shown in FIG. 12A, 'BTBS (bis(T-Butylamino) second burn) is used as a raw material on the structure 20 shown in the figure "He" as a raw material, and is deposited as an HF resistive film 55 by lpcvd. A SiOCN film or film. The HF resistance film 55 is deposited to a thickness one of the same height as the surface of the stone substrate 11. In the step shown in Figure 12B, by high-density plasma cvd,

37 1278115 A niobium monoxide film is deposited in the structure shown in Figure 12A. Then, the ruthenium oxide film is polished and removed by CMP, and therefore, the ruthenium oxide film pattern 56 is formed on the HF resistance film 55 corresponding to the part separation trench 112. Next, in the step shown in FIG. 12C, by using the yttrium oxide film pattern %5 as a mask, the HF resistance film 55 and the SiN pattern 54 under the HF resistance film 55 are dissolved and moved by the thermal phosphate treatment. except. Then, the hafnium oxide film 56 is removed by wet etching using HF. Here, since the si〇CN film or the SiCN film is soluble in the hot phosphate and has a silver engraving speed similar to or slightly lower than SiN, in the thermal acid salt treatment, even when the siN pattern is removed 10, Prior to this, the HF resistance films 52C and 55 are removed in the component separation trench 112, so that the CVD oxide film 52B is not exposed at all. Further, a part of the HF resistance film 55 may be protruded after the thermal sulphate treatment to form a projection 55a. In this example, the iiF resistive film 55 can be flattened by CMP. In this manner, the component isolation region 52 is formed in which the CVD oxide film 52B 15 is entirely covered by the HF resistance films 52C and 55. Figure 13 is a cross-sectional view showing a portion of the semiconductor device 50 continued from Fig. 12C, showing a method for fabricating the semiconductor device 50 in accordance with the present embodiment of the present invention. Next, in the step shown in Fig. 13, in the element region 20 11A shown in Fig. 12C, the fourth embodiment shown in Figs. 4A to 4C and Fig. 5A in the first embodiment are performed.

Process. That is, the n-type impurity is implanted into the element region 11A (FIG. 4A); the gate insulating film 13, the gate electrode 14, the source extension region 11EA, the drain extension region 11EB, the first sidewalls 16A and 16B, Second sidewall insulating films 18A and 18B (Fig. 4B); channels 111A and 111B are formed in the element region 11A (Fig. 4C 38 1278115); and portions of the first sidewall insulating films 16A, 16B formed from the hafnium oxide film The space is removed by isotropic etching, and the spaces 16A1 and 16B1 are formed by exposing the surface of the tantalum substrate 11 located below the bottom surface of the second side wall insulating films 18A and 18B. 5 After the step of Fig. 13, a telluride layer is formed as shown in Fig. 5B. In this manner, the p-channel M〇S transistor 50 in Fig. 10 is fabricated. In the method of the present embodiment, in the step shown in Fig. 13, since the portions of the first side wall insulating films 16A, 16B are removed, even when the HF treatment is excessive, 'because the integral part separation region 52 is HF resistance film The 52C and 55 covers 10 covers' to prevent dissolution by HF; therefore, corrosion of the component separation region 52 can be prevented, and junction leakage can be prevented. [Fifth Embodiment] Fig. 1 is a cross-sectional view showing an example of a semiconductor element 60 according to a fifth embodiment of the present invention. 15 The semiconductor element 6 所示 shown in FIG. 14 which is a via MOS transistor is basically the same as the ρ path M 〇 transistor 3 〇 in FIG. 6 of the second embodiment, but the difference lies in the component separation region. The 12 series is replaced by the component separation zone 52 of Fig. 13. By this, the p-channel MOS transistor 60 has the same effect as the p-channel MOS transistor 50 in the tenth diagram of the fourth embodiment. Sixth Embodiment Fig. 15 is a cross-sectional view showing an example of a semiconductor element 65 according to a sixth embodiment of the present invention. The semiconductor element 65 shown in Fig. 15 which is a p-channel MOS transistor is basically the same as the P-channel MOS transistor 40 of the eighth embodiment of the third embodiment.

39 1278115 Same as 'but the difference is that the component separation zone 12 is replaced by the component separation zone 52 of Fig. 13. By this, the P-channel MOS transistor 65 has the same effect as the P-channel MOS transistor 50 in the tenth diagram of the fourth embodiment. Seventh Embodiment 5 Fig. 16 is a cross-sectional view showing an example of a semiconductor element 70 according to a seventh embodiment of the present invention. In the following description, the same reference numerals are assigned to the same components as those described in the previous embodiment, and the repeated description is omitted. The semiconductor device 70 shown in Fig. 16 is an n-channel M〇s electro-crystal 1 body. In the n-channel MOS transistor 70, the SiGe mixed crystal layer 丨9 and 丨9Β in the NMOS via transistor MOS transistor 30 in the third embodiment of the second embodiment are not used, and the SiC mixed crystal layers 71A and 71B are used. A tensile stress is induced in the passage zone. Further, the impurity introduced into the n-channel MOS transistor 70 has a conductivity type opposite to the impurity introduced into the via MOS transistor 30 of FIG. 3, that is, the SiC mixed crystal layer 71 and the 71-lanthanum include n-type impurities. . Further, in the n-channel MOS transistor 70, the p-type impurity is implanted in the element region 11A, the cap portion 11pc, and a Si well region, and the n-type impurity is introduced into the source extension region UEA and the drain extension region 11A. , the source region llSn and the drain region UDn. Except for the above points, the n-channel MOS transistor 70 is basically the same as the p-channel MOS transistor 30 of the third embodiment of the second embodiment. In the crucible substrate 11, the channels 111A and 111B are formed outside the second sidewall insulating films 18A and 18B, respectively. The Sic mixed crystal layers 71A and 71B including n-type impurities are grown in the channels 111 A and 111B to fill the trenches 40 1278115. 111 8 and 1113, respectively. The epitaxial growth is on the tantalum substrate 11 (:: the mixed crystal layers 71 and 71B have a structure constant smaller than that of the tantalum substrate, as described above with reference to the i-th diagram, resulting in an arrow "a", "b,,,", c,,, %,, the opposite stress. As a result, a uniaxial tensile stress is applied to the via region just below the gate electrode 14 of the tantalum substrate n. Due to tensile stress Therefore, the electron mobility is increased in the via region, and the current driving capability of the n-communication MOS transistor 70 is improved. Like the SiGe mixed crystal layers 19Α and 19Β in Fig. 3, the SiC mixed crystal layers 71A and 71B have an extension. The portions 71Aa and 71Ba, the extension portion 71 and the 71Ba are formed on the first side wall insulating films 16A and 16B which are located below the bottom surface of the second side wall insulating films 18A and 18B and cover the surface of the base material 11 and cover the first side wall insulating films 16A and 16B. On the side, the extensions 71Aa and 7iBa are in contact with the source extension iiEA and the non-polar extension 11EB, respectively. As described below, the sic mixed crystal layers 71A and 71B are highly active due to the extensions 71 Aa and 71 Ba. The low-resistance CVD film of the n-type impurity can greatly reduce the stray resistance. As a result, no The short path 15 effect is generated, and the current driving capability of the η path M〇S transistor 70 is improved. Further, it is expected that the extension portions 71Aa and 71Ba are just below the extension portions 71Aa and 71Ba at the gate length of the stone substrate 丨丨A compressive stress is induced in the direction. In this example, 'because the side surface 19b is fixed by the SiC mixed crystal layers 71A and 71B', the extension portions 71Aa and 71Ba of the salt crystal layer 71A and 71B are in the source extension region. In the 11EA and the buckle extension 11EB, compression deformation is induced, and the pressure and % shape generate relative tensile stress in the channel region in the stone substrate. As a result, the η-channel MOS transistor 70 shown in Fig. 16 is because The electron mobility can be further increased by the extension portions 71Aa & 71Ba which are in contact with the source extension region ΠΕΑ and the electrode extension region 11ΕΒ. 1278115 Because of the good crystallinity of the SiC mixed crystal layers 71A and 71B, the C atom concentration is preferably SiC. 0.1 atom% to 2.0 atom% of the mixed crystal layers 71A and 71B. For example, the n-type impurity in the SiC mixed crystal layers 71A and 71B is P (phosphorus) or As (珅), and the n-type impurity concentration is from lxl〇. I9 centimeters _3 to 1χ1〇2〇2 centimeters.

5 For example, the SiC mixed crystal layers 71 and 71 can be formed using a low pressure CVD element. This method is described below. The processes shown in Figs. 4A to 4C and Fig. 5 in the first embodiment are performed. The substrate on which the channels 111A and 1UB are formed is introduced into a low-pressure CVD element, and the low-pressure CVD element is filled with helium, nitrogen, argon, helium gas, or other inert gas, and is maintained at 5 Pressure to 1330 Pa. Then, the temperature is increased to 4 to 55 in a hydrogen atmosphere (after TC, the pressure is maintained at 5 to 1330 Pa for 5 minutes to perform baking of the substrate in a hydrogen atmosphere. Then, at 400 to 550 The substrate temperature of °C, and the partial pressure of 15 hydrogen, nitrogen, argon, helium, or other inert gas in the range of 5 to 1330 Pa, the following gases are supplied in a period of 1 to 40 minutes, that is, 1 to 40 Torr. Partially divided decane (S1H4) gas (as a gas phase material of ruthenium), (10) 曱 to 丨 范围 范围 之 之 Si Si Si Si Si Si Si Si Si Si 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 ΐχΐ〇 Hydrogenated phosphorus (PH3) (as a dopant gas) to a pressure range of ιχι〇_2, and HCK gas (by a pressure of 20) in a range of (7) Pa (as a precursor to enhance selectivity). Therefore, the n-type SiC mixed crystal layers 71A and 71B are epitaxially grown in the channels 111A and 111B. As a result, the SiC mixed crystal layers 71A and 71B are also grown in the space below the bottom surface of the sidewall insulating films 18A and 18B to form the extending portions 71Aa and 71Ba of the Sic mixed crystal layers 71A and 71B. Further, the dry blend 42 1278115 and the crystal layers 71A and 71B are grown upward until they closely contact the side surfaces of the second sidewall insulating films 18A, 18B. In the n-channel MOS transistor 70 of the present embodiment, the side surface shape of the NMOS substrate 11 filled with the SiC mixed crystal layer 71A and the 71 Β channel 111 Α and 111 系 is the same as that of the p-channel MOS transistor. Eighth Embodiment Fig. 17 is a cross-sectional view showing an example of a semiconductor element in accordance with an eighth embodiment of the present invention. In the present embodiment, the same reference numerals are assigned to the same components as those described in the previous embodiment, and the repeated description is omitted. The semiconductor element 75 shown in Fig. 17 is an n-channel MOS transistor. In the η via MOS transistor 75, the side surfaces 19d of the SiC mixed crystal layers 71 and 71 are the same as those of Fig. 6 in the second embodiment. In the n-channel MOS transistor 75, the same effect can be obtained except that the stress is opposite to that of the second embodiment, and this further improves the current driving capability of the η-channel MOS transistor 75. Ninth Embodiment Fig. 18 is a cross-sectional view showing an example of a semiconductor element in accordance with a ninth embodiment of the present invention. In the present embodiment, the same reference numerals are assigned to the same components as those described in the previous embodiment, and the repeated description is omitted. The semiconductor device 80 shown in Fig. 18 is an n-channel MOS transistor. In the η via MOS transistor 80, the side surfaces 19d and 19f of the SiC mixed crystal layer 71A and 71A are the same as those shown in Fig. 8 of the third embodiment. 43 1278115 η-channel MOS transistor, the same effect can be obtained except that the stress is opposite to that in the third embodiment, and this further improves the current driving capability of the η-channel MOS transistor 80. Tenth Embodiment Fig. 19 is a cross-sectional view showing an example of a semiconductor element in accordance with a tenth embodiment of the present invention.

In the present embodiment, the same reference numerals are assigned to the same components as those described in the previous embodiment, and repeated plug-ins are omitted. The semiconductor element 85 shown in FIG. 19 is an n-channel m〇s electro-crystal H) body which is incorporated into the n-channel MOS transistor of the seventh embodiment by the component isolation region 52 shown in FIG. Obtained in the middle. In the component separation region 52 of the η-channel electroencephalograph 85, since the hf-resistance films 52C and 55 cover the entire cvd oxide film 52B' for removing the original gas-up film, it is prevented from being used for removing the first wall insulation. The portion of mi6a, i6b 15 or used to remove the native oxide film on the stone substrate U performs the erosion of the component separation region 52 caused by one of the HF treatments. As a result, it is possible to prevent the telluride layer of the source or the drain from coming into contact with the 11 well 1111 in the crucible substrate 11, and to prevent the junction bubble. Eleventh Embodiment Fig. 20 is a cross-sectional view showing an example of a semiconductor element according to a first embodiment of the present invention. In the present embodiment, the same reference numerals are assigned to the same components as those described in the previous embodiment, and the repeated description is omitted. The semiconductor device 90 shown in FIG. 20 is an n-channel m〇S transistor 44 1278115 body which is incorporated into the n-channel MOS transistor of the eighth embodiment by the component isolation region 52 shown in FIG. And get. The n-channel MOS transistor 9A has the same effect as the n-channel MOS transistor 85. [Twelfth Embodiment] Fig. 21 is a cross-sectional view showing an example of a semiconductor element according to a twelfth embodiment of the present invention. • The semiconductor element 95 shown in FIG. 21 is an n-channel M〇s transistor which is incorporated into the n-channel MOS transistor of the ninth embodiment 10 by incorporating the component isolation region 52 shown in FIG. obtain. The η via MOS transistor 95 has the same effect as the η via m 〇 S transistors 85 and 90. Although the present invention has been described above with reference to the specific embodiments of the present invention, it is understood that the invention is not limited to the embodiments, but many modifications may be made thereto without departing from the spirit and scope of the invention. [Fig. 1 is a cross-sectional view of a ρ-channel M〇s transistor containing a compressive stress; Figure 2 is a reference of the reference 2) FIG. 3 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment of the present invention; and FIGS. 4A to 4C are cross-sectional views showing a portion of the semiconductor device 1 in FIG. To show a method for fabricating a semiconducting 45 1278115 body element ίο according to one embodiment of the present invention; FIGS. 5A and 5B are cross-sectional views showing a portion of the semiconductor element 10 of FIG. 3 continuing from FIG. 4C. To illustrate a method for fabricating a semiconductor device 10 of the present embodiment of the present invention; FIG. 6 is a cross-sectional view showing an example of a semiconductor device 30 according to a second embodiment of the present invention; FIGS. 7A and 7B are diagrams showing A cross-sectional view of a portion of the semiconductor device 30 in Fig. 6 to show a method for fabricating a semiconducting beta body element 30 in accordance with one of the second embodiments of the present invention; 10 Fig. 8 is a view showing a third embodiment of the present invention An example of a semiconductor component 40 Cross-sectional view; FIGS. 9 to 9C are cross-sectional views showing a portion of the semiconductor element 40 in FIG. 8 to show a method for fabricating the semiconductor device 40 according to a third embodiment of the present invention; 15 FIG. 10 is a view showing A cross-sectional view of an example of a semiconductor device I 50 according to a fourth embodiment of the present invention; and FIGS. 11A to 11C are cross-sectional views showing a portion of the semiconductor device 50 in FIG. 10 to show one of the fourth embodiments according to the present invention. A method for fabricating the semiconductor device 50; 20 FIGS. 12A to 12C are cross-sectional views showing a portion of the semiconductor device 50 in FIG. 10 continued from the 11th CC to show the semiconductor device 50 used in the present embodiment of the present invention. Figure 13 is a cross-sectional view showing a portion of the display semiconductor device 50 from the continuation of the 12C to show a method for fabricating the semiconductor component 50 of the semiconductor 46 1278115 according to the present embodiment of the present invention; An example cross-sectional view of a semiconductor device 60 according to a fifth embodiment of the present invention; FIG. 15 is a view showing a semiconductor device 5 65 according to a sixth embodiment of the present invention. FIG. 16 is a cross-sectional view showing an example of a semiconductor device 70 according to a seventh embodiment of the present invention. FIG. 17 is a cross-sectional view showing an example of a semiconductor device according to an eighth embodiment of the present invention. FIG. 18 is a cross-sectional view showing an example of a semiconductor device according to a ninth embodiment of the present invention; and FIG. 19 is a cross-sectional view showing an example of a semiconductor device according to a tenth embodiment of the present invention; 20 is a cross-sectional view showing an example of a semiconductor element 15 according to an eleventh embodiment of the present invention; and FIG. 21 is a cross-sectional view showing an example of a semiconductor element according to a twelfth embodiment of the present invention. [Description of main component symbols] 11EB, 101B···汲polar extension 11η··.η type Si well llpc...n type capsule implantation area 11S,101S...source area llSp,llDp... P-type diffusion region 12, 52... component separation region 10, 30, 40, 50, 60, 65, 70, 75, 80, 85, 90, 95... semiconductor device 11, 101... Shixi substrate 11A.. .Component area 11D,101D...bath area 11EA,101A...source extension 47 1278115

13,102...Threshold insulating film 14,103...The idle electrode 16A, 16B···The first sidewall insulating film 16A1, 16B1...the space 16Α2,16Β2·"The opening 18Α, 18Β...the second sidewall insulating film 19A,19B , 19C, 105A, 105B...SiGe mixed crystal layer 19 Aa,19Ba,71 Aa,71 Ba···Extension 19A···Source region (Fig.5B) 19B···No-polar region (Fig. 5B) 19b, 19d, 19f... side surface 19c... bottom surface 19e... intersection line 19g... wedge-shaped front end 19h·. end point of the first side wall insulating film 20A, 20B, 20C, 106 · · · 夕 夕 层 52 A... Thermal oxide film 52B ... CVD oxide film 52C, 55 ... HF impedance film 53 ... Sacrificial oxide film 54 ... SiN film, SiN pattern 55a ... protrusion 56 ... oxidation矽 film pattern 71A, 71B... SiC mixed crystal layer 100··_ρ via MOS transistor 104A, 104B··· sidewall insulating film 105Aa, 105Ba, 111A, 111B ... channel 112... component separation trench a, b, c,d···arrow L...Southern 48

Claims (1)

1278115 X. Patent application: 1. A semiconductor component comprising: a stone substrate having a via region; a gate electrode corresponding to the via region formed on the financial substrate with a gate therebetween a first sidewall insulating film formed on a sidewall of the gate electrode; a second sidewall insulating film formed on a side surface of the first sidewall; a source extension region and a drain extension a region formed from a diffusion region having a predetermined conductivity type, the diffusion regions being formed in the germanium substrate on a side of the gate electrode to embed the via region; a source region and a drain region Forming a diffusion region having the predetermined conductivity type, the diffusion regions being formed in the outer substrate of the second sidewall insulating film and contacting the source extension region and the drain extension region, respectively, and the semiconductor a crystal layer formed on the outer side of the sidewall insulating film and epitaxially grown on the germanium substrate; wherein the semiconductor mixed crystal layer is when the predetermined conductivity type is p-type Self-SiGe mixed junction Forming, or forming from a SiC mixed crystal when the predetermined conductivity type is n-type, the semiconductor mixed crystal layer includes an impurity having the predetermined conductivity type, 49 1278115, the semiconductor mixed crystal layer is grown to the germanium substrate And a height of an interface between the gate insulating film and the semiconductor mixed crystal layer having an extension between a bottom surface of the second sidewall insulating film and a surface of the germanium substrate, the extension The portion 5 contacts a portion of the source extension and one of the drain extensions. 2. The semiconductor device of claim 1, wherein the germanium substrate has a (100) plane as a main plane; and the gate electrode is approximately in a <110> direction or approximately at a <100> The method extends over the tantalum substrate. 10. The semiconductor device of claim 1, wherein the semiconductor mixed crystal layer is formed to contact an outer surface of the second sidewall insulating film. 4. The semiconductor device of claim 1, wherein the side surface of the semiconductor mixed crystal layer comprises a cross section at a predetermined angle with respect to a major plane of the base material. 15. The semiconductor component of claim 4, wherein the cross-section comprises a cross-section extending in a direction perpendicular to a major plane of the crucible substrate. 6. The semiconductor device of claim 4, wherein the sections are formed such that a distance 20 between side surfaces of the two semiconductor mixed crystal layers is reduced in a predetermined direction. 7. The semiconductor component of claim 4, wherein the sections comprise an upper section and a lower section, the lower sections being formed such that a distance between side surfaces of the two semiconductor mixed crystal layers is obtained Decreasing in a predetermined direction, and 50 1278115, the upper sections are formed such that a distance between side surfaces of the two semiconductor mixed crystal layers is increased in a predetermined direction. 8. The semiconductor component of claim 4, wherein the sections are formed from a flat plane. 5. The semiconductor component of claim 8, wherein the sections are formed from a crystalline plane. 10. The semiconductor device of claim 1, wherein the first sidewall insulating film and the second sidewall insulating film are formed of an insulating material having different etching selectivity. 10. The semiconductor device of claim 1, further comprising: a component separation region on the crucible substrate to define a component region; wherein the component separation region includes a separation region covering the integral component HF (hydrofluoric acid) impedance film. 12. The semiconductor component of claim 1, wherein the semiconductor component is a p-channel transistor, wherein the predetermined conductivity type is a p-type, and the semiconductor mixed crystal layer comprises a p-type impurity. A SiGe mixed crystal layer is formed, and a Ge concentration in the SiGe mixed crystal layer is less than 40 atom%. 13. The semiconductor device of claim 12, wherein the SiGe mixed crystal layer comprises a B impurity, and a concentration of B in the SiGe mixed crystal layer is between lxl and 19 cm to 1 x 1 〇 21 cm _3. In the scope. 14. A method for fabricating a semiconductor component comprising a semiconductor hybrid crystalline layer on a side of a via region to induce a stress in the via region, the method comprising the steps of: 51 1278115. Forming a gate insulation Membrane on the germanium substrate; forming a gate electrode on the germanium substrate with the gate insulating film corresponding to the via region; forming a first diffusion region on each side of the gate electrode The 5 矽 substrate has a predetermined conductivity type; a first sidewall insulating film is formed on the gate electrode and sidewalls of the gate insulating film, and a portion of the first sidewall insulating film extends on the ruthenium substrate Forming a second sidewall insulating film on the side 10 surface of the first sidewall insulating film; forming a second diffusion region in the germanium substrate outside the second sidewall insulating film and having the predetermined conductivity type, the first The second diffusion region forms a source region and a region and a polar region, and the channel is formed by etching the channel region corresponding to the source region and the drain region in the germanium substrate to make the side surfaces of the channels And the bottom surface is the same The two diffusion regions are continuously covered, the channels have a side surface defined by the cross section; a portion of the first sidewall insulating film is removed; the semiconductor mixed crystal layer is grown by epitaxial growth to fill 20 of the trenches The semiconductor mixed crystal layer is grown to a height different from an interface between the germanium substrate and the gate insulating film; wherein in the removing step, a bottom of the second sidewall insulating film is located 52 1278115. The portion of the first sidewall insulating film between the surface and the surface of the germanium substrate is removed to form a space, and in the step of growing the semiconductor mixed crystal layer, the semiconductor mixed crystal layer It fills the space. 15. The method of claim 14, wherein the first sidewall insulating 5 film and the second sidewall insulating film are formed from insulating materials having different etch selectivity, and in the removing step, using one The etching solution is such that an etching rate in the first sidewall insulating film can be made larger than an etching rate in the second sidewall insulating film. 16. The method of claim 14, wherein in the step of forming a channel, the sections are formed by dry etching such that side surfaces of the channels are perpendicular to the substrate A main plane. 17. The method of claim 14, wherein in the step of forming a channel, the side surfaces having a cross section perpendicular to a major plane of the crucible substrate are etched to follow different The Si (lll) plane forms a plurality of 15 sections. 18. The method of claim 14, wherein the side surfaces having a cross section perpendicular to a major plane of the fractured substrate are etched between the step of removing and the step of growing A section is formed along the Si (ll 1) plane. The method of claim 14, wherein a dopant gas having the predetermined conductivity type is added to a Si gas source and a Ge or C gas source by low pressure CVD (Chemical Vapor Deposition) ) to carry out the steps of this growth. 53