I271〇?64i twf.doc/r 八、本案若有化學式時，請揭示最_示獅特徵 學式： 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種輸出入緩衝裝置，且 於-種具有高速預緩衝準位移位器之輪出入】有關 【先前技術】 友衡衣置。 加快隨集度不斷的提升以及操作速度日益 勢。、因此:塊的卫作電壓有越來越低的趨 對外部電路收送對應準位之訊號。出入緩衝裝置才能 積體說明厂：積體電路之方塊圖。請參照圖1A， 二Γ 塊110透過多個輸出入緩衝茫置m中 以輸出入緩衝裝置13〇盥14〇 野衣置（圖中 (圖中以料⑽代表之则部路H之各個輝塾 位之訊號。核心區塊11G的對應準 心區塊110欲洁砜押拥/ 弘&為VCCK，因此當核 需利用工作電愿=、^nnpad) 140傳送訊號至外部電路，必 轉換。同理，本核、、「播之輸出入緩衝裝置130進行準位 圖一 置15G進彳了準位轉換。 請參照輸出入緩衝裝置⑽之方塊圖。 輸出入緩衝裝置130包括準位移位器(ievd 1271034 - 16497twf.doc/r shifter) 131、預缓衝器(pre_buffer) 132 與輸出緩衝哭 i33。 一般而言，輸出入埠電源電壓VDD之準位較核°=電壓 VCCK高，因此需利用準位移位器131將核心區塊11〇所 輸出之訊號DATA進行準位轉換。預緩衝器132與輸出緩 衝器133則將準位移位器131之輸出訊號傳送至焊墊14〇。 由於需要推動較高壓之外部電路，習知的輸出緩衝器 133往往操作在較高電壓環境巾，因此常使用可耐受較高 電壓之厚氧化層金氧半電晶體元件(thick 〇娜组 成輸出緩衝器133。在相同驅動能力之下，厚氧化層金氧 半電晶體元件之大小將比薄氧化層金氧半電晶體元^恤 oxuie device)還大’亦即厚氧化層金氧半電晶體元件之寄生 電容值將比薄氧化層金氧半電晶體元件大。如此—來辦加 I預緩衝器132之輸出負載，使得輸出入緩衝裝置13〇曰之 操作速，無法提升。再者’有些f知預緩衝器132中亦會 使用厚氧化層金氧半電晶體元件，使得其轉能力變差: 進，導致輸出人緩衝裝置13〇之操作速度更加無法提升。 近來有許多讀(例如美國第6429716號專卵卩針對上述 習知技術之諸缺失而提出各種改進技術。 【發明内容】 ㈣1發_目的就是提供—種預緩衝準位移位器，以便 ，：位亚且驅動由薄氧化層金氧半電晶體 in oxide device)所構成之緩衝器。 6 1271034 · 16497twf.doc/r *薄提:二=出入緩衝裝置’使用 與緩衝器，以=構成之預緩衝準位移位器 似基ΐ上t及其他目的’本發明提出一種預緩衝準位移 緩i單元預位移位器包括可娜電流源、電流鏡、 源接收第-次i甜位電路以及第二鉗位電路。可切換電流 其第一二3訊!虎並依據第一資料訊號決定提供輯至 4或其第二電流端。電流鏡之第—電流端 可第-電流端，並且其第二電流端耦接至 罝-夕、二二弟—電流端並輸出該第二資料訊號。緩衝 訊：〗入f耦接至電流鏡之第二電流端並輸出第三資料 弟—她電_接至電流鏡之第二電流端，用以钳 限㈣零咱第二資料訊號之準 衝單，輸出端，用以钳限第三資料訊號之^祕至緩 用舰^看’本發明提出—種輸出人緩衝褒置， m貧料訊號而產生輸出資料訊號並輪出至焊 =上出';r妾收並依據第二資料訊號與第三= 二串”號輸出至焊墊。其中輸出緩衝器具有電 ^ = 晶體串是由受控於第二資料訊號之第-堆 =电=肢、=控於第一參考電壓之至少一第二堆疊電晶 脰、叉控於第二參考電壓之至少一第= 曰 =資料訊號之第四堆叠電晶體相:串二 T準位私位讀接至輸出緩衝器，用哺換第―資料訊號I271〇?64i twf.doc/r VIII. If there is a chemical formula in this case, please reveal the most _ lion characteristic formula: IX. Invention Description: [Technical Field] The present invention relates to an input-input buffer device. And in a kind of high-speed pre-buffered quasi-displacer wheel access] related [prior art] You Heng clothing. Accelerate the continuous improvement of the collection and the increasing speed of operation. Therefore, the guard voltage of the block has a lower and lower voltage, which tends to receive the corresponding level signal from the external circuit. In and out of the buffer device can be integrated into the factory: block diagram of the integrated circuit. Referring to FIG. 1A, the two blocks 110 are transmitted through a plurality of output buffers m to be input and output into the buffer device 13〇盥14〇 (the figure (the figure is represented by the material (10). The signal of the 塾 position. The corresponding aligning block 110 of the core block 11G is required to be condensed by sulfone/Hong & VCCK, so when the core needs to use the working power =, ^nnpad) 140 to transmit signals to the external circuit, it must be converted. In the same way, the core and the "input output buffer device 130 perform the level map and set the 15G into the level conversion. Please refer to the block diagram of the output buffer device (10). The output buffer device 130 includes the quasi-displacement. Positioner (ievd 1271034 - 16497twf.doc/r shifter) 131, pre-buffer (pre_buffer) 132 and output buffer cry i33. In general, the output 埠 power supply voltage VDD level is higher than the core ° = voltage VCCK, Therefore, the signal DATA outputted by the core block 11A needs to be level-converted by the quasi-bit shifter 131. The pre-buffer 132 and the output buffer 133 transmit the output signal of the quasi-displacer 131 to the pad 14习. Known output buffer due to the need to push higher voltage external circuits 133 tends to operate in higher voltage environmental wipes, so thick oxide metal oxide semi-transistor components that can withstand higher voltages are often used (thick 组成na constitutes output buffer 133. Under the same drive capability, thick oxide gold The size of the oxygen semi-transistor element will be larger than that of the thin oxide layer of the oxuie device. That is, the parasitic capacitance of the thick oxide layer of the gold oxide semi-transistor element will be smaller than that of the thin oxide layer. The crystal element is large. Thus, the output load of the I pre-buffer 132 is increased, so that the output speed of the output buffer device 13 can not be improved. Further, some thick buffer layers are also used in the pre-buffer 132. The gold-oxygen semi-transistor element makes its turning ability worse: the operation speed of the output buffer device 13 is further unacceptable. Recently, there have been many readings (for example, the US Pat. No. 6429716 specializing in the above-mentioned prior art) A variety of improved techniques are proposed. [Summary] (4) The first purpose is to provide a pre-buffered quasi-displacer so that: the sub-Asian drive is controlled by a thin oxide oxide in a transistor. 6 1271034 · 16497twf.doc / r * Thin: two = access buffer device 'use and buffer, to = pre-buffered quasi-positioner based on t and other purposes' the present invention A pre-buffered quasi-displacement slow-unit pre-displacement device is proposed, which comprises a Kana current source, a current mirror, a source receiving first-times i-sweet bit circuit and a second clamp circuit. The switchable current is the first two 3 signals! And according to the first data signal, the serial to 4 or its second current terminal is provided. The current end of the current mirror can be a current-current terminal, and the second current terminal is coupled to the 罝- Xi, 二二弟-current terminal and outputs the second data signal. Buffering: 〗 The f-coupled to the second current terminal of the current mirror and output the third data brother--she is connected to the second current end of the current mirror to clamp (4) zero 咱 the second data signal Single, output, used to clamp the third data signal to the slow-moving ship ^ see 'the present invention proposes a kind of output buffer device, m poor material signal to produce output data signal and turn to welding = Output ';r妾 and output to the pad according to the second data signal and the third=two string number. The output buffer has electricity ^ = crystal string is controlled by the second data signal - heap = electricity = limb, = at least one second stacked transistor controlled by the first reference voltage, at least one of the second reference voltage = 曰 = data signal of the fourth stacked transistor phase: string two T level private Bit read to output buffer, use to feed the first - data signal
1271034 16497twf.doc/r ^ΐ位亚據时別提供第二資料訊號與第三資料訊號裏 輸出緩衝器之第-輸人端與第二輸人端。 ° 本發明因使用由薄氧化層金氧半電晶體元 ，準位移位器與輸出緩衝器，因此可以提昇其速 又。再者’本糾目制触電路而將推織丨緩之 ㈣的跨壓(VGltageswing)控制在合適的電壓範圍， =確驅動由薄氧化層金氧半電晶體元件所組成的輪出缓 衝益亚確保輸出入緩衝裝置之可靠度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 日w ’下域舉較佳實施例，並配合_献，作詳細說 明如下。 【實施方式】 以下將以輸出緩衝裝置為範例，以便於說明本發明。 熟習此技藝者亦可依本發日狀精神與下述實施例之示而 犬員推至輸出緩衝裝置或雙向緩衝裝置。 的圖2是依照本發明實施例說明一種具有預緩衝準位移 位^230的輸出人緩衝裝置之方塊圖。請參照圖2，包含 員、、爰衝準位移位為230與輸出緩衝器220之輸出入緩衝裝 置輕接至知墊(pacj) 21〇，用以依據前級電路(例如核心區塊) 所輸出之第—資料訊號DATA而產生輸出資料訊號，並將 輸出資料訊號傳送至焊墊210。 ^輸出緩衝器22〇具有第一輸入端、第二輸入端與耦接 至=墊210之輸出端。輸出緩衝器22〇分別經由其第一輸 入端與第二輸入端接收預緩衝準位移位器230所提供之第 8 I2710l_ 訊號與第三資料訊號，並據以將輸出資料訊號經由 Ϊ輸出ί輸出ΐ焊墊21G。於本實施例t，輸出緩衝器220 〇括由第-堆豐電晶體22卜第二堆疊電晶體222、第三 豐電晶體223與第四堆疊電晶體—相互 ，體串。在此電晶體221與222為p型電晶體，而 f曰Γ4則^型電晶體。在此輸出緩衝器⑽中二 电日日體均可以疋薄氧化層金氧半電晶體元件。 電晶體221之閘極即為輪出緩衝器22〇 電壓日體2 電源 定蝴，之電:=第=考，_(固 沒極即為輸出緩衝器220之輸出二二=體222之 電壓咖！之偏壓而保持導^“㉟晶體222因受參考 移位器230所提供之第接收預緩衡準位 接至電日，二貝科讯號。電晶體224之沒極輕 二電壓二是接並且電㈣224之_接至第 轉換ΓΐΓΤ11230輕接至輸出緩衝器細，用以 二，分別提供第 第二輸入端。預緩衝準位:位322G之第-輸入端與 刊移位為23〇包括可切換電流源 9 1271034 16497twf.doc/r 23i、電流鏡232、緩衝單元如、第一钳位電路说 二，位電路235。可切換電填源231依據其控制端所接收 之第一資料訊號DATA而決定提供電流至其第—山 IT1或第二電流端IT2〜二者之一。電流鏡232具有第 流端IN與第二電流端out。電流鏡232之第一電流端m • _至可切換電流源231之第一電流端m，並且^流鏡 - 2%之第二電流端OUT耦接至可切換電流源231之第二^ 鲁 流端IT2與輸出緩衝器220之第一輪入端。其中，電流^ 232之第二電流端〇UT輸出第二資料訊號。 现兄 緩衝單元233之輪入端耦接至電流鏡232之第二電流 端=υτ ’而緩衝單元233之輸出_接至輪出緩衝器 ^第二輸入端。其中’緩衝單元233輸出端之訊號即為第 三資料訊號。第一鉗位電路234耦接至電流鏡232之第二 電流端OUT，肖以鉗限(clamping)第二資料訊號之跨壓 (voltage swing)。第二鉗位電路235耦接至緩衝單元幻3之 輸出端，用以鉗限第三資料訊號之跨壓。本實施例因使用 • 鉗位電路將推動輸出緩衝器220訊號的跨壓控制在合適的 . 電壓範圍，因此可以正確驅動由薄氧化層金氧半電晶體元 件所組成的輸出緩衝器220並確保輸出入緩衝裝置之可靠 ' 度。 、 卜在此預緩衝準位移位器230中所有電晶體均可以是薄 氧化元件薄氧化層金氧半電晶體元件。另外，更可以視需 要而在預緩衝準位移位器230中配置可控制開關236。; 控制開關236之第一端耦接至緩衝單元233之輸出端。可 1271034 16497twf.doc/r ，制開關236依據其控制端之第一資料訊號DATA而決定 是否將第三資料訊號切換至接地電壓。 上述預緩衝準位移位器230可依下述實施例施作之。 ，3疋依A?、本發明說明圖2中預緩衝準位移位器230之實 施例，路圖。請參照圖3，其中可切換電流源231包括第 一電，源3U、第二電流源312與切換器313。於本實施例 中’第—-電流源3U、第二電流源312分別以第一電晶體 T1與第二電晶體T2實施之，並且電晶體τι與丁2均為n ，電晶體。電晶體T1之第一端(例如間極你接第一電壓1271034 16497twf.doc/r ^Do not provide the second and second input terminals of the output buffer in the second data signal and the third data signal. ° The present invention can be improved in speed by using a thin oxide layer of gold oxide semi-transistor, a quasi-displacer and an output buffer. Furthermore, 'this correction system touches the circuit and controls the VGltageswing of the (4) to the appropriate voltage range, = indeed drives the wheel-out buffer composed of thin oxide MOS semi-transistor elements. Yiya ensures the reliability of the output into the buffer device. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] An output buffer device will be exemplified below to facilitate the description of the present invention. Those skilled in the art can also push the dog to the output buffer or the two-way cushioning device in accordance with the present embodiment and the following embodiments. Figure 2 is a block diagram showing an output buffer device having a pre-buffered quasi-displacement bit 230 in accordance with an embodiment of the present invention. Referring to FIG. 2, the input and output buffers of the output buffer 230 and the output buffer 220 are lightly connected to the pacj 21 〇 according to the pre-stage circuit (for example, the core block). The output data signal DATA is output to generate an output data signal, and the output data signal is transmitted to the bonding pad 210. The output buffer 22 has a first input, a second input, and an output coupled to the pad 210. The output buffer 22 receives the 8th I2710l_signal and the third data signal provided by the pre-buffered quasi-positioner 230 via the first input end and the second input end, respectively, and outputs the output data signal via the output signal Ϊ The germanium pad 21G is output. In the present embodiment t, the output buffer 220 includes a second stacked transistor 222, a third abundance crystal 223, and a fourth stacked transistor. Here, the transistors 221 and 222 are p-type transistors, and the f曰Γ4 is a type of transistor. In this output buffer (10), the dielectric solar cells can be thinned by the oxide layer. The gate of the transistor 221 is the wheel snubber 22 〇 voltage body 2 power supply butterfly, the electricity: = the first test, _ (solid no pole is the output buffer 220 output two two = body 222 voltage The bias of the coffee device is maintained. The "35 crystal 222 is connected to the electric day by the receiving pre-neutralization level provided by the reference shifter 230. The second Becco signal. The transistor 224 has no light and two voltages. The second is connected to the electric (four) 224 _ to the first conversion ΓΐΓΤ 11230 lightly connected to the output buffer, for the second, respectively provide the second input. Pre-buffer level: the first input of the bit 322G and the journal shift 23〇 includes a switchable current source 9 1271034 16497twf.doc/r 23i, a current mirror 232, a buffer unit, for example, a first clamp circuit, a bit circuit 235. The switchable power source 231 is received according to the control terminal thereof. A data signal DATA determines to supply current to either the first mountain IT1 or the second current terminal IT2~. The current mirror 232 has a current terminal IN and a second current terminal out. The first current terminal m of the current mirror 232 • _ to the first current terminal m of the switchable current source 231, and the second current terminal OUT of the flow mirror - 2% is coupled to The second current terminal IT2 of the current source 231 and the first wheel input terminal of the output buffer 220 are switchable, wherein the second current terminal 〇UT of the current ^232 outputs the second data signal. The input terminal is coupled to the second current terminal of the current mirror 232=υτ', and the output of the buffer unit 233 is connected to the second input terminal of the wheel-out buffer. The signal at the output of the buffer unit 233 is the third data signal. The first clamp circuit 234 is coupled to the second current terminal OUT of the current mirror 232 to clamp the voltage swing of the second data signal. The second clamp circuit 235 is coupled to the buffer unit. The output of the magic 3 is used to clamp the voltage across the third data signal. This embodiment uses the clamp circuit to push the voltage across the output buffer 220 to a suitable voltage range, so it can be driven correctly. The output buffer 220 composed of a thin oxide layer of gold oxide semi-transistor elements ensures the reliability of the output into the buffer device. In this pre-buffered quasi-positioner 230, all of the transistors can be thin oxide elements. Oxide layer gold oxide semi-transistor element In addition, the controllable switch 236 can be configured in the pre-buffered quasi-positioner 230 as needed. The first end of the control switch 236 is coupled to the output end of the buffer unit 233. 1271034 16497twf.doc/r , The switch 236 determines whether to switch the third data signal to the ground voltage according to the first data signal DATA of the control terminal. The pre-buffered quasi-positioner 230 can be implemented according to the following embodiments. The present invention illustrates an embodiment of the pre-buffered quasi-positioner 230 of FIG. 2, a road map. Referring to FIG. 3, the switchable current source 231 includes a first power source, a source 3U, a second current source 312, and a switch 313. In the present embodiment, the first current source 3U and the second current source 312 are implemented by the first transistor T1 and the second transistor T2, respectively, and the transistors τ1 and 丁2 are both n, the transistor. The first end of the transistor T1 (for example, the pole is connected to the first voltage
Ϊ VCCK)，以及電晶體T1之第二端(例如汲極) 電流源231之第一電流端IT1。電晶體T2之第 (列如閘極)耦接第一電壓(例如核心電壓VC = 第二端(例如汲極)即為可切換電流_之第 313依據其第—端之訊號而決定使 、弟一‘耦接至其苐三端或第四端二者之一。 ^第-端即為可切換電流源231之控制端接: =訊號data。切換器313之第二端 第三端(例如源極)，以及切換：373= 至電晶體T1之 體T2之第三端(例如祕;?^313之__接至電晶 上述圖3中之切換器313可參照圖4 依照本發明實施例說明一種切換器之電心之二圖：是 4，在此切換器313包括反(NOT)間510、第回：:曰茶照圖 與第四電晶體T4,其中電晶體T3與T4均為;，日日體T3 叼為Ν型電晶體。 11 1271034 16497twf.doc/rΪ VCCK), and the first current terminal IT1 of the current source 231 of the second terminal (eg, the drain) of the transistor T1. The first (such as the gate) of the transistor T2 is coupled to the first voltage (for example, the core voltage VC = the second end (for example, the drain) is the switchable current _ 313 is determined according to the signal of the first end thereof, The first one is coupled to one of the three ends or the fourth end. ^ The first end is the control termination of the switchable current source 231: = signal data. The second end of the second end of the switch 313 ( For example, the source), and the switch: 373 = to the third end of the body T2 of the transistor T1 (for example, the secret; ? 313 __ connected to the electric crystal. The switch 313 in the above FIG. 3 can refer to FIG. 4 according to the present invention. The embodiment illustrates a second diagram of a switch core: Yes 4, where the switch 313 includes a reverse (NOT) interval 510, a first:: a tea view and a fourth transistor T4, wherein the transistors T3 and T4 All; T3 日 is a 电-type transistor. 11 1271034 16497twf.doc/r
f閘510之輸入端與電晶體T4之閘極即為切換器3i3之 第一端，用以接收第一資料訊號DATA。反閘51〇將所接 收之第一資料訊號DATA反轉後輸出反相訊號給電晶體 T3=閘極。電晶體T3之汲極即為切換器313之第三端， 而電晶體Τ4之汲極即為切換器313之第四端。電晶體^ 之，極與電晶體Τ4之源極相互耗接，並成為切換器313 之第二端。因此，切換器313可以依據其第一端之訊號 DATA而决疋使其第二端耦接至第三端或第四端二者之 、，繼續參照目3，在此電流鏡232包括第六電晶體吖 以及第七電晶體T 7，其中電晶體τ 6與τ 7均為p型電晶 體。電晶體Τ6之第二端(例如源極)叙接至第三電壓(例如 是輸出入埠_壓VDD)，電晶體Τ6之第一端 極)編妾至該電晶體Τ6之第三端(例如錄），並且電晶體 Τ6之第二端即為電流鏡232之第一電流端ιν。電晶體η 之第-端(例如閘極)耦接至電晶體Τ6之第一端， Τ7之第二端(例如源極)麵接至第三電壓，並且電晶體^ 之弟二端(例如汲極）即為電流鏡232之第二電流端〇υτ。 上述緩衝單元233例如包括反問_與開關撕 =〇〇之輸入端即為緩衝單元233之輸入端，用以接 所輸出之第二資料訊號。開關sw依據其控制 而f定其第—端與第二端之間的導通狀態，其中開關SW 之控制端柄接至反間_之輸出端，開關SWn_ 12 1271034 16497twf.doc/r 接至第二電壓(例如是輸出入埠電源電壓VDD) SW之第二端即為缓衝單元233之輸出端。 圖5是依照本發明說明圖3中反閘600之實施範例。 明夢知、圖5，在此反閘600包括p型電晶體與N型電 b曰體620。電晶體61〇之閘極與電晶體62〇之閘極相互耦 接而成為反閘600之輸入端。電晶體61〇之源極耦接第三 電麼(例如是輸出人埠電源糕VDD)，而其汲極即為反閘 600之輸出端。電晶體62〇之源極耦接第四電壓，以及電 晶體620之汲極耦接電晶體61〇之汲極。於本實施例中， 上述第四電壓是第三參考電壓REF3 (固定電壓）。 a、上述開M SW可依任何方式實施之，例如參照圖 保=件之可靠度。圖6是依照本發明說明圖3中開 例。請參照圖6，開關sw包括ρ型電晶 i f P1 〇 ι電壓(例如是輸出人埠電源電壓 _而其錄触至電晶體ρ2 閘極耦接至第五電壓，而雷……：％曰曰體Ρ2之 包日日體P2之汲極則作為開關SW ，弟=(即為緩衝單元233之輸出端）。於 逑第五電Μ是第四參考電壓娜4㈤定電"1， 考依其需要而適當地設定上述第-失 考私昼卿卜第二參考電壓REF2、m (弟參 與第四參考電壓咖4之準位。尸 咖3與卿4可叹相叫狀魏卿1、 1271034 16497twf.doc/r 請繼績參照圖3，在此多二^甘位電路234每楚p型電 晶體，其源極麵接第三電壓如是輸出入璋電源命斤 VDD)，其閘_接至其祕，以及其汲極墟至電= 232之第二電流端〇UT。然而，第一钳位電路234之每 方式並不限於圖3所示之方式。例如，可以使用二極^ .. ^貫施第—齡電路234，而使二極體單元之陽極|馬接第 • 三電塵，並使一其陰極輕接至電流鏡232之第二電流端ουτ。 鲁 在此—第二钳位電路235包括Ν型電晶體，其源極耦接 第二電壓(例如是接地電壓），其閘極輕接至其没極，以及 其沒極搞接至緩衝單元233之輸出端。然而，第二甜位電 路235之實!，方式並不限於圖3所示之方式。例如，可以 使用-極體單疋實施第二鉗位電路235，而使二極體單元 之陰極_第二電壓，其陽極輕接至緩衝單元233之輸出 端。 另外，可控制開關236可以包括第一反閘mvl、第二 反間INV2與N型電晶體TN。反閘INV1之輸入端即為可 φ 控制開關236之控制端，用以接收第-資料訊號DATA。 反㈤INV2之輪入端_接至反閘INV1之輪出端。反閘INV1 :、將所接收之第一資料訊號DATA、緩衝後輸出至電 曰曰之閘極。電晶體1^之源極（即為可控制開關236 之第一端）耦接至第二電壓(例如是接地電壓），而電晶體 TN#之没極（即為可控制開關236之第一端）則耦接至緩 衝早元233之輪出端。因此，即可控制第三資料訊號，使 14 號接The input terminal of the f-gate 510 and the gate of the transistor T4 are the first ends of the switch 3i3 for receiving the first data signal DATA. The reverse gate 51〇 inverts the received first data signal DATA and outputs an inverted signal to the transistor T3=gate. The drain of the transistor T3 is the third end of the switch 313, and the drain of the transistor Τ4 is the fourth end of the switch 313. The transistor is in contact with the source of the transistor Τ4 and becomes the second end of the switch 313. Therefore, the switch 313 can be coupled to the third end or the fourth end according to the signal DATA of the first end thereof, and continue to refer to the object 3, where the current mirror 232 includes the sixth The transistor 吖 and the seventh transistor T 7, wherein the transistors τ 6 and τ 7 are both p-type transistors. The second end (eg, the source) of the transistor 叙6 is connected to a third voltage (eg, input/output 埠_voltage VDD), and the first end of the transistor Τ6 is braided to the third end of the transistor Τ6 ( For example, the second end of the transistor Τ6 is the first current terminal ι of the current mirror 232. The first end of the transistor η (eg, the gate) is coupled to the first end of the transistor Τ6, the second end of the Τ7 (eg, the source) is connected to the third voltage, and the second end of the transistor is The drain is the second current terminal 〇υτ of the current mirror 232. The buffer unit 233 includes, for example, an input terminal of the inverse _ and the switch tear 〇〇, which is an input end of the buffer unit 233 for receiving the output second data signal. The switch sw is in accordance with its control to determine the conduction state between the first end and the second end, wherein the control end of the switch SW is connected to the output end of the reverse _ switch, and the switch SWn_ 12 1271034 16497twf.doc/r is connected to the The second voltage (for example, the input/output power supply voltage VDD) is the output terminal of the buffer unit 233. FIG. 5 illustrates an embodiment of the reverse gate 600 of FIG. 3 in accordance with the present invention. Ming Mengzhi, Fig. 5, here the reverse gate 600 includes a p-type transistor and an N-type electric b-body 620. The gate of the transistor 61 is coupled to the gate of the transistor 62 to become the input of the reverse gate 600. The source of the transistor 61 is coupled to the third power (for example, the output power VDD), and the drain is the output of the reverse gate 600. The source of the transistor 62 is coupled to the fourth voltage, and the drain of the transistor 620 is coupled to the drain of the transistor 61. In this embodiment, the fourth voltage is the third reference voltage REF3 (fixed voltage). a. The above-mentioned open M SW can be implemented in any manner, for example, referring to the reliability of the figure. Figure 6 is an illustration of the example of Figure 3 in accordance with the present invention. Referring to FIG. 6, the switch sw includes a p-type electric crystal if P1 〇ι voltage (for example, an output power supply voltage _ and its recording to the transistor ρ2 is coupled to the fifth voltage, and the thunder...: %曰The 汲 Ρ 2 package of the Japanese body P2 is used as the switch SW, the brother = (that is, the output of the buffer unit 233). The fifth Μ is the fourth reference voltage Na 4 (five) fixed electricity " 1, test According to the needs of the above, the above-mentioned first-missing private syllabus second reference voltage REF2, m (the younger brother participates in the fourth reference voltage coffee 4 level. The corpse 3 and the Qing 4 sighs like Wei Qing 1 1271034 16497twf.doc/r Please refer to Figure 3, where the multi-two-gigabit circuit 234 is a p-type transistor, and its source is connected to the third voltage, such as the input and output power supply VDD). _ is connected to its secret, and its second current terminal 〇UT of 232. However, each mode of the first clamp circuit 234 is not limited to the mode shown in Fig. 3. For example, two poles can be used. ^ .. ^ The first-age circuit 234 is applied, and the anode of the diode unit is connected to the third electric dust, and a cathode is lightly connected to the second electric current of the current mirror 232. The second clamp circuit 235 includes a Ν-type transistor, the source of which is coupled to a second voltage (for example, a ground voltage), the gate is lightly connected to its immersed pole, and its pole is not connected. To the output of the buffer unit 233. However, the second sweet bit circuit 235 is not limited to the mode shown in Fig. 3. For example, the second clamp circuit 235 can be implemented using a - pole body, The cathode of the diode unit has a second voltage, and its anode is lightly connected to the output end of the buffer unit 233. In addition, the controllable switch 236 can include a first reverse gate mvl, a second reverse INV2, and an N-type transistor TN. The input end of the gate INV1 is the control terminal of the φ control switch 236 for receiving the first data signal DATA. The reverse (5) the wheel input terminal of the INV2 is connected to the wheel output terminal of the reverse gate INV1. The reverse gate INV1: will receive The first data signal DATA is buffered and output to the gate of the battery. The source of the transistor 1 (ie, the first end of the controllable switch 236) is coupled to a second voltage (eg, a ground voltage). The transistor TN# has no pole (ie, the first end of the controllable switch 236) is coupled to the buffer Element 233 of the wheel side. Therefore, the third control data signals to the contact 14
1271034 16497twf.doc/r 其依照第一資料訊號DATA而決定是否使第三資料訊 地。 ^綜上所述，在本發明之預緩衝準位移位器與輸出緩衝 ，因可以完全使用薄氧化層金氧半電晶體元件，因此可以 提昇其操作速度。再者，本發明因使用鉗位電路而將推動 輸^緩衝器之訊號的跨壓(voltage swing)控制在合適的電 壓範圍中，因此可以正確驅動由薄氧化層金氧半電晶體元 件所組成的輸出緩衝器，並確保輸出入緩衝裝置之可靠度。 —雖然本發明已以較佳實施例揭露如上，然其並非用^ 限疋本發明’任何熟習此技藝者，在不脫離本發明之 ^範圍内，當可作些許之更動與潤飾，因此本發明之保罐 乾圍當視後附之申請專利範圍所界定者為準。 “叹 【圖式簡單說明】 圖1Α是說明一般積體電路之方塊圖。 圖是說明圖1Α中習知輸出入緩衝裝置之方塊圖。 你” ^讀照本發财施例_—種财賊衝準位移 位為的輸出入緩衝裝置之方塊圖。 之兩疋依照本發明實施例說明一種預缓衝準位移位器 圖4疋依照本發明實施例說明一種切換器之電路圖。 圖5是依照本發明說明圖3中反閘之實施範例。回 圖6是依照本發明說明圖3中開 w 【主要元件符號說明】 乾例。 110 :核心區塊 15 1271034 16497twf.doc/r 130、140 :輸出入缓衝裝置 131 :習知準位移位器 132 :習知預緩衝器 133 :習知輸出緩衝器 140、210 :焊墊 220 :輸出緩衝器 230 :預緩衝準位移位器 221 〜224、610、620、T1 〜T7、TN :電晶體 231 可切換電流源 232 電流鏡 233 緩衝單元 234 第一鉗位電路 235 第二鉗位電路 236 可控制開關 311、312 :電流源 313 :切換器 • 510、600、INV卜 INV2 :反閘 PI、P2 : P型電晶體 REF1、REF2、REF3、REF4 :參考電壓 ' SW :開關 VDD :輸出入埠電源電壓 VCCK :核心電壓 161271034 16497twf.doc/r It decides whether to make the third data broadcast according to the first data signal DATA. In summary, in the pre-buffered quasi-displacer and output buffer of the present invention, since the thin oxide layer of the gold oxide semi-transistor element can be completely used, the operation speed can be improved. Furthermore, the present invention controls the voltage swing of the signal for driving the buffer in a suitable voltage range by using a clamp circuit, so that it can be properly driven by a thin oxide layer of gold oxide semi-transistor components. The output buffer and ensure the reliability of the output into the buffer. The present invention has been described above with reference to the preferred embodiments of the present invention, and it is not intended to be limited to the scope of the present invention, and may be modified and retouched without departing from the scope of the invention. The invention shall be subject to the definition of the patent application scope attached to it. "Sighing [simplified description of the schema] Figure 1 is a block diagram illustrating the general integrated circuit. The figure is a block diagram illustrating the conventional input and output buffering device of Figure 1. You can read the financial example _ - The thief punches the displacement bit as the block diagram of the output into the buffer device. A pre-buffered quasi-displacer is illustrated in accordance with an embodiment of the present invention. FIG. 4 is a circuit diagram of a switch in accordance with an embodiment of the present invention. Figure 5 is a block diagram showing an embodiment of the reverse gate of Figure 3 in accordance with the present invention. 6 is a diagram showing an example of the opening of the main component in FIG. 3 in accordance with the present invention. 110: core block 15 1271034 16497twf.doc/r 130, 140: input-in buffer device 131: conventional quasi-positioner 132: conventional pre-buffer 133: conventional output buffer 140, 210: pad 220: output buffer 230: pre-buffered quasi-positioners 221 ~ 224, 610, 620, T1 ~ T7, TN: transistor 231 switchable current source 232 current mirror 233 buffer unit 234 first clamp circuit 235 second Clamp circuit 236 can control switches 311, 312: current source 313: switcher 510, 600, INV INV2: reverse gate PI, P2: P-type transistor REF1, REF2, REF3, REF4: reference voltage 'SW: switch VDD: output 埠 power supply voltage VCCK: core voltage 16