TWI270785B - Universal serial bus flash memory integrated circuit - Google Patents

Abstract

The present invention discloses a universal serial bus flash memory integrated circuit, which provides a flash memory integrated circuit having universal serial bus and host connections. Universal serial bus (USB) becomes a standard serial interface, which is capable of quickly storing data in an external memory device, and quickly reading data from the external memory device. Therefore, combining the speed of the flash memory device and the universal serial bus is very important. Further, by means of designing the flash memory device according to the universal serial bus interface, the flash memory device could become a standard universal serial bus storage device, such that the host and the flash memory storage device could easily connect and interact with each other. If the storage device represents an integrated circuit type, it becomes a built-in universal serial bus flash memory integrated circuit.

Description

1270785 IX. Description of the invention: [Technical field of the invention] The invention relates to a flash memory storage device, in particular to a flash memory storage device type which can be connected by a bus bar, that is, a _____ face Road f [Prior Art] _τγ, and the non-erasable characteristics make it a non-I of the new data. In the case of Rushe (4) Zi Qiang viewing device, this is the data storage method of the big Γρ八^ The convenience brought by the flash memory makes it more advantageous than the dog I = storage | (such as hard disk, etc.), in addition to the advantages of flash memory and low power And the advantages of high speed. The crime of the quarter two θ flash memory is forward-oriented, which means that even if the power is turned on, it still retains the stored data, which is more than the standard random access memory (RA(4).

Progress is made, and the random access memory is volatile. When the shame power is turned off, the stored data is lost. The universal serial transmission interface is the standard of the PC/ΝΒ/ϊ A product, and the above products can be activated by the storage medium of the universal serial transmission interface (, 丨ab 1 e )' so that the hard disk is serially transmitted through the interface. The space replaced by storage media has increased's. However, the storage media of the current serial transmission interface is often plugged in, which causes a lot of inconvenience. 5 1270785 The current miniaturized ϊ A products such as p DA, computers, digital cameras, etc. are equipped with multi-functional requirements, so they are equipped with operating systems (〇perati〇n System) such as Boundary nc E/L lnux, etc. Hardware design requires a CPU, plus a NOR Type Flas.h Mem〇r to store the code, if you need to have data storage space, you need to add other _ram or built-in iNAND Flash Memor y or external memory card, the above three solutions _ do not count ^in CE / Linux's fresh 'I face', you need to modify these operating system drivers or applications, S The development of new products often costs a lot of effort and money for these interfaces. Therefore, 'currently needed—a storage medium can be built into the system, with a standard surface that can be used in various operating systems, without having to modify the operating system or program of these operating systems and have low power consumption. The advantages of rate, availability, lightness, and high speed are required to achieve portability. Lu [invention] 】, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Flash memory volume connected to the bus and the host

Universal serial bus (USB has become the standard serial interface, it allows the number 6 1270785 to follow the late thief _ _, and: =, = Γ flash memory volume body circuit to read data, so profit, except two or two points 'And the speed of the universal serial bus will be very good, 胄 by the four-column serial bus interface serial combination. 4 shirts, come to the machine and (four) the clock can __ even and interactive control system = sequence The block of the bus flash memory volume circuit includes 1: M milk - domain mail, Mei's foot retains the universal ship channel interface (phase transmission interface); the storage type is fast = 2 = fine, after the coffee drink her recall volume body electric two out of the pepper peak followed by the lion volume; and the controller input 〇 = _ position, the job sequence bus (four) memory volume circuit can be controller in the device - The main component of this control, which controls the commands and data between the flash memory volume circuit and the host: = ^ The data in the array is preferably - does not require external read-only memory - (ROM) or Single-chip random access memory (RAM). Universal serial bus flash memory volume body The road library saves the two-fold memory to expand the magic surface to expand the flash memory capacity, so as to extend the memory size by using the flash memory array 1270785. The order of the invention is the flash memory volume. The controller of the body circuit has a myriad of functions. Among these functions, there is a - item for controlling the Wanxian ship flow interface. The controller scales the Vanke ship flow specification in terms of physical and secret agreements, and the controller step-by-step includes - A FI FQ controller buffer that causes the controller to receive commands and record dumps from the host with the multi-purpose downstream bank, which is then stored in a special temporary pin defined by the control port, and The controller also controls the data transfer between the host and the host. In addition, the controller also provides status data to the host. When the host issues a write command, the financial output is interrupted and sent to the controller and the micro Handle H to notify the microprocessor H of the command, and the location of the command. The processor (for example, an 8- or 16-bit microprocessor) is the main component of the controller: and the micro-processing ^ Read the order from the temporary storage The command and the button, in addition, and the microprocessor also executes the command with parameters, the microprocessor manages and maps the FI FQ address of the sequence ship to the control buffer on the one hand, and the wire has its own order ship flow row. The domain is sewn, and the data is transmitted to the host. In addition, the micro-drive is also a (four) clock _ management, such as the trial of private or item fetching commands, in addition, the microprocessor is also based on the control of different methods Execute the address method., w Micro-processing is a read-only memory (R〇M) that will be built into the controller to control the alpha spears to be stored 7 while the microprocessor is controlling II to execute the universal sequence. The system uses a system random access memory (RA Μ) for the 1270785 row command or flash algorithm, which reduces the cost of the system because it does not need to leave the chip memory. The system buffer used to buffer the universal serial bus interface and the flash memory array interface is used as a cache. The microprocessor manages the address of the buffer. If necessary, the buffer can pass the byte or text. Access. The invention's universal serial bus flash memory volume circuit further includes: - a hardware state machine to establish a system buffer between the host and the flash memory, and a write and write timing 'flash interface And the circuit controls the read and write commands to the flash memory array 'in this case, this is a pure hardware circuit 0. In addition, the data of the New Chong area cache is written. When (4) remembering the marrow array, the c circuit will encode the cc code, and when reading the data of the (4) register array to the slow_cache, the Ecc circuit decodes the ECC code. If the Ec error occurs, the ECC circuit will Interpret the text or byte in the buffer cache and error. The universal sequence bus command actually includes the receiver of the receiving host, and tears the command and the wheeled lion's axis, and the second and the nickname _, has received the command. The control benefits are based on the universal sequence bus logic and entity specification data 'and the data is sent to the domain, the number of the address side ^ ^ 3 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Mapping. 9 1270785 In the middle of the road ^ ΐ command and record "correction of the scales _ volume volume will be stored in the - specific temporary correction, the data will be followed by the micro-domain (four) news Including 7 her yuan, BmRequest D (1), and bit 70 specify the type of command agreement, the type includes standard, level aid = for; 1 the flash memory device of the month of the three-axis plastic agreement The ordinary order of slaves, such as the universal serial sink. ~~ ^Feature The flash memory storage device of the invention utilizes a universal sequence bus _s s storage class with b u 1k/control/break transmission in a specific form. Due to the limitation on the flash memory entity, the erase command must be executed before the write command is executed. Generally, the _ memorandum needs _about 1 QQ 10,000 times after the erase, then the axis, 35鸠It is very important to extend the life of the flash memory, __ for a logical and physical address mapping table 'and a mother/sub-architecture to achieve this goal. The following is a description of the use of the logical and physical address mapping table. When the flash memory is started, 'all the blocks will be searched' and the relationship between the searched entity and the logical block will be difficult. The address mapping table, at the same time, the unused entity area is placed in the _block for the FIF to use, and then the logic and the logical block in the 1270785 physical address mapping table are used to find the corresponding physical block. The address 'in this way, it is possible to accurately write or capture the data associated with a particular physical block. When writing data to flash memory, you may need to erase the block (new block) instead of the block, and write the data to the new block. Finally, the data will not be changed. The block, this step completes the action of writing a page of data. If there are several pages of data to be written, the above steps will be repeated. However, if the data continues to repeatedly write the same-block towel, there will be many unnecessary erase and migration actions. Not only is it a waste of time, but it also shortens the life of the flash memory. Therefore, in the flash memory device of the present invention, when data is repeatedly written in the same block, it avoids the erase operation. The migration action is only performed when the replacement block is known. This method not only prolongs the life of the flash, but also improves the efficiency of the device. The following is an example of writing data, which requires 3 2 blocks (sweet

The data of Se c t 〇 r) is written to the logical block address in the parent block starting with 〇/〇 block/page. Each block has 32 pages, and the total physical block/logical block is i 〇 2 4 /992 ' The total spare block of the FIFO is 32, and none of the blocks are defective, and the FIF 0 is reserved. The area obtains the spare block, that is, the sub-block (physical address: 〇3 e 〇h) indicated by the starting indicator (η eadpointer) is taken from the FIF 〇 spare area' and then the starting indicator is increased (pointing to the next spare) Area 11 1270785 block), and writes 32 pages of data into sub-blocks (physical address: 〇3 e 〇 h

)in. Then, the parent block indicated by the address Ο 〇〇〇h is erased, and the end index of the FIF 〇 spare area is increased. Then the physical address of the parent block is filled in the end of the spare area. In the address indicated by the index, the address of the sub-block is 〇3 E 0 h to fill the logical and physical address mapping table (10)(10)h, so that the logical address 〇0 0 0 h points to the physical address 〇3 E 〇 h, the completion of the write. The following is a description of the writing procedure according to the specific form of the invention: The host writes the corresponding write command and address parameters into the memory storage split, and the memory storage device then starts executing the program (4) algorithm, and then, the host The logical address will be swapped into a _memory real block and a dump block, and the (four) will check if the sub-block exists. If the subblock does not exist, will it be from F? Take a clean block from the side to create a sub-block for the existing writer block. Then, check the existing flash memory logical page number to see if the page number of the g person is equal to "Q", if it is equal to "0" 'The data from the game to the flash memory will be written to the buffer, and the count of the block will be reduced. This program will be repeated until the block is counted as "〇", if the page number of the person to be written is If it is not equal to "Q", the data of the parent block will be moved to the sub-block between "Write Post-Page" and "Existing Writer Page", and then, from (4) to the flash memory. If the data will be written by the person, the count of the block will be reduced. "This program will be used until the "Q" is calculated. If the sub-block exists, it will check the logical block of the existing flash memory. 12 1270785 Block 'Whether the write is equal to the last-written fast memory block, if not equal, the parent block The data will be moved to the "sub-block" of "write last page" and "sub-block" of the post-page of this block and then erase the parent block to update the logical and physical addresses in the controller. The mapping table, with the sub-block address generation #原母块块Address 'then' put the erased parent block back into the F j ?〇仔 column to become a clean block 'Ruo Liren's area If the block is equal to the last-written flash memory logical block, it will touch the existing flashing logic page number to see if the writer is greater than the last-writer (4) memory display. If it is greater than, the existing one will be checked. Write page number 'look if d is equal to the last written-page plus i, if it is, the data from the host to flash fe will be written to the buffer, the count of the section will be reduced, this program will be - straight repeat Until the cell block is scaled to "Q", if the page number of the money is not equal to the last page written, "After most of a written", the data will be moved to the parent block and sub-block between "existing written page." If the file to be written is not larger than the last written flash memory logical page, the data of the parent block will be moved between "the last page written" and "the last page of this block". Sub-block, then the parent block is erased, the logic and the intersection address in the controller are updated, the original block address is replaced by the sub-block address, and then the erased The parent block is placed back into the F!F column to become a clean block. When the right-to-write cache page is larger than the last-written person, the parent-free data will be moved to the sub-block between the "last page of the writer" and the "existing writer page". From the continuous to the flash, the data will be written to the buffer, and the count of the cell 13 1270785 will be reduced, and the data will be written until the cell block count is equal to "the flash memory of the specific form according to the invention. In terms of device read sequence, the host's logical address will be converted into a flash memory block and page address, and then 'check the existing flash memory logic block to see if the read is equal to the most ^ - The flashed memory block that is read, if not, the flash memory ^ physical block and page data will be read 'and the cell block count will be reduced, this program will - straight repeat Until the cell block count is equal to "0", the read data is read = the last flash memory logical block read, it will check the existing Lu flash memory logical page, see if the read Greater than the last - a person's flash memory logical page . ° If 'flash memory physical block and page data will be read, and the cell block count will decrease' this program will repeat until the cell block count is equal to "0" until the (five) is not greater than Finally, if you write a person's memory logical page, the data of the sub-block physical block and page will be read S, and the cell block count will be reduced. 'This program will be - the straight repeat block count is equal to " Q" so far. When the microprocessor begins to execute the command, the universal sequence bus flash memory will download its record from the domain, for example, read or use the - vendor command packet system will pass the device / start byte 6 One bit to determine the address mode, . The flash of the hairy day and the moon § the memory device supports the logical block address ([b magic and circular domain start cell block (CHs) mode] if the host Li Hong BA mode is provided, the device will convert it In the (3)s mode, then the c H s mode is changed to 1270785 into a physical address. When the universal order is used to execute the spine command, the controller first will flash the data of the flash memory - a block of cells - The cell block is read into the controller's _(5 1 2 octet), and then the system platoon engine sends the cell block to the host. When the number of cell blocks sent to the line is expected to be read by the host When the number of cell blocks is completed, the entire command is completed. When the universal order ship scale_memory volume circuit is executed, the old device will pass the data of the system_flow block engine. The block is read into the control buffer (5 i 2 bytes), and the cell is stored in (4) memory, and the number of cell blocks written by the cell block sent to the line is recorded. The entire command is completed. The universal sequence bus flash memory volume circuit can support more than one. Flash reading body, this kind of hair supply provides multiple wafer selection feet. When starting the device, = record the type of flash memory (capacity) used for the connection, and the system has 2 2 ' ' 'Universal sequence The __memory touch circuit will sort all the records to find the total capacity. When the host needs this type of data, the megaphone flash memory volume circuit will provide the total capacity to the host instead of The capacity of the wafer as early as one. The body is defeated, and a certain address (logic) is sent to the universal sequence bus. The flash memory is smashed by the mountain. The universal sequence bus flash memory volume circuit will execute the leaf tube, ... The exact chip to be accessed and the corresponding address, _, universal order, 1270785 bus flash memory volume circuit will use the calculated address, and start the wafer selection foot. [Embodiment] Hereby, the above description The general description, as well as the following detailed description, are exemplary and are intended to further explain the invention. The drawings are intended to provide a better understanding of the invention and are incorporated in and constitute a part of the specification. The invention was expressed in conjunction with the narrative and explained the principle of the invention. In the picture, the description of the specific performance is prioritized: At this stage, the reference details of the specific performance of the invention will be made. The examples illustrate the examples, pictures and In the narrative, the same reference number is used for the same or similar parts as much as possible. 〇, the flash flash (4) number of 12 0 is extended, and the charge is 2 Q material against the threat (4) memory 丄 please refer to the figure - According to the specific form of the invention, the schematic diagram of the circuit arrangement of the universal serial bus flash memory volume body is shown in the figure. The figure shows that the universal sequence bus (4) memory rhyme circuit 5 includes - a control and 4 〇 and at least one The flash memory chip 5 Q, and the universal serial bus connector i 连接 is connected to the universal ship flashing flash (four) integrated circuit 5 and the host with the universal serial bus, and the order pet flow (4) The Lai body touch circuit 5 includes at least one flashing Wei wafer 50, and the universal sequence bus line flash memory volume body Wei 5 enters the step-by-step includes -_存_钟钟口脚位2 And The storage flash memory is expanded to form a connection with the controller 4 Q of the universal phase bus flashing bulk circuit circuit 5 by using the storage 16 1270785 flash memory expansion interface pin 20 - Come, the multi-purpose sequence will be expanded. The memory capacity of the flash memory volume circuit 5 can be easily expanded as needed. Furthermore, the controller 40 is the main component of the device, and the controller 4 is used to control commands and data between the universal serial bus and the host with the universal serial bus, and manage the flash memory chip. The data in the 50 and the flash memory χ 2 ,, and the controller 4 〇 is preferably a single-chip design that does not require external read-only memory (R〇M) or random access memory (RAM). 'Welcome to the universal serial bus flash memory volume body circuit 5 storage flash memory expansion interface pin 2 〇 'to connect flash memory i 2 〇 and lang sequence convergence ^ flash memory volume body circuit 5 In order to paste the extra flash memory 丨 2, it is necessary to extend the memory size, and the universal sequence bus flash memory volume circuit 5 contains at least one additional flash memory chip 5 〇, which also You can connect multiple flashing bodies 1 2 〇 to expand the amount of memory as needed. The input/output control pin of the universal sequence bus bar flash memory volume circuit 5 is provided with the other input and output controls. ° Yue Fen is shown in the second figure, which is a schematic diagram of a universal serial port circuit controller based on the specific form of the invention. The invention is a fast-to-body storage device control. The device 2 has a myriad of functions, and among these functions, the item is the control universal serial bus interface 210. 17 1270785 The logical agreement aspect consists of a system buffer in accordance with the universal sequence. The above controller 200 is in the entity and stream specification, and the controller 20 is in the FIF controller buffer. The control receives 20 Q commands and parameter packets from the host, and the packet warms are stored in a system_region 2 5 〇〇 defined by the controller 2 ,, and the control 20 〇 is also responsible for controlling and the universal sequence. The data transfer between the bus masters 'except this' control (4) 2 (10) also provides status data to the host. When the host issues a write command, it will generate a break and send it to the microprocessor 2 2 控制器 in the controller to inform the microprocessor 2 2 0 of the command, as well as the location of the command. The microprocessor 22 (for example, an 8- or 16-bit microprocessor) is the main component of the t-200, which is read from the system buffer 250. The commands and parameters of the universal sequence bus, in addition, the microprocessor 2 2 0 also executes the command with parameters. The microprocessor 22 manages and maps the universal serial bus FIFO address to the line area 2 5 Q on the one hand, and receives the money from Qian Zhilin and transmits the data to the host. In addition, the processing is 2 2 0 is also the flash memory array management (such as erase, program or item fetching commands), in addition, the microprocessor 2 2 〇 is also based on the controller 2 0 0 different method Execute the address method. Microprocessor dump memory (R〇M) 2 3 G will be built into controller 2 18 1270785 的 controller 2 GQ program code plus financial memory u AM) 2 4 〇 system controller / processing Random access memory p R . d丄0 and flash memory array interface word access The flash memory storage of the invention is further comprised of a hardware state, for 'building a host and fast Flash memory between system buffers 2 5 ;; write timing. 0 Prime Minister / 统 倾 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25

I. Reading and determining the right side of the body array 2 6 Q is the control of the flashing neon array reading and writing 'In the specific performance of the invention, this; % - a pure hardware circuit. When the system buffer 255 cache data is written to the flash memory array interface 2 6 0 'ugly (: (: circuit 2 7 0 will encode £ (: (: code, and when reading flash _ The data of the memory array to the system buffer 2 5 ◦ cache, E cc circuit 2 70 will decode the ECC code, if an E cc error occurs, E cc circuit 2 7 〇 will judge the system buffer 2 5 Q fast Take the text or byte of the towel and correct the error. Input/output control interface 2 8 0, other input/output control is required to provide the system. Please refer to the third figure, which is displayed according to the specific form of the invention. 10,000 19 1270785 with the order ship (8) touch flash coffee volume circuit of the secret frame of the lion's intention, in some of the versatile riding 羯 3 0 (10) for (four) system (such as

Wl^d〇WS and nd〇ws2〇〇〇, etc.) are included, universal serial sinks, and other operating systems may need to be installed in the host - a universal serial sink thief drive, and The sequence bus η is only used for 3 2 Q. It contains the command of receiving the main « 〇〇 and parameter ( 4 ) H 3 Q 5 through the universal serial bus interface 3 ^ ,, and the riding order and parameters are stored in the control call by 3 〇 5 & the temporary storage 11 and will generate and issue a break to inform _ that the processor has received the command. The parameter controller 3 0 5 picks up the data of the 3 依据 依据 according to the universal sequence bus logic and the physical specification and sends the data to the host 3 〇 〇. The address method 3 3 〇 contains the erase, read, and write commands of the memory_memory 3 4 Q, and the management entity-to-logic mapping. = Referring to the fourth figure, according to the specific form of the invention, the application flow diagram of the universal order ship flow agreement of the machine-like operating system is shown. When the main memory _^ 1 (four), the command and parameters are written for universal use. The sequence bus is fast 'in step: 4 22, the controller will store it in the -specific register, and 30 o's to the microprocessor, the data will then be read in step 4 Take information from the host. Let's start step 4 4 ' 'The microprocessor starts the round command according to the parameters. If the person ~, enter the command, the buffer cache will be received in step 4 5 Q with a universal order number: 20 1270785 bus Host data. The microprocessor then converts the address of the logical address to the address of the flash memory in step 406 in step 406, in step 4 7 Π Φ, Mt. The data of her flash memory or the data is written in the _ memory, if the command is a read command, the data will be transferred to the host with the oil sequence downstream in step 480. According to the standard system order, she is required to include 7 bits. Please refer to the fifth figure. BmRequest τ”_ — D 5 bits end the type of command agreement, including types and standards. As well as the vendor's "monthly flash memory device, all three types of agreements are supported. The standard type is the standard job requirement. This is a common command, such as USB-G et.

Status 〇r USB__set_Fea tu7e#〇_ b u 1 ass The flash memory storage device of the invention is spliced with a 1k/control/breaking transmission universal sequence bus. Due to the physical limitation of the flash random access memory (Ram), the erasing command must be executed before the completion of writing and inputting the period of _7, and the general flash memory needs to be removed by about 100,000 times. After that, it can work normally. Therefore, it is very important to reduce the erasing step to extend the life of the flash memory. Therefore, the invention provides a logical and physical address mapping table, and a mother/ Sub-architecture to achieve this goal. The following is the description of the logical and physical address mapping table. When the flash is started, all the blocks of 21 1270785 will be searched, and the relationship records between the searched entities and logical blocks will become logical and physical bits. The address mapping table, at the same time, the unused physical blocks are placed in the spare block for the FIFO queue to use. Then, the logical blocks in the logical and physical address mapping table are used to find the corresponding physical block address, so that the data associated with the specific physical block can be accurately written or retrieved. . Referring to the eighth figure, the block diagram of writing data into a new block according to the specific form of the invention is shown. When data is written into the flash memory, an erased block may be needed (new Block) 8; [ 〇 to replace the old block 8 〇〇, then write the data into the new block 81 ,, and finally move the data that has not been changed from the old block 800 to the new block 81 〇, This step completes the action of writing a page of data. If there are several pages of data to be written, the above steps will be repeated. Please refer to the ninth figure, which is a block diagram showing the data of the extra page according to the specific form of the invention. The specific form of the invention shows a block diagram of the data written to the extra page, the data is written into the new block 91, and the unmodified data is moved from the old block 9 to the new block 91. However, if the data is repeatedly written into the same block, many unnecessary erase and migration actions are generated, which not only wastes time, but also shrinks the life of the short flash memory. Referring to the tenth figure, the block diagram of the parent and child technology 22 1270785 is shown according to the specific form of the invention. _ 'This is a block diagram showing the parent and child technologies according to the invention form, so 'in this case In the flash memory of the invention, when the data is repeatedly written into the same-block, it will avoid the erase action, and the migration action will only be performed when the block is replaced, and all the data are written first. People new _ sub-block) i 0 1 0, then the data has not been changed, the old block (mother block) i 〇〇〇 ^ new block 1 0 1 0 in 'use this method not only extended _ memory The strangeness of the body also raises the efficiency of the device. According to the tenth 11th section, a schematic diagram showing a logical and appealing physical address mapping table according to the specific form of the invention is shown. The following is an example of writing data, and the logical and physical address mapping table is linked with an entity. The block address 丄丄0 0 and one logical block address 111〇' need to be 32 blocks (86 (^) data is written into the flash memory starting with 0/0 block/page, The total physical block/logical block is 1 0 2 4/9 9 2 'The total spare block of FIFQ is 32, and none of the blocks are mad, each block has 32 pages. According to the eleventh, thirteenth and fourteenth figures, according to the specific form of the invention, the schematic diagram of the initial indicator and the end indicator operation is displayed, and the logical and physical addresses before the unwritten person are displayed. Diagram of bribe and tail (4) 'In this example, the address of the sub-block i 3 〇〇 indicated by the initial indicator 121〇 is 0 3 E ◦ h is taken from the FIF 〇 spare area 2 〇〇, then the starting indicator The address of 1210 will increase to become the starting indicator i 4 i Q, and the data of 32 pages will be written into the sub-block 13 0 。. 23 !27〇785 and then sub-block 13 Ο 0 address 〇3 e 〇h filled in the logic block and the logical block address of the parent block 131Q 〇〇〇Qh 焉 address map 3 1 〇 address ◦ QQQ h is wiped, and the tail end The index i 2 = after block 1 'the parent block address 〇〇〇〇 h is filled in the spare area 0 増 plus 'the address indicated by 0. · Indicator 14 2 will now be based on the specific performance of the invention , the production of 窎. ”,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, As shown in the figure, according to the specific form of the invention, the writing program of the flash memory volume circuit of the universal serial bus is displayed, and the logic bit sent by the host in step 6 Ο 1 is displayed. The address is converted into a flash memory physical block and a page address. Then in step 602, the controller checks to see if the sub-block exists. If the sub-block does not exist, then skip to step 6 〇5, if the sub- The block exists, and in the step Lu 6 y 3, the logical block of the existing side memory is checked and treated. Whether writing a person is equal to taking a memory block of the memory of the person, and skipping to step 6 ^ 1 〇 if equal' will check the existing flash memory logical page number in step 6 ,4, see Whether the written is greater than the last-written person's flash clock logical page, and if so, continue to step 61, if not, then skip to step 6. 24 1270785 Step 6 0 5 Take one from the FIF queue The clean block creates a sub-block for the existing write command. In step 6 0 6 check the existing flash memory logical page number to see if the write is equal to "0", and if it is equal to "0", continue to step 608. . If it is not equal to "0", in step 607, the data of the parent block is moved to the sub-block between "the last page written" and "the existing write page". In step 608, the data from the host to the flash memory is written into the buffer, and the count of the cell block is reduced. In step 60, 9, if the cell block count is equal to "〇", then proceed to "end point", if not, proceed to step 6 0 8. In step 610, if the existing write page number is equal to the last written page number processing, proceed to step 6 0 8. If not, continue to step 6 〇 7. In step 611, the data of the parent block is moved to the sub-block between the "last page written" and the last page of the block, and the parent block is erased and updated in the controller. Lai and the entity Jianying practice, replacing the parent block address with the sub-block block', and put the erased parent block back into the F j F◦ column as a clean block. ^月彡看七图图' is based on the specific form of the invention to show that the flash memory storage material is light, this is still clear that the specific form does not show flash memory compared to the reading Procedure flow chart. In /Step 7 〇 1, in order to convert the host address of the universal serial bus to 25 1270785 into a flash memory entity and a page address. In step 702, check the existing flash memory to see if the read is equal to the last read flash memory logic block. If yes, skip to step 7 〇5. If no, continue to step 7 〇 3. The data of the flash memory block and page is read in step 703, and the count of the block is reduced. In step 704, the cell block count is checked to see if it is equal to "〇". If it is equal to "0", it proceeds to "end point", and if not, it returns to step 7 〇 3. In step 705, the existing memory logical page is checked to see if the read is greater than the last written person's flash memory logical page. If yes, go back to step 7 〇 3, and if no, proceed to step 7 〇 6. ▲ The data of the sub-block entity_item is read in step 7 Q6, and the count of the cell is reduced. 〇7 Check the cell block count to see if it is equal to "〇", =〇", then proceed to "end point", if not, go back to step 7〇5. According to the fifteenth figure, according to the specific form of the invention, the life of the a, the eucalyptus structure is not exhausted, and when the microprocessor starts to execute the command, the flash memory volume I# Thunder A sequence bus map is displayed. Face command packet.鸠^取或写,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, LBA) and circle 26 1270785 Start cell block (CHS) mode. If the host_LBA mode provides an address, the device will convert it to c H S mode and then change the cH S mode to a physical address. When the universal sequence bus line flash memory volume circuit executes the read command, the controller firstly stores (4) the data of the memory - a block of cells - a buffer of the cell block controller (5 i 2 group). Then the universal sequence sinking two engine will send the cell block to the host. When the number of cell blocks sent to the host is equal to the number of cell blocks that the host wants to read, the entire command is completed. Ludang universal serial bus flash memory volume body circuit write command when the ten system will use the universal sequence bus engine to read the host data - a block of a block to the controller's buffer (5 work 2 bytes), then the cell block will be stored in the flash memory, when the number of cell blocks sent to the flash memory is less than the number of cells to be written by the host, the entire command is completed. In the invention, a plurality of wafer selection legs are provided, and when the device is activated, the memory will be flashed. The memory expansion interface is connected to the flash memory class =: and the system has!! A flash memory 'device will find the total valley 罝' when the host needs this type of data, 10,000 = column The bus flash memory volume circuit provides the total capacity to the host instead of the capacity of a single flash memory. When the host sends a certain address (logic) to the universal sequence bus flash memory 27 1270785 integrated circuit, the universal sequence bus flash memory volume circuit performs calculation to find out what the host wants to access. The exact chip, and the corresponding address, then the device will use the different address and start the wafer pick. In addition, the flash memory chip and the controller described in the present invention are designed as a single chip to reduce the overall S product of the universal sequence bus flash memory rhythm circuit, and do not require external random access memory. The design of ram or OM. For those who have skilled technology, the scope and spirit of the original invention are carried out in accordance with the scope of the original invention, and the purpose of this is to make a modification and change in the following In the pre-conditions, the invention encompasses the scope of the invention and its equivalent meanings and variations. 28 1270785 [Simple description of the drawings] The first figure is a schematic diagram of the layout of the flash memory volume body of the universal serial bus according to the specific form of the invention. The second figure is a schematic diagram of a universal sequence bus flash memory volume circuit controller according to the specific form of the invention. The third figure is a schematic diagram of a system architecture block of a flash memory volume circuit of a universal serial bus according to the specific form of the invention. The fourth figure is a schematic diagram of the application flow of the universal sequence bus arrangement agreement for various operating systems according to the specific form of the invention. The fifth figure shows the table parameters of the universal sequence bus arrangement in the flash memory volume circuit of the universal sequence bus according to the specific form of the invention. The sixth figure shows the writing procedure of the universal sequence bus flash memory volume circuit according to the specific form of the invention. The seventh figure shows the reading procedure of the universal sequence bus flash memory volume circuit according to the specific form of the invention. The eighth figure shows a block diagram of writing data into a new block in accordance with the specific form of the invention. The ninth figure is a block diagram showing the data written to an extra page in accordance with the specific form of the invention. 29 1270785 The tenth figure is based on the specific form of the invention, and the block diagram of the parent and sub-technical. FIG. 11 is a schematic view of the invention. The display logic and physical address mapping tables are not intended to be specific to the invention. The figure shows the starting index and the tail end index as the fourteenth figure. The schematic diagram of the specific body address mapping table according to the invention is a schematic diagram of the specific industry according to the invention. The form shows the logic and the actual before the write. The 7F start and end indicators are also displayed.

The fifteenth figure shows the structure of the command packet according to the specific form of the invention.

Main component symbol description 10, universal serial bus connector 12 0, flash memory 20 2〇〇2 1 〇, system buffer, flash memory array interface flash memory expansion interface pin, controller 2 5 〇

Universal serial bus interface 2 6 Q 30 1270785 2 2 0, microprocessor 2 7 0, ECC circuit 2 3 0, read-only memory (ROM) 2 8 0, input/output control interface 2 4 0, random Access memory (RAM) 3 0, input/output control pin 3 0 0, host 3 3 0, address method 3 0 5, parameter controller 3 4 0, flash memory 310, universal sequence bus Interface 3 2 0, universal sequence bus arrangement command implementation 40, controller 5, universal sequence bus bar flash memory volume body circuit 50, flash memory chip 31

Claims (1)

1270785 卜, the scope of application for patents ··,: a variety of universal serial bus flash memory volume body circuit, the controller and the evening storage (four) remember the marrow crystal #封钱-particle circuit, used to The command and data between the host computer and the flash memory device; the package inspection includes: the universal serial bus (USB) for connecting the universal sequence check flash to the 5 volume memory circuit Universal phase bus (USB) host _ 9 memory flash memory expansion interface pin, so that the universal sequence bus flash memory volume circuit can be external storage flash memory to increase capacity; The SB controller's V-output control pin enables the Universal Sequence 2 channel to be used for other applications. Body 2 special consumption of the universal serial bus bus flash memory volume as described in item 1. To = step into the step contains the V output control interface 'providing the system to enter other input / output control. 3 The universal sequence sinking circuit described in the first item 'in step-by-step contains a foot with a flash memory expansion interface 1 extended fine and fine _ _ memory size 4, such as The universal circuit described in the third paragraph of the patent application includes, in a step-by-step manner, the buffer between the host and the flash memory 32 1270785 memory device. The serial bus flash memory volume circuit described in claim 1 of the patent application includes a state machine to establish read and write timing for the system buffer. The universal serial bus flash memory volume circuit described above further includes an error correction code (ECC) circuit 'to encode E cc when data is written to the flash memory device, and to flash when reading The data of the memory device is decoded by E c C., H 7. The universal serial bus flash memory volume circuit as described in claim 6 wherein the ECC circuit further includes when the correction occurs. Invalid number when an error occurs The judgment of the address. 8. The universal sequence bus flash memory volume circuit as described in the scope of patent application 其中1, which further includes a flash memory interface to control the delivery to at least one fast Flash memory read and write commands 9. As described in the patent scope 帛!, the universal sequence bus flash memory volume body circuit, in which flash memory crystals > 5, the controller is - Single Crystal>[Designed to reduce the overall volume of the flash memory storage device. ! 〇, as described in the patent application 帛1, the universal sequence of the flash memory volume circuit's step-by-step includes A microprocessor is used to execute the host with the number of commands. ^ i1, as described in the patent scope, i.e., the universal sequence bus flash memory 33, -3⁄4 way, wherein the control is the control host And flash memory, the data of the spoon, and the management of at least one of the data in the flash memory, /, the controller in the step _ step contains ~ · ~ eight ~ Tuhuadan number of orders / system, k-rush area, between money and flash memory devices Buffer; universal sequence bus flash memory volume circuit, in which the universal sequence is called the state machine of the volume circuit to establish the read and write timing for the system buffer., = please special plane, (4) m-slot flash memory The p-circuit, wherein the control 11 is a single-wafer design that does not require external random access memory (-am) or read-only memory (R〇M).: a universal serial bus bus flash memory volume circuit, Contains: : = = use serial bus (USB) to connect the universal serial bus fast volume circuit to the host; at least - a flash memory to store data; 1 flash brother to remember the body interface, read The fetch and write command; from the transport to at least one of the flash memory modules, a flash memory expansion interface, connecting the 10,000-body circuit to the extended memory, using the serial bus flash memory volume 10,000 sequence Bus interface, as the Hummer host and the flash memory interface between the ~ surface 'ring (four) Qing sequence confluence 34 1270785, flash memory circuit _ command and data, and manage at least the data in the flash memory The controller further includes: a buffer that provides a buffer between the sequenced stream interface and the flash memory interface; the microprocessor 'reads the commands and parameters of the system buffer, and executes Most commands; and - state machines, for system buffer fetch and write timing. Becker 4 t applied for the special 13th reward of the Vanke Lai flow flash memory _ - integrated circuit 'where the controller controls the data to and from the host. The second application of the universal range bus as described in the thirteenth patent scope, the flashing secret volume circuit, wherein the controller controls the 10,000 serial bus interface, such as the scope of patent application! The three-purpose universal ship bank volume circuit described in the 'the controller receives the command from the host. ... 7, :=fan=,_sequence__memory The volume body circuit in which the controller provides the status to the host. See 8, for example, apply for the system of the full-scale three-phase system, in which the microprocessor reads the system buffer command: ^ y, as described in the patent scope i i 3 A flashing syllabary volume circuit in which the microprocessor executes a parameter a Μ- Μ, as described in the patent range i i 3, the universal sequence sink • fast ring memory 35 1270785 volume body circuit The microprocessor-side receives the data of the host or transmits the data to the host's side management and maps the address to the system buffer 2. The fast-moving memory module management, Such as technical division, program or read commands. 2 2. The method of claim 4, wherein the microprocessor executes the bit I method according to the algorithm of the controller. Repair 2 ===13 described in the __ fast _ volume body circuit's towel micro-processing material county _ district address. 2 4, such as the W1 item of the application (4) the coffee volume circuit, wherein the microprocessor further includes: 丨, flash 仏 a read-only memory called the control H program code (r〇二二控制器The random access memory used when executing the command (r 2 5, as in the patent application scope 丄3 volume body circuit, step-by-step 4 with sequence bus bar flash memory extended universal sequence bus bar fast = two fast memory The body expands the interface to the memory of the volume circuit.