TWI268545B - Method of forming semiconductor structures - Google Patents
Method of forming semiconductor structuresInfo
- Publication number
- TWI268545B TWI268545B TW094143039A TW94143039A TWI268545B TW I268545 B TWI268545 B TW I268545B TW 094143039 A TW094143039 A TW 094143039A TW 94143039 A TW94143039 A TW 94143039A TW I268545 B TWI268545 B TW I268545B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- photo resist
- semiconductor structures
- formed over
- dummy patterns
- Prior art date
Links
Classifications
-
- H10D64/01326—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/917—Deep level dopants, e.g. gold, chromium, iron or nickel
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/012,414 US7432179B2 (en) | 2004-12-15 | 2004-12-15 | Controlling gate formation by removing dummy gate structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200620415A TW200620415A (en) | 2006-06-16 |
| TWI268545B true TWI268545B (en) | 2006-12-11 |
Family
ID=36584515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW094143039A TWI268545B (en) | 2004-12-15 | 2005-12-06 | Method of forming semiconductor structures |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7432179B2 (zh) |
| CN (1) | CN100454500C (zh) |
| TW (1) | TWI268545B (zh) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9070623B2 (en) * | 2004-12-15 | 2015-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling gate formation for high density cell layout |
| US7432179B2 (en) * | 2004-12-15 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling gate formation by removing dummy gate structures |
| JP2008227076A (ja) * | 2007-03-12 | 2008-09-25 | Nec Electronics Corp | 半導体装置 |
| KR101286644B1 (ko) * | 2007-11-08 | 2013-07-22 | 삼성전자주식회사 | 더미 게이트부를 포함한 반도체 소자 및 그 제조방법 |
| US7939384B2 (en) * | 2008-12-19 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Eliminating poly uni-direction line-end shortening using second cut |
| US8685808B2 (en) | 2011-09-28 | 2014-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device fabrication method |
| US9236379B2 (en) | 2011-09-28 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabrication method thereof |
| KR102279711B1 (ko) | 2014-03-11 | 2021-07-21 | 삼성전자주식회사 | 반도체 장치의 레이아웃 방법, 포토 마스크 및 이를 이용하여 제조된 반도체 장치 |
| US9607988B2 (en) * | 2015-01-30 | 2017-03-28 | Qualcomm Incorporated | Off-center gate cut |
| US11063006B1 (en) * | 2020-02-21 | 2021-07-13 | Nanya Technology Corporation | Semiconductor device structure with fine patterns forming varied height spacer and method for forming the same |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183345A (ja) * | 1993-12-24 | 1995-07-21 | Nec Corp | 半導体装置 |
| TW329563B (en) * | 1996-06-01 | 1998-04-11 | Winbond Electronics Corp | The manufacturing method for load resistors of SRAM |
| KR100192521B1 (ko) * | 1996-07-19 | 1999-06-15 | 구본준 | 반도체장치의 제조방법 |
| JP3495869B2 (ja) * | 1997-01-07 | 2004-02-09 | 株式会社東芝 | 半導体装置の製造方法 |
| SE519628C2 (sv) * | 1997-03-04 | 2003-03-18 | Ericsson Telefon Ab L M | Tillverkningsförfarande för halvledarkomponent med deponering av selektivt utformat material,vilket är ogenomträngligt för dopjoner |
| US6103592A (en) * | 1997-05-01 | 2000-08-15 | International Business Machines Corp. | Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas |
| JP3466874B2 (ja) * | 1997-06-11 | 2003-11-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6287904B1 (en) * | 2000-01-27 | 2001-09-11 | Advanced Micro Devices, Inc. | Two step mask process to eliminate gate end cap shortening |
| JP2002270538A (ja) * | 2001-03-12 | 2002-09-20 | Matsushita Electric Ind Co Ltd | ゲート電極の形成方法 |
| US6461906B1 (en) * | 2001-03-14 | 2002-10-08 | Macronix International Co., Ltd. | Method for forming memory cell by using a dummy polysilicon layer |
| TW567575B (en) * | 2001-03-29 | 2003-12-21 | Toshiba Corp | Fabrication method of semiconductor device and semiconductor device |
| US6492073B1 (en) * | 2001-04-23 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Removal of line end shortening in microlithography and mask set for removal |
| US6624068B2 (en) * | 2001-08-24 | 2003-09-23 | Texas Instruments Incorporated | Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography |
| US6787469B2 (en) | 2001-12-28 | 2004-09-07 | Texas Instruments Incorporated | Double pattern and etch of poly with hard mask |
| US6944844B2 (en) * | 2002-04-03 | 2005-09-13 | Synopsys, Inc. | System and method to determine impact of line end shortening |
| JP3759924B2 (ja) * | 2002-11-21 | 2006-03-29 | 松下電器産業株式会社 | 半導体装置 |
| US7432179B2 (en) * | 2004-12-15 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling gate formation by removing dummy gate structures |
| US7795080B2 (en) | 2007-01-15 | 2010-09-14 | Sandisk Corporation | Methods of forming integrated circuit devices using composite spacer structures |
| US7821039B2 (en) | 2008-06-23 | 2010-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout architecture for improving circuit performance |
| US7939384B2 (en) | 2008-12-19 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Eliminating poly uni-direction line-end shortening using second cut |
-
2004
- 2004-12-15 US US11/012,414 patent/US7432179B2/en not_active Expired - Fee Related
-
2005
- 2005-12-06 TW TW094143039A patent/TWI268545B/zh not_active IP Right Cessation
- 2005-12-15 CN CNB200510131807XA patent/CN100454500C/zh not_active Expired - Fee Related
-
2008
- 2008-08-18 US US12/193,538 patent/US8105929B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20060128082A1 (en) | 2006-06-15 |
| US7432179B2 (en) | 2008-10-07 |
| CN100454500C (zh) | 2009-01-21 |
| US20080305599A1 (en) | 2008-12-11 |
| US8105929B2 (en) | 2012-01-31 |
| TW200620415A (en) | 2006-06-16 |
| CN1812062A (zh) | 2006-08-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |