TWI267760B - Method of forecasting unit capacitance for chip design - Google Patents

Abstract

A method of forecasting a unit capacitance of a chip having a plurality of layers. Each layer includes a predetermined layout of metal lines. First, layout design parameters of the predetermined layout are obtained before forming the chip, such as number of layout layers, metal line width of each layout layer, distance between each metal line and the ratio of metal lines to routing channels. Next, a testing interconnection according to the layout design parameters is generated. Finally, the unit capacitance is obtained by a predetermined capacitance extraction tool according to the testing interconnection.

Description

1267760 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) [Technical Field to Be Invented by the Invention] The present invention relates to a technique for extracting a specific circuit, and more particularly to a technique for predicting the length of a metal of a wafer. The unit capacity of the predicted metal structure is applied to the wafer design flow. (4) The length of the interconnecting unit is [Previous] In the case of t metal or polycrystalline sprite inside the integrated circuit, the internal connection capacitance caused by the internal wiring is reported to be the design bottleneck of the circuit. Accurately simulate the integrated body: it is able to evaluate the above metal interconnect capacitance. μ '' In the past, many on-ch testing structures have been used in an attempt to obtain higher accuracy capacitance evaluation results. However, the traditional test structure has (4) line points, which leads to the measurement of the metal interconnect capacitance is not accurate. J. US Patent No. 63 1 296 is the method of the internal program parameters. This method uses a test structure of two::::: to simulate the target layout. After that, according to;; cloth ... connection process parameters include 4 genera: = system = and here, the relevant information of the capacitor. Layers are produced between different layers of metal wires. However, the traditional method is based on the observation of θ y, and the execution of the # 之 之 # 日 日 κ 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 片The result of the weeping is "whether the Japanese and Japanese films meet the requirements", and the standards set by the test will be based on the test structure test; ΐ;; page 5 0697-8886TWF (η1); Ρ 2002-046; ROBERT.ptd 1267760

The process parameters of the target wafer. However, in general, the conventional layout is relatively simple, so the actual state of use does not match, so at the time of analysis, since a large number of time slices have been consumed, it is too late when the target wafer manufacturing completes the setting error. SUMMARY OF THE INVENTION The test structure of the above test structure used in the method is generally meaningless to the result of the target wafer. Moreover, the metal interconnect process parameters were discovered after the fabrication and the above-mentioned target crystal formation.

In view of the above, in order to solve the above problems, the main object of the present invention is to manufacture or simulate a test structure according to a layout parameter of a predetermined wafer metal interconnect layout to predict a unit length electric valley of a predetermined wafer metal interconnect layout. value. The layout parameters include the number of layers of the predetermined chip metal interconnect layout for the wiring, the width of the metal lines of each metal line, and the ratio of the outgoing metal lines between the metal lines to the wiring channels of the metal layers. The test structure formed according to the layout parameters of the wafer metal = wiring layout will have a layout that is quite close to the layout of a given wafer metal interconnect. After forming the test structure, the electric valley extraction software is used to retrieve the unit length capacitance value of the test structure. Then, the obtained unit length capacitance is used as a basis for the design procedure of the 丨c, for example, in the steps of logic synthesis, floor plan, and ci〇ck tree synthesis. Therefore, the unit length capacitance of the wafer fabricated according to the above IC design steps will approach the unit length capacitance previously predicted by the test structure, thereby accelerating the convergence of the IC design flow. In order to achieve the above object, the present invention proposes an estimation target wafer

0697-8886TWF(η1);Ρ2002-046;ROBERT.p t d Page 6 1267760

The method of metal interconnecting the capacitance per unit length, the target wafer has a plurality of metal layers, and each metal layer has a predetermined metal line layout rule, including the following steps. First, before forming the target wafer, the layout design parameters of each metal layer of the target wafer are obtained in advance, and the layout design parameters include the number of layers of the wiring of the inner metal of the wafer, the width of the metal lines of each metal wire, and the distance between the metals. The metal wire wiring occupies the proportion of the wiring channels of each metal layer, and then 'the corresponding simulated metal interconnection layout is randomly generated according to the layout design parameters. Finally, the specific metal extraction wire is used to obtain the unit metal between the metal layers according to the simulated metal interconnection layout. The capacitance value of the line length. [Embodiment]

Embodiments: The 1C program includes a logic synthesis step (i〇gic synthesis), a component plan (floor plan), and a clock network synthesis (cl〇ck tree synthesis), and routing, and the like, and then

A target wafer can be formed. The present invention provides a method for predicting the capacitance per unit length of each layer of a target wafer according to layout parameters, and using the predicted unit length electric valley value as a basis for execution of relevant steps of the IC design, such as a floor plan and a clock. Net synthesis (cl〇ck tree synthesis) and other steps. Therefore, in the end, a wafer having a unit length capacitance value close to the previously predicted capacitance value can be designed, and the IC design step is designed based on the previously predicted unit length capacitance value, thereby accelerating the convergence of the wafer design. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the operation of a method for estimating the capacitance value per unit length of a target wafer metal according to an embodiment of the present invention. First, at

1267760 V. INSTRUCTIONS (4) Before forming a wafer, pre-acquisition of each metal layer in the wafer (ie layout design parameter (si) 'The above layout design parameters include the layout of the wiring for the number of layers of the wiring, the metal line of each metal wire wiring The distance between the wires, the wire routing of each metal layer, and then the corresponding mode (S2) are randomly generated according to the layout design parameters. In the present invention, the analog interconnect layout can be generated by the machine, such as IpeTestPatGen.

In the four-layer metal wiring process, the sMET2 unit length is taken as an example, and the second to second images are shown in the wafer, and the $line layout. 2A shows that the layout of the wafer *MET1 shows the layout of MET2 in the wafer, the 2C shows the wafer office, the 2D shows the layout of the MET4 in the wafer, and the 2E shows the MET1+MET2 + MET3 + MET4 complete layout top view. For example, the four-layer metal wiring process is not from the second layer to the second layer from the first layer to the fourth layer. The 2E figure shows the complete layout. In general, the metal lines in the odd-numbered layers are along the water (as shown in Figures 2A and 2C) and in the vertical direction of the even-numbered layers (as shown in Figures 2B and 2D). The metal wires are all arranged in a cloth extending in a horizontal or vertical direction and the distance between adjacent wiring cells is indicated by reference numeral 24. Therefore, after the setting of the local parameters, the analog metal interconnect wiring can be generated. If the simulated metal interconnect layout is generated by a program, an example of the program input content of the proposed interconnect layout is given. Here, the program input of the MET 1 and MET2 unit length capacitance values is taken as an example.

Hi 0697-8886TWF(nl); P2002-046; ROBERT.ptd is the wafer metal inner line width and gold channel ratio for each layer). The in-line connection is a specific program with the capacitance value of the same layer of metal. In Fig. 2B, the layout of MET3 shows the crystal. Here, the metal line system is arranged in the horizontal direction in the order of the layout. In addition, the layers are on the line 2 2, according to the above layout. The next is to generate the model to decide separately

Page 8 1267760 V. Description of invention (5)

«LAYER DEFINITION

#layerNarae * layerNo routing—grid ♦LAYER MET1 * 8 0.8 MET2 *10 0.86 MET3 =13 0.8 MET4 -15 0.86 *ENDLAYER < // MET1

MODEL = ROUTING-LINE TOP_LAYER=HET4 ROUTING WIDTH=0.40 HORI UTILIZATICW = 50 TOP_LAYER=HET3 ROUTING UIDTH=0.42 VERT UTILIZATICN = 50 TOP_LAYER=HET2 ROUTING UIDTH=0.40 HORI UTILIZATICN = 50 HID_LAYER=HET1 UIDTH=0.32 PITCH-1 UTIL=50 PITCH-2—UTIL=50 } { // MET2

MODEL = ROUTING LINE TOP a LAYER=HET4 ROUTING UIDTH=0.40 VERT UTILIZATICN = 50 TOP_LAYER=MET3 ROUTING WIDTH=0.42 HORI UTILIZATICN = 50 HID__LAYER=MET2 UIDTH=0.40 PITCH-1lUTIL=50 PITCH-2 UTIL= 50 BOT LAYER=HET1 ROUTING UIDTH=0.32 HORI UTILIZATICN = 50 According to the above program input, each layer of simulated metal can be generated by software.

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The layout and the layout are as shown in Figs. 2A to 2DG, and the top view of the above-described simulated metal interconnection layout result is as shown in Fig. 2E. Down, the capacitance of the upper interconnect layout can be obtained by extracting the software with a specific capacitance, and converted into a capacitance value per unit length (S3). Here, the capacitance extraction software can be Raphael, Star Rc, Xcal ibre, and DRACULA.

The capacitance per unit length is a very important reference parameter for IC design, especially in the component configuration (fl〇0r pi ail) and cjock tree synthesis. If the unit length electric valley of the wafer can be predetermined, the designer can adjust the position of the circuit component configuration based on the unit length capacitance value. According to the experimental data, the wafer designed according to the wafer design method disclosed in the embodiment of the present invention has been experimentally tested, and its unit length capacitance is quite close to the unit length capacitance value previously predicted by the analog interconnection layout. Therefore, the I匕 design convergence is effectively accelerated. Fig. 3 is a graph showing the relationship between the number of connections (N e t ) and the estimated capacitance of the pre-wired prediction and the ratio of the capacitance measured after wiring using the method according to the embodiment of the present invention. Here, the number of links represents the number of metal wires having a driving relationship between the components. According to the experimental results shown in Figure 3,

It can be found that the estimated value obtained by the unit length capacitance prediction method using the metal interconnect layout of the present invention is close to the actual value measured after wiring. Most of the errors are within ± 10%, which is an acceptable margin of error. Furthermore, as shown in the figure, the greater the number of links, the better the convergence of the predictions. The method of the present invention is shown to provide a fairly accurate estimate of the unit capacitance value under a large number of samples.

〇697-8886TW(nl) ;P2002-046;ROBERT.ptd Page 10 V. Description of the invention (7) As described above, the layout parameters of the hairline layout to the layout of the metal interconnection of the wafer metal interconnect layout Line width, channel ratio between metal lines. The layout is close according to the wafer test structure'. In the formation of the test structure test structure of the unit length of capacitance as a 1C design program (logic synthesis: c 10 ck according to the test structure designed by the above steps to predict the proud system provides a manufacturing or simulation unit The length of the length of the electrical supply wiring, the metal metal interconnection cloth and the predetermined wafer gold can be used to obtain the capacitance value. Then, for example, |, the component configuration tree synthes the unit length per unit length capacitance according to the test knot The capacity of the cloth and the wiring of each gold wire is the internal capacitance of the cloth, and the floor is equal capacitance.

疋 构 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , It will be accelerated that the 1C metal interconnect prediction is intended to include the splicing of the metal layer wiring of a given line to take the unit length step, and thus, the present invention is disclosed in the preferred embodiment. As above, it is not intended to limit: invention: scope, any person skilled in the art, without departing from the invention: within the scope of the moon and the scope, when a little change and retouching can be done, so the scope of protection of the present invention This is subject to the definition of the scope of the patent application. x

BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment of the present invention is exemplified by a program input for determining a capacitance value per unit length of MET2. The detailed description is as follows: Description of the drawings: Fig. 1 is a flow chart showing the operation of the method for estimating the target unit unit length capacitance value according to the embodiment of the present invention. Figure 2A shows the layout of meT1 in the wafer. Figure 2B shows the layout of MET2 in the wafer. Figure 2C shows the layout of MET3 in the wafer. The 2D image shows the layout of MET4 in the wafer. The second map shows the top view of the wafer center 1 [1 + ^ 12 + 1 ^ D 3 + ^ D 4 complete layout. Figure 3 is a diagram showing the relationship between the number of (Ne t ) and the predicted capacitance of the pre-wired prediction and the ratio of the capacitance measured after the wiring in the method according to the embodiment of the present invention. Symbol Description: 2 2~Wiring grid 2 4~Wiring grid

Claims (1)

* i · a method for estimating the metal line layout of the above-mentioned target, in the layout of the metal layer, the distance between the wiring lines for laying the metal lines; according to the layout of the cloth; and obtaining the metal layers according to the mold 2 · If you apply for the internal connection unit length layout is made by a specific process 3 · If you apply for an internal connection unit length 1 peTestPatGen ° "Day, sheet metal connection line unit length capacitance #: Jing I County has a plurality of metals The layer, each metal layer is formed to include the following steps: Before the standard wafer, the target wafer preparation parameters are obtained in advance, and the layout design parameters include the number of layers of the metal wire of the wafer, the width of the metal line of the metal wire, the distance, and the metal. The wire wiring occupies the metal interconnect routing channel and the corresponding design of the analog interconnect inner metal wire interconnect layout using a specific capacitance to extract the capacitance value of the soft unit metal wire length. A method for the metal capacitance value of a target wafer, wherein the above-mentioned simulated metal interconnection type is randomly generated. Method metal wafer capacitance value, wherein the specific program is 4. The method of estimating the metal interconnect length per unit capacitance value of the target wafer as described in claim 1, wherein the specific capacitance extraction software is one of Raphael, Star-RC, Xcalibre, and DRACULA. 0697-8886TWF2(η1);Ρ2002-046;ROBERT.p t c第13页