TWI266070B - Chip-level design under test verification environment and method thereof - Google Patents

Abstract

A chip-level design under test verification environment and a method thereof are provided. The verification environment comprises a test pattern mechanism, an input mechanism, a behavior module, a comparison output mechanism and a verification environment interface. A test pattern is provided by the test pattern mechanism, and a design under test (DUT) is inputted by the input mechanism. The behavior module receives the test pattern to simulate ideal state of the DUT based on test pattern operation. The comparison output mechanism is used to compare the behavior module and the results from DUT based on test pattern operation. The verification environment interface is coupled with the DUT to output in real time the verification state of the DUT, the state of the verification environment and the state of adjusting verification environment in the verification process. With the above steps, it is able to effectively improve verification efficiency and verification report quality.

Description

1266070 V. INSTRUCTIONS (1) -- [Technical Fields of the Invention] This 'Xue Yue's is about a wafer-level test object verification environment and method, especially for a wafer-level test that can provide interaction with the outside world. Physical verification environment and method. [Prior Art] In general, electronic products are mass-produced after the process. In the ring of ° is usually first software

(design under test, DUT into the test pattern (test pattern requirements. At the beginning of the design, will pass the so-called design process, verification is very important analog electronic products, that is, the object to be tested) circuit layout, and then After the test object is carried out to verify whether the object to be tested conforms to the design of the object to be tested, it is better to compare the simulations. Please use the analog load module 123 (the result of the simulation is taken as an example of a test object of the analog chip level (CHIP-level). The general wafer level simulation method is to load the test pattern into the object to be tested by the simulator. The output of the object to be tested 'checks whether the output result is correct. The environment (simulation environment) will check the action, that is, the result of the object to be tested will automatically be compared with the expected result. The simulator is used to provide a sample of the object to be tested. The test pattern mechanism 121 uses the input mechanism 丨2 to simulate the object to be tested 1 2 5 and simulates the row of the ideal object of the object to be tested * Then 'compare the output mechanism 1 24 The comparison test pattern ^^别' 待 the test object 125 and the action module 123 after the round-out result, the output mechanism 丨 24 will output the verification result, wherein the mechanism is established by the verification software programming language used by the device.

Page 5 1266070 V. Description of the invention (2) Before the wafer has not completed the layout and winding (p&R), it is mainly verified for the functionality of the wafer, usually called the front-end simulation (Pre-Simulati0n). The loaded test pattern is mainly for verifying whether the functions of the object to be tested 125 are correct. After the wafer completes P&R, it will perform post-simulation (p〇st_emulation) in this verification environment. In addition to verifying the function of the wafer, the loaded test pattern also checks the object to be tested. Line logic layout ^layout) Timing of the circuit. During the verification period, the verification will be taken in the verification process, which may be used in the message file, called the message output (print 〇ut) or directly save the nickname waveform (waveform) . However, the message is output. = The message is too large and the number is none (4), and too much useless message will make the report readability. Directly storing the signal waveform consumes a large amount of hard disk space, which slows down the simulation. s In addition, due to the increasing complexity of the chip design, the verification time will increase. In some cases, the test will be single and long. In addition to the further: the amount of data that will last for several days, or the amount of data in the waveform, during the verification process, the engineer responsible for verification has the latest status, progress, and even the test strip in the middle; The verification method of the conventional method, when the test pattern is loaded into the simulation simulation environment, the simulation environment represents the ^^ owing time--the office is unable to reach the dynamic adjustment verification. The verification condition of the table 2 cannot be changed, and the simulation is performed in the latter stage. If the object to be tested is not normal (uming vi〇UU〇n), or the object to be tested is stuck (dead 1266070)

V. INSTRUCTIONS (3) Authentic i ί Γ 2 Ϊ When the device is idling for unknown reasons, in the case of nowhere: part of the message... Stop the test, μ wastes the test verification time. If you decide to force the inspection process. The method is used to test the final part of the pattern to verify the final output. The output result is related to the timing. Therefore, the calculation is usually performed by the time delay of the large and the 辑1. Because the amount of calculation ^ = the time of the simulation increases a lot, if the output is verified by the graph's side. Simulator and workstation hard disk load 'Impact = 4α. The present invention proposes a wafer level test object verification environment to shake the second: to obtain real-time information within the simulated environment to grasp whether the Γ Γ Ι Ϊ Moreover, there is no need to continuously output simulations during the verification process, which reduces the readability of the verification report; and reduces the chance of saving the waveform to increase the simulation performance. SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a verification environment of a chip-level design under test (DUT), which has a test pattern mechanism (mechanism), Input the machine 匕 ^, set to 杈, and, compare output mechanism, and verify the environment interface. The test pattern mechanism is used to provide a test pattern. Input mechanism / use, input the test pattern into the object to be tested. The behavior module is to receive the test pattern: to simulate the ideal state of the object to be tested according to the test pattern. Compare output ^ to

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:: The module and the test object are tested according to the test pattern. The $% interface is coupled to the object to be tested to output the verification status of the object to be tested in real time. In the preferred embodiment, the verification environment interface is coupled to at least one of the test pattern mechanism, the input mechanism, the behavior module, and the comparison rounding mechanism, respectively, for instant verification during the verification process. Output verification status and adjust the status of the verification environment. In a preferred embodiment of the invention, the verification environment can be provided using an electronic design automation language such as Open Vera. Correspondingly, the verification environment interface is provided by the VSV function. As for the interaction between the verification environment interface and the outside world, the interactive function group of the VSV function can be called through the human-machine interface program of the C language to complete the interaction between the verification environment interface and the outside world. Another main object of the present invention is to provide a method for verifying a wafer level test object, which includes: S for the test pattern to be loaded (4) and the behavior mode, and /, the middle behavior module is used to simulate the test object according to the test The ideal state of the pattern operation ° #, compare the behavior module and the object to be tested according to the results of the test pattern operation. Finally, the comparison result is output. And wherein, in the verification process, the verification state of the object to be tested is output when the environment interface (4) is verified. In view of the above, the present invention provides a wafer level test object verification environment and method 'It is provided by the interaction interface provided during verification, and interacts with the simulation to obtain the instant real-time m, to grasp whether it can be mentioned. : End: 匕: The message that is intended to be rotated through this interface will not be tainted: verify the address: μ and save the waveform when the timing of the object under test is abnormal to increase the simulation performance.

V. Description of the Invention (5) [Embodiment] The simulator simulates the object to be tested and loads the test pattern to measure the object, and in order to: get the inside of the simulator for some of the information in the process, The simulation environment can be interacted to evaluate the efficiency of the verification in order to improve the efficiency of the verification. The interface of the invention provides an interaction with the outside world - the simulator of each process inside the simulator Internal processes generate interactions to dynamically align and maintain a virtual environment. Therefore, by this, it is possible to optimize the efficiency of the entire verification in the process, especially the efficiency of the test. In order to enable the reviewing committee to have a more in-depth understanding and understanding of the features, objects and functions of the present invention, the detailed description of the drawings is as follows. Please refer to FIG. 2, which is a preferred embodiment of the present invention. The method of verification is not thinking. In FIG. 2, if an interface 210 that can interact with the simulator internal mechanisms 121-124 is provided, and through the interface 21〇 interacts with the mechanisms 121-124, some internal information of the mechanisms 121-124 can be obtained, and 1 The internal parameters of the mechanism 丨2丨~丨24 are dynamically adjusted by the interface 2 1 0 to obtain the best verification path, and the time for reading the useless message during the verification is saved, or the waveform result of the huge load is not required to be completely accessed. . In the shelling, when the simulator uses V era as the verification language, to establish the mechanism for preparing the test pattern to be used for testing, for example, to load the test pattern into the object to be tested 1 2 5 and to simulate the test to be tested. The input mechanism 122 of the behavioral module 123 of the object ideal state and the comparison of the object to be tested 125 and the behavior module 123! 266070 V. The invention description (6) The mechanism of the round-off result 124...etc. The 〇pen Vera language itself has an interface 210 that can communicate with the outside world, such as a vsv function. The interface 210 provided by ^ Ming uses the VSV function interface 210 provided by the 0pen Vera language itself. The vsv function surface 210 provided by the conventional 0pen Vera language has not been used for communication with the outside world during verification. This embodiment is a functional program provided by the verification software programming language as an interface. The invention is not limited thereto. Interfaces can also be created using other programming languages that can communicate with the verification software programming language. In addition, in the preferred embodiment, in the simulation environment provided by the 0pen Vera language, the object to be tested 125 can be implemented by, for example, a hardware description language of "41". In order to correspond to the interface 210 of the VSV function, In the preferred embodiment of the present invention, 'C language is used as the interface program 230 to transmit through the My function.

What is the simulation environment provided by the Open Vera language? ! ~〗 24 for communication. § However, this is used as an interface program 23〇, including interactive functi〇ri sets for communicating with functions and providing a human-machine interface function for externally using the interface program 230 to communicate with the mechanisms 121 to 124 through the VSV function. For example, the interaction program of the interface program 2 3 0 human interface function is equivalent to the client (client), when starting to test the object 125 for verification, The mechanisms 121-124 are equivalent to the server and start to operate one after another, and when the interface program 230 is connected to the interface 210' of the vsv function through its interaction function group, the external interface can be connected through the interface 210 and the mechanisms 121 to i24.

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The interface program 230 interacts with the mechanisms 121-124. Assuming that the user wants to create a command to query the current simulation time, an option can be established on the interface program 230, for example, a graphical user interface (GUI), and the interface program 230 prepares the corresponding and executes the option. The interactive function group, therefore, this corresponding interactive function group will contain a VSV function, that is, the vsv function interface 21〇, used to communicate with the mechanism 1 21~1 2 4 . Through such a network connection, when the mechanism 1 2 1~1 2 4 receives a command to query the simulation time, the simulator providing these mechanisms 1 2 1 to 1 2 4 has an internal function that generates an instant simulation time message and Then send this message back to the interface program ~ 230 through the VSV function interface 2 1 . Therefore, when the interface program 230 receives the instant analog time message returned by the VSV function interface 210, it can be displayed through the human interface of the interface program 230. In this embodiment, the interface 21 0 can instantly output the verification status to be observed in the object to be tested 125 or the various status parameters of the other mechanisms 12 in the verification environment during the verification process. The verification status can be output and stored in the form of a message or a waveform. Since only the verification results that the verification engineer wants to observe are output, a large amount of storage space is not wasted, and the readability of the verification report can be increased. In addition, the interface 2丨〇 can also observe and adjust various state parameters of other mechanisms. In this way, the verification test environment can be dynamically adjusted and changed in response to various conditions in the verification process, thereby saving verification time and improving verification efficiency. Therefore, during the verification period, if the mechanism of the present invention communicates with the simulation environment, the following advantages can be obtained:

1266070 V. Invention description (8) 1 · When verifying, you can know the rate of 2). When you verify, you can change, for example, to change. 3. When you verify, you can get the interest. Instead of reaching the early end. 4. End the test pattern early. And the result report is also 5 · When verifying, it can be judged that the object to be tested and the workstation are idling. 6 · If the verification period is not correct, etc., change the waveform to the above. By providing and modulating, you can get instant information. Therefore, the pass-through is added, and the verification progress is passed through the test 1> dr* Ms rate. This device is temporarily stored through this useless beam test. The test can not be interrupted as it is in the past, whether it is under the test of the hardware, or the simulation of the occurrence of the analogy. The present invention does not change the quality of the test. Internal conditions, time of execution, coverage rate (C〇Verage, program change simulation environment verification conditions, instrument value, number of test changes, etc., program I to test the required information' and can be reused to verify Condition, the second does not need to test the output of the model by repairing the original test = the final inspection of the pattern. The program monitors the internal information of the object to be tested, and the timing is violated in the 2 pattern test, the design is not Other reasons such as the abnormality of the simulator, and the simulation of the situation 'and the determination of the timing violation or set, 'the way in which the verification results can be determined by the two outputs' to optimize the simulation load. A wafer-level test object is proposed. Verification method, the interface to the outside world and the simulation environment to see each other's information, and by this test, under the conditions of the sample, dynamically adjust the test The method is sufficient to make the verification high

1266070 V. INSTRUCTIONS (9) The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention, and should be considered as a further implementation of the present invention.

Page 13 1266070 BRIEF DESCRIPTION OF THE DRAWINGS [Brief Description of the Drawings] Figure 1 is a schematic diagram of a verification method in accordance with a preferred embodiment of the present invention. Figure 2 is a schematic diagram of a verification method in accordance with a preferred embodiment of the present invention. Description of the figure: 121~124: Flow 1 2 5: DUT 210 : VSV function interface

I I 2 3 0 : interface program

Claims (1)

1266070 6. The patenting scope 1. The verification environment of the design under test (DUT) of the slice, and the chiP level, the verification environment includes: test pattern mechanism (mechanism) For inputting a test pattern; inputting a system for inputting the test pattern into the object to be tested; and a behavior module receiving the test pattern for simulating an ideal state of operation of the object to be tested according to the test pattern;杈 output mechanism for comparing the behavior module and the result of the test object according to the test pattern; and a verification environment interface, instantaneously inputting 2 · if the patent application scope interface is more separately from the module, the comparison In the process of transmission, the input is instantaneous. 3. If the application scope of the patent application is different from the module and the comparison process, the object to be tested is connected by the verification state 0, and is used for the verification process. The verification status of the test object. The verification environment of claim 1, wherein the verification loop is coupled to the at least one of the test pattern mechanism, the input mechanism, and the behavioral mechanism for verifying the status of the verification environment. The verification environment of item 1, wherein the verification loop is coupled to at least one of the test pattern mechanism, the input mechanism, and the exit mechanism, and the 证马证环境 interface adjusts the verification environment in real time. The verification environment described in item 1, wherein the verification status is outputted in the form of a message. ... Temple, measuring object 5. As claimed in claim 1, the verification ring 垮, %%' where the verification state of the object to be tested is rotated in the form of a signal waveform. ~early L266〇7〇' patent application scope wherein the verification ring wherein the electronic device is provided in the verification ring, which further includes a verification environment environment as described in item 1 of the patent application scope, using an electronic design automation language, such as a patent application The verification environment punching automation language described in the sixth item is an Open Vera language. The verification environment described in item 7 of the patent application scope is provided by a VSV function. 10 11 The verification environment human-machine interface program described in claim 8 is used to interact with the verification environment interface, such as the verification environment described in claim 9 of the patent scope, wherein the human-machine interface program is The C language program provides an interactive function group for calling the vsv function. A verification method of a chip- levei design under test fT, comprising: 'providing a test pattern to load the object to be tested and a row=module, wherein the behavior module It is used to simulate the ideal state of operation of the test object according to the test pattern; 匕^ the behavior module and the test object are operated according to the test pattern, and the mouth wheel outputs the comparison result; In the process of verification, the test status of the test object is checked by the tester. The verification method described in item 11 of the patent scope is output immediately, and the verification environment interface is immediately in the state of verification. % out of the verification environment 1266070 6. Patent application scope 1 3 · The verification method described in claim 11 of the patent application, wherein the verification environment interface adjusts the state of the verification environment in real time during the verification process. IK1第17页