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TWI265700B - Decision feedback equalization input buffer - Google Patents

Decision feedback equalization input buffer

Info

Publication number
TWI265700B
TWI265700B TW094114012A TW94114012A TWI265700B TW I265700 B TWI265700 B TW I265700B TW 094114012 A TW094114012 A TW 094114012A TW 94114012 A TW94114012 A TW 94114012A TW I265700 B TWI265700 B TW I265700B
Authority
TW
Taiwan
Prior art keywords
signal
timing
response
control signal
input buffer
Prior art date
Application number
TW094114012A
Other languages
English (en)
Other versions
TW200616392A (en
Inventor
Young-Soo Sohn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040037966A external-priority patent/KR100615597B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200616392A publication Critical patent/TW200616392A/zh
Application granted granted Critical
Publication of TWI265700B publication Critical patent/TWI265700B/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03484—Tapped delay lines time-recursive
    • H04L2025/0349—Tapped delay lines time-recursive as a feedback filter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0024—Carrier regulation at the receiver end
    • H04L2027/0026—Correction of carrier offset
    • H04L2027/0038—Correction of carrier offset using an equaliser

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Memory System (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
TW094114012A 2004-05-27 2005-04-29 Decision feedback equalization input buffer TWI265700B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040037966A KR100615597B1 (ko) 2004-05-27 2004-05-27 데이터 입력회로 및 방법
US11/040,808 US7542507B2 (en) 2004-05-27 2005-01-21 Decision feedback equalization input buffer

Publications (2)

Publication Number Publication Date
TW200616392A TW200616392A (en) 2006-05-16
TWI265700B true TWI265700B (en) 2006-11-01

Family

ID=35433344

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094114012A TWI265700B (en) 2004-05-27 2005-04-29 Decision feedback equalization input buffer

Country Status (3)

Country Link
JP (1) JP4955224B2 (zh)
DE (1) DE102005022684B4 (zh)
TW (1) TWI265700B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4557948B2 (ja) 2006-10-12 2010-10-06 ザインエレクトロニクス株式会社 クロックデータ復元装置
US7916780B2 (en) * 2007-04-09 2011-03-29 Synerchip Co. Ltd Adaptive equalizer for use with clock and data recovery circuit of serial communication link
JP2011113450A (ja) 2009-11-30 2011-06-09 Toshiba Corp メモリインターフェース回路
JP2012244537A (ja) * 2011-05-23 2012-12-10 Ricoh Co Ltd データリカバリ方法およびデータリカバリ装置
JP6273679B2 (ja) * 2013-03-04 2018-02-07 株式会社リコー 送受信システム、送受信方法及び受信装置
JP6079388B2 (ja) * 2013-04-03 2017-02-15 富士通株式会社 受信回路及びその制御方法
US9325489B2 (en) * 2013-12-19 2016-04-26 Xilinx, Inc. Data receivers and methods of implementing data receivers in an integrated circuit
JP6769317B2 (ja) 2017-01-31 2020-10-14 富士通株式会社 判定帰還型等化器及びインターコネクト回路
CN111726104B (zh) * 2019-03-22 2024-08-27 瑞昱半导体股份有限公司 决策反馈均衡器
KR102842041B1 (ko) * 2021-06-24 2025-08-04 에스케이하이닉스 주식회사 데이터정렬동작을 수행하기 위한 전자장치
CN115589225A (zh) * 2021-07-05 2023-01-10 长鑫存储技术有限公司 输入缓冲电路以及半导体存储器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468834A (ja) * 1990-07-05 1992-03-04 Fujitsu Ltd インパルス応答の標本値推定方式
DE69321427T2 (de) * 1992-08-06 1999-05-12 Koninklijke Philips Electronics N.V., Eindhoven Empfangsanordnung zum Empfang eines digitalen Signals von einem Übertragungsmedium mit variablen Entzerrungsmitteln
JP2002184125A (ja) * 2000-12-08 2002-06-28 Matsushita Electric Ind Co Ltd ディジタル信号再生装置
JP4331641B2 (ja) * 2004-04-09 2009-09-16 富士通株式会社 等化回路を有する受信回路

Also Published As

Publication number Publication date
TW200616392A (en) 2006-05-16
DE102005022684A1 (de) 2005-12-22
JP2005341582A (ja) 2005-12-08
JP4955224B2 (ja) 2012-06-20
DE102005022684B4 (de) 2011-01-13

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees