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TWI264065B - Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region - Google Patents

Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region

Info

Publication number
TWI264065B
TWI264065B TW094118829A TW94118829A TWI264065B TW I264065 B TWI264065 B TW I264065B TW 094118829 A TW094118829 A TW 094118829A TW 94118829 A TW94118829 A TW 94118829A TW I264065 B TWI264065 B TW I264065B
Authority
TW
Taiwan
Prior art keywords
peripheral region
silicon nitride
nitride layer
photoresist pattern
semiconductor device
Prior art date
Application number
TW094118829A
Other languages
English (en)
Other versions
TW200605200A (en
Inventor
Kyung-Won Lee
Ki-Won Nam
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200605200A publication Critical patent/TW200605200A/zh
Application granted granted Critical
Publication of TWI264065B publication Critical patent/TWI264065B/zh

Links

Classifications

    • H10P50/73—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H10P50/283—
    • H10P50/71—
    • H10P76/4085—
    • H10P76/4088—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094118829A 2004-06-25 2005-06-07 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region TWI264065B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040048365A KR100706780B1 (ko) 2004-06-25 2004-06-25 주변영역의 선폭을 줄일 수 있는 반도체 소자 제조 방법

Publications (2)

Publication Number Publication Date
TW200605200A TW200605200A (en) 2006-02-01
TWI264065B true TWI264065B (en) 2006-10-11

Family

ID=35506461

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118829A TWI264065B (en) 2004-06-25 2005-06-07 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region

Country Status (5)

Country Link
US (3) US7179749B2 (zh)
JP (1) JP4771750B2 (zh)
KR (1) KR100706780B1 (zh)
CN (1) CN100345282C (zh)
TW (1) TWI264065B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706780B1 (ko) 2004-06-25 2007-04-11 주식회사 하이닉스반도체 주변영역의 선폭을 줄일 수 있는 반도체 소자 제조 방법
KR100571629B1 (ko) 2004-08-31 2006-04-17 주식회사 하이닉스반도체 반도체 소자 제조 방법
KR100788587B1 (ko) * 2006-07-05 2007-12-26 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
KR100780652B1 (ko) 2006-12-27 2007-11-30 주식회사 하이닉스반도체 반도체 소자 제조방법
KR100954107B1 (ko) 2006-12-27 2010-04-23 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100780606B1 (ko) * 2006-12-27 2007-11-30 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100875655B1 (ko) * 2007-01-04 2008-12-26 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100843899B1 (ko) * 2007-03-19 2008-07-03 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP2009152243A (ja) * 2007-12-18 2009-07-09 Toshiba Corp 半導体装置の製造方法
CN101740328B (zh) * 2008-11-13 2012-03-07 中芯国际集成电路制造(上海)有限公司 刻蚀方法
KR20100079081A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 엠아이엠 커패시터 및 그의 제조 방법
US7989355B2 (en) * 2009-02-12 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of pitch halving
US9710802B2 (en) * 2009-04-28 2017-07-18 Visa International Service Association Merchant competition alert
US8293656B2 (en) * 2009-05-22 2012-10-23 Applied Materials, Inc. Selective self-aligned double patterning of regions in an integrated circuit device
CN101777493A (zh) * 2010-01-28 2010-07-14 上海宏力半导体制造有限公司 硬掩膜层刻蚀方法
CN102931089B (zh) * 2011-08-10 2016-08-03 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
US8872339B2 (en) * 2012-02-10 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductors structure with elements having different widths and methods of making the same
TWI571699B (zh) * 2014-12-26 2017-02-21 旺宏電子股份有限公司 佈局圖案以及包含該佈局圖案的光罩
US9442366B2 (en) 2014-12-31 2016-09-13 Macronix International Co., Ltd. Layout pattern and photomask including the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0338102B1 (de) * 1988-04-19 1993-03-10 International Business Machines Corporation Verfahren zur Herstellung von integrierten Halbleiterstrukturen welche Feldeffekttransistoren mit Kanallängen im Submikrometerbereich enthalten
JPH05326899A (ja) * 1992-05-25 1993-12-10 Sony Corp 半導体装置およびその製造方法
JP2850833B2 (ja) * 1996-02-23 1999-01-27 日本電気株式会社 半導体装置の製造方法
JP3460436B2 (ja) * 1996-03-28 2003-10-27 ソニー株式会社 半導体装置の製造方法
US5995724A (en) * 1996-11-01 1999-11-30 Mikkelsen; Carl Image process system and process using personalization techniques
JPH11242336A (ja) * 1998-02-25 1999-09-07 Sharp Corp フォトレジストパターンの形成方法
JP2000058827A (ja) 1998-08-17 2000-02-25 Asahi Kasei Microsystems Kk 半導体装置の製造方法
US6774043B2 (en) * 2000-04-12 2004-08-10 Renesas Technology Corp. Method of manufacturing semiconductor device
JP2003272999A (ja) * 2002-03-14 2003-09-26 Sony Corp レジストパターンの形成方法、半導体装置の製造方法およびレジストパターンの形成装置
US6762130B2 (en) * 2002-05-31 2004-07-13 Texas Instruments Incorporated Method of photolithographically forming extremely narrow transistor gate elements
KR100493029B1 (ko) * 2002-10-26 2005-06-07 삼성전자주식회사 반도체 소자의 미세 패턴 형성방법
US20040087153A1 (en) * 2002-10-31 2004-05-06 Yan Du Method of etching a silicon-containing dielectric material
JP2004179226A (ja) * 2002-11-25 2004-06-24 Renesas Technology Corp 半導体装置の製造方法
US7186649B2 (en) * 2003-04-08 2007-03-06 Dongbu Electronics Co. Ltd. Submicron semiconductor device and a fabricating method thereof
JP4529024B2 (ja) * 2003-04-22 2010-08-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7368392B2 (en) * 2003-07-10 2008-05-06 Applied Materials, Inc. Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode
US7316979B2 (en) * 2003-08-01 2008-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for providing an integrated active region on silicon-on-insulator devices
KR100706780B1 (ko) 2004-06-25 2007-04-11 주식회사 하이닉스반도체 주변영역의 선폭을 줄일 수 있는 반도체 소자 제조 방법
US8121338B2 (en) * 2004-07-07 2012-02-21 Directsmile Gmbh Process for generating images with realistic text insertion
US7271107B2 (en) * 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US7978364B2 (en) * 2007-06-18 2011-07-12 Canon Kabushiki Kaisha Image processing apparatus and control method thereof

Also Published As

Publication number Publication date
CN1722409A (zh) 2006-01-18
US20050287809A1 (en) 2005-12-29
US20090253263A1 (en) 2009-10-08
KR100706780B1 (ko) 2007-04-11
TW200605200A (en) 2006-02-01
US7179749B2 (en) 2007-02-20
US20070184664A1 (en) 2007-08-09
US7563721B2 (en) 2009-07-21
US7803710B2 (en) 2010-09-28
JP2006013485A (ja) 2006-01-12
JP4771750B2 (ja) 2011-09-14
KR20050122737A (ko) 2005-12-29
CN100345282C (zh) 2007-10-24

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees