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TWI263934B - Synchronous periodical orthogonal data converter - Google Patents

Synchronous periodical orthogonal data converter

Info

Publication number
TWI263934B
TWI263934B TW093127265A TW93127265A TWI263934B TW I263934 B TWI263934 B TW I263934B TW 093127265 A TW093127265 A TW 093127265A TW 93127265 A TW93127265 A TW 93127265A TW I263934 B TWI263934 B TW I263934B
Authority
TW
Taiwan
Prior art keywords
vector
bank
data converter
components
register files
Prior art date
Application number
TW093127265A
Other languages
Chinese (zh)
Other versions
TW200512644A (en
Inventor
Boris Prokopenko
Timour Paltachev
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/666,083 external-priority patent/US7284113B2/en
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200512644A publication Critical patent/TW200512644A/en
Application granted granted Critical
Publication of TWI263934B publication Critical patent/TWI263934B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

An orthogonal data converter for converting the components of a sequential vector component flow to a parallel vector component flow. The data converter has an input rotator configured to rotate corresponding vector components of the sequential vector component flow by a prescribed amount, and a bank of register files configured to store the rotated vector components. The converter also has an output rotator configured to rotate the position of the vector components read from the bank of register files by a prescribed amount. A controller of the converter is operative to control the addressing of the bank of register files and the rotating of the vector components. In this regard, the controller is operative to write the vector components to the bank of register files in a prescribed order and read the vector components in a prescribed order to generate the parallel vector component flow.
TW093127265A 2003-09-19 2004-09-09 Synchronous periodical orthogonal data converter TWI263934B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/666,083 US7284113B2 (en) 2003-01-29 2003-09-19 Synchronous periodical orthogonal data converter

Publications (2)

Publication Number Publication Date
TW200512644A TW200512644A (en) 2005-04-01
TWI263934B true TWI263934B (en) 2006-10-11

Family

ID=34619749

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093127265A TWI263934B (en) 2003-09-19 2004-09-09 Synchronous periodical orthogonal data converter

Country Status (2)

Country Link
CN (1) CN100517212C (en)
TW (1) TWI263934B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8659611B2 (en) * 2010-03-17 2014-02-25 Qualcomm Mems Technologies, Inc. System and method for frame buffer storage and retrieval in alternating orientations
CN104011664B (en) * 2011-12-23 2016-12-28 英特尔公司 Super multiply-add (super MADD) instruction using three scalar terms

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4556850A (en) 1982-11-01 1985-12-03 United Technologies Corporation Serial to parallel data conversion circuit
US5175819A (en) * 1990-03-28 1992-12-29 Integrated Device Technology, Inc. Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer
DE4105193A1 (en) * 1991-02-20 1992-08-27 Bodenseewerk Geraetetech DATA INTERFACE FOR THE INPUT AND OUTPUT OF DATA WITH PARALLEL COMPUTERS
CA2100729C (en) * 1993-07-16 2001-01-16 Simon Skierszkan Serial bit rate converter embedded in a switching matrix
KR0141767B1 (en) * 1994-04-25 1998-07-01 이헌조 A digital signal processor's form / depot device

Also Published As

Publication number Publication date
CN100517212C (en) 2009-07-22
CN1591316A (en) 2005-03-09
TW200512644A (en) 2005-04-01

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Legal Events

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MK4A Expiration of patent term of an invention patent