1263367 九、發明說明： 【發明所屬之技術領域】 本發明係挺供一種電丨谷絲的結構，尤指一種電炼絲上之 金屬多晶矽化物層小於閘極上之金屬多晶矽化物層之電熔 絲之結構。 ⑩ 【先前技術】 隨著半導體製程的微小化以及複雜度的提高，半導體元 件也變得更容易受各式缺陷或雜質所影響，而單一金屬連 線、二極體或電晶體等的失效往往即構成整個晶片的缺 陷。因此為了解決這個問題，現行技術便會在積體電路中 形成一些可熔斷的連接線(fusible links)，也就是溶絲 (fuse)，以確保積體電路的可利用性。 一般而§ ’纟谷絲係連接積體電路中的冗餘電路 (redundancy circuit)，一旦檢測發現電路具有缺陷時，這些 ， 連接線就可用於修復(repairing)或取代有缺陷的電路。以記 、 憶體(memory)的結構為例，習知製程會於結構的最上層製 作一些溶絲的結構’其作用在於當記憶體完成時，若其中 有部分記憶胞、字元線(word line)或導線之功能有問題時， 1263367 就可以利用熔絲跳接另一些冗餘的（re(jundant ceus)的記憶 胞、字元線或導線來取代之。 另外，目岫的熔絲設計更可以提供程式化(pr〇gramming elements)的功能，以使各種客戶可依不同的功能設計來程 式化電路。例如’為了節省研發與製作成本，晶圓廠便可 以利用金屬連線與記憶陣列内每個電晶體相連接，並在連 接線中增加-個喊化連純元件，待半導體晶片製作完 成後’再由外部進行資料輪入’以獨特化各個標準晶片成 各式產品晶片。當可程式化唯讀記憶體(p哪贿邮他r〇m， PROM；Ht貝料輸人時，如使用較高電壓將連接線上的程 式化連結性元件㈣，而產生斷路(Gff_state)，即完成1 ” 的輸入；反之，未經燒毁醜絲，t晶體連接線路仍存在 而形成導通狀態(on-state) ’即相當於存入，，0，，。此種利用高 電壓燒毀(Mowing)熔絲的過程即為程式化㈣gramming)， 而且-旦程式化的熔絲將永久形成斷路狀態存在。經由程 式化過程可使經程式化而形成斷路狀態的熔絲與未經程式 化而形成通路狀態的溶絲形成數位資料⑷邮⑽形式 存。 1263367 而攸4呆作方式來説’纟谷絲大致分為熱纟容絲和電炫絲 (eFUse)兩種。所謂熱熔絲，使指其先藉由一雷射切割灯 zip)的步驟來切斷熱熔絲，再藉由一包括切斷(cm)、連接 〇lnk)等之雷射修補（laser repair)的步驟，來切斷壞的記情 胞、字元線(word line)或導線原本之電連接，或製作出一此 新的電連接以補償被報廢的記憶胞、字元線或導線；至於 電熔絲則是利用電致遷移（electro-migrati〇n)的原理使熔絲 出現斷路，以達到修補的效果。 目前備受矚目的電熔絲更整合了軟體演算法和精微電 子熔絲來組成晶片，因此能調控並適應其功能，並回應外 部條件的變化和系統要求，這種技術能夠自行調節功能， 無需人工干預，能在性能和功耗之間進行折衷方案的選 齡擇，該技術持續監控晶片功能，並透過切斷便宜簡單的電 子熔絲啟動糾正步驟。簡單來說，電熔絲有助於晶片控制 單個電路的速度，以管理功率消耗並修復不可預料的、潛 在的缺陷。例如，該技術可檢測出晶片因為單個電路執行 • 速度太决或太('叉，晶片可以透過調節合適的局部電壓，力。 、 速或減少電路速度。電熔絲成功採用了電致遷移特性，在 過去電致遷移技術傳統上對晶片性能有不良影響，避免用 於设计之中，但現在卻利用電致遷移技術使得電熔絲產生 1263367 斷路’進而達到修補或程式化積體電路的功效。 3知之電纟谷絲1 〇結構如第1圖所示，其包含一電溶絲 12，另對外部電路延伸出一陰極(Cath〇de)14、一陽極 (Anode)16，而電熔絲12和陰極14電連接之處係存在有一 接面18。在一般情況下，電熔絲結構1〇都是備而不用， 僅為積體電路上一塊冗餘電路，但是當需要進行修補或程 式化時’就必須有適當的電流通過電熔絲結構1〇以使得電 熔絲10產生電致遷移。習知之電熔絲結構10作用方式如 第2圖所示，當大電流持續通過電熔絲結構1〇時，電熔絲 12的地方會是電流密度越高的地方，電場也會越高，而導 致原子沿著材質本身的晶粒邊界，往電子流動的方向移動 的現象。因此隨著電致遷移的持續增加，電流密度亦跟増 加，使情況更加惡化，若電致遷移太過劇烈，則會導致第 1圖中之接面18斷開造成斷路28，斷路28 一旦形成即表 不達到修補或程式化的目的。 :、、<、而，習知技藝以電致遷移的方式斷開多晶石夕炫絲的方 法十刀難以控制，因此造成修補良率(repair yield)的下降。 因為當電壓值過小時，電熔絲將不產生電致遷移的現象， 則不可忐達到設計者所需的電路，但是，當電壓值過大時， 1263367 電熔絲又會發生多晶矽熔絲的爆裂的情況，不僅將污染積 體電路，同時可能造成各種短路情況，換句話說，在過去 必須要有效控制電壓才有可能有效控制電熔絲的斷路情 形。然而電溶絲對於最高電壓值的容許誤差範圍很小，通 常需控制在5%範圍以下，而超過此範圍即會造成多晶矽熔 絲的爆裂，所以必須花費諸多的檢測儀器或者設備去監控 通過電熔絲之電壓，然而即便是這樣勞神費力，其控制情 況因為需同時注意電流通過的時間和產生的電壓，所以成 果亦不佳。 因此，如何發展一種方式或結構能快速並精準地讓電熔 絲被燒斷，且不易受到電壓變化而產生燒不斷或者發生爆 裂等現象，是目前該技術領域中十分需要的。 【發明内容】 本發明係提供一種電熔絲的結構，以解決上述問題。 在本發明之最佳實施例中，係提供一種設於一基底上之 電熔絲（eFuse)結構，該基底包含有至少一導電結構，且該 導電結構包含有一第一多晶矽層及一第一金屬多晶矽化物 層堆疊於該第一多晶石夕層之上。而該電溶絲結構包含有一 1263367 第二多晶秒層’以及—第二金屬多晶石夕化物層，堆疊於該 第一夕曰曰矽層之上，且该第二金屬多晶矽化物層的截面積 係小於該第一金屬多晶矽化物層的截面積。 在本發明之另一最佳實施例中，係提供一種設於一基底 上之電熔絲（eFuse)結構，該電熔絲結構之堆疊結構係相同 於該基底上之一閘極結構之堆疊結構，故幾乎可用相同的 製程來加以製備，但該電熔絲之厚度係小於該閘極結構之 厚度。 由於本發明之電溶絲結構具有較薄的金屬多晶碎化物 層，故較易燒斷，可有效解決習知技術無法適當地控制熔 、、、糸k k/f與否的情況並且提升修補良率(repair yieid)，不再需 要非常精密的電壓控制，此外，本發明之閘極又因為具有 車又厚的金屬多晶矽化物層而能使得電流流通情形更穩定， 再者，於本發明中閘極和電熔絲之結構相似可整合於同一 製程完成，所以能簡化製程且成本更低。 【實施方式】 請參考第3圖至第7圖，第3圖至第7圖為本發明製作 電熔絲之第一實施例示意圖。如第3圖所示，首先，提供 1263367 一半$體曰曰片30’半導體晶片30包含有一基底（substrate) 31，且基底31表面至少定義有一第一區域32和一第二區 域33。接著利用區域氧化法（i〇cai οχι—，L〇c〇S)或淺 溝隔離（shallow trench isolation, STI)等製程，於第二區域 〜 33之基底31中製作出複數個絕緣層，例如場氧化層（f]eid oxide layer)或淺溝隔離(STI) 34，來環繞並隔離第一區域 32 ’以使弟一區域32形成一主動區域(active area)，用來製 鲁 作金屬氧化物半導體(M0S)電晶體等之元件。 然後如第4圖所示，利用一高溫熱氧化(thermal oxidation)或化學氣杻沈積（chemical vap〇r dep〇siti〇n，CVD) 等製程’在第-區域32表面形成—石夕氧化層或氮化石夕層， 當作間極絕緣層40，而第二區域33表面則因為淺溝隔離 鲁34的關係，由石夕氧化物所構成之閘極絕緣層幾乎重合於淺 溝隔離34表面。接著依序進行—多晶料(帅siii·) 42 以及-金屬多晶耗物層（pQlysilieide) 44的沈積製程， 再利用黃光暨則製程(PEp)，姓刻多晶石夕層42以及金屬 '多晶石夕化物層44,以於第一區域32和第二區域33中分別 '沿成夕曰曰矽層42a、金屬多晶矽化物層44a之閘極結構52 以及夕曰曰石夕層42b、金屬多晶石夕化物層44b之電溶絲結構 56等之堆叠結構，如第5圖所示。至此，由於—次姓刻的 11 1263367 關係，多晶矽層42a、42b具有相同膜厚，而金屬多晶石夕化 物層44a、44b亦具有相同膜厚，但是金屬多晶矽化物層 44a、44b的膜厚不一定相等於多晶矽層42a、42b的膜厚， 而多晶石夕層42a、42b以及金屬多晶石夕化物層44a、44b可 依不同之設計需求而具有相同或不相同的線寬。在本發明 之較佳實施例中，多晶矽層42a、42b與金屬多晶矽化物層 44a、44b係具有相同的線寬。 請參考第6圖，接著進行一離子佈植(i〇nimpiantati〇n) 製程，於閘極結構52之相對兩侧形成MOS電晶體之輕摻 雜汲極(lightly doped drain，LDD) 5 8。然後利用一化學氣相 沈積法(chemical vapor deposition，CVD)，於半導體晶片 30 表面沈積一氮化石夕（silicon nitride)層（未顯示），再進行一 非等向性的乾钱刻製程，回钮刻氮化石夕層至基底31的表 面，以於閘極結構52以及電熔絲結構56之周圍分別形成 一侧壁子（spacer) 60。 如第7圖所示，隨後進行一離子佈植製程，以於閘極 結構52之相對兩侧形成M0S電晶體之汲極62與源極62。 最後再形成一自行對準金屬矽化物阻擋層（salicide block layer)覆蓋於第二區域33，並利用一自行對準金屬石夕化物 12 1263367 (self_aligned silicide，簡稱 salicide)製程，於源極 62、没極 62以及閘極結構52表面形成一自動對準金屬多晶石夕化物 層（salicide layer) 64，使得閘極結構52之金屬多晶矽化物 層的總膜厚（金屬多晶碎化物層44 a加上自動對準金屬多晶 砍化物層64)大於電熔絲結構56之金屬多晶石夕化物層的膜 尽（金屬夕晶梦化物層44b)。而因為在本發明之較佳實施例 中，多晶矽層42a、42b與金屬多晶矽化物層44a、44b係 具有相同的線寬，因此閘極結構52之金屬多晶矽化物層的 截面積亦大於電熔絲結構56之金屬多晶矽化物層的截面 積0 如此一來，相對於閘極結構，本發明之電熔絲結構便 具有幸乂薄的金屬多晶石夕化物層，故較易燒斷，可有效解決 習知技術無法適當地控制熔絲燒斷與否的情況並且提升修 補良率此外，本發明之閘極結構又因為具有較厚的金屬 多晶矽化物層而能使得電流流通情形更穩定。 明多考第8圖，第8圖為本發明製作電溶絲之另一實施 例示意圖，其與前述第3圖至第7圖為之第一實施例的主 要不同之處在於金屬多晶石夕化物層的形成方式。首先，提 供半導體晶片80，半導體晶片80包含有一基底81，且 13 1263367 基底81表面至少定義有一第一區域82和一第二區域幻。 接著於第二區域83之基底81中製作出複數個淺溝隔離 (STI) 84來環繞並隔離第一區域82,以使第一區域幻形成 一主動區域(active area)，用來製作金屬氧化物半導體 電晶體等之元件。 然後利用一高溫熱氧化或化學氣相沈積(CVD)等製 程’在第一區域82表面形成一閘極絕緣層86。接著依序 進行一多晶矽層（未顯示）以及一金屬多晶矽化物層（未顯示） 的沈積製程，再利用半透型光罩(half-tone mask)來進行黃 光暨蝕刻製程(PEP)，蝕刻多晶矽層以及金屬多晶矽化物 層，以於第一區域82和第二區域83中分別形成多晶矽層 88a、金屬多晶矽化物層9〇a之閘極結構92以及多晶石夕層 88b、金屬多晶矽化物層9〇b之電熔絲結構94等之堆疊結 構。其中，多晶矽層88a、88b係具有相同膜厚，而金屬多 晶矽化物層90a、90b則因為半透型光罩(half-tone mask)的 關係而具有不同膜厚，且閘極結構92之金屬多晶矽化物層 9〇a的膜厚大於電熔絲結構94之金屬多晶矽化物層90b的 膜厚。在本實施例中，閘極結構92與電熔絲結構94係具 有相同的線寬。此外，若欲形成不同金屬多晶矽化物層之 膜厚亦可以利用多次沈積加上一次蝕刻，或是利用一次沈 1263367 積加上多次_等方式，岐最終⑽成之閘極結構％ 金屬多晶耗物層90a的膜厚大於電炫絲結構％之八尸夕 晶石夕化物層90b的膜厚，此為習知相關技藝者所^萄夕 此不多加贅述。 、 在 相較於習知技術，本發明的電炫絲提供一種電心糸之全 屬多晶石夕化物層小於閘極上之金屬多晶魏物層之電炫: 之結構’這樣的電料結構可简㈣知技術無^效控 制炫絲燒斷與否的情況並且提升修補良率㈣一灿），不 再需要精密的電壓控制，即可因為電溶絲之金屬多晶石夕化 物層較薄的緣故，而較易燒斷，而閘極又因為具有較厚的 金屬多晶魏物層而使得電流流通情形更穩定，再者於本 毛月中閘極和㈣絲之結構相似可於經由同—製程完成， 所以製程更簡化且成本更低。 二上所述僅為本發明之較佳實施例，凡依本發明申請 專利I&圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 1263367 【圖式簡單說明】 第1圖為習知技術中電熔絲之結構圖。 第2圖為習知技術中電熔絲產生電致遷移後之結構圖。 第3圖至第7圖為本發明中於一半導體晶面上製作一電熔 絲的方法示意圖。 第8圖為本發明中於一半導體晶面上製作一電熔絲的另一 方法示意圖。 ► 【主要元件符號說明】 10、56、94電熔絲結構 12 電熔絲 14 陰極 16 陽極 18 接面 28 斷路 30、80 半導體晶片 3卜81 基底 32、82 第一區域 33 > 83 第二區域 34、84 淺溝隔離 40、86 閘極絕緣層 42、42a、42b、88a、88b 多晶矽層 44、44a、44b、90a、90b 金屬多晶梦化物層 52、92 閘極結構 58 輕摻雜没極 60 側壁子 62 没/源極 64 自動對準金屬多晶矽化物層 161263367 IX. Description of the invention: [Technical field to which the invention pertains] The present invention provides a structure for an electric bismuth wire, in particular, an electric fuse of a metal polycrystalline bismuth layer on an electroformed wire that is smaller than a metal polycrystalline bismuth layer on a gate. The structure. 10 [Prior Art] With the miniaturization and complexity of semiconductor processes, semiconductor components are also more susceptible to various types of defects or impurities, and failure of single metal wires, diodes or transistors is often That is, it constitutes a defect of the entire wafer. Therefore, in order to solve this problem, the current technology forms fusible links, that is, fuses, in the integrated circuit to ensure the availability of the integrated circuit. In general, § 纟 纟 丝 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 red red red 冗余 冗余 冗余 冗余 red 冗余 red red red red red red red red red red red red red red red red red red red red red red 。 。 。 Taking the structure of memory and memory as an example, the conventional process will make some filament structure in the uppermost layer of the structure. The function is to have some memory cells and word lines when the memory is completed. If there is a problem with the function of the line or the wire, the 1263367 can be replaced by a fuse (re(jundant ceus) memory cell, word line or wire). In addition, the fuse design is witnessed. It can also provide pr〇gramming elements to enable various customers to program circuits according to different functions. For example, in order to save development and production costs, fabs can use metal wiring and memory arrays. Each of the transistors is connected, and a new component is added to the connection line. After the semiconductor wafer is completed, 'the data is rotated by the outside' to uniqueize each standard wafer into various product wafers. Programmable read-only memory (p), if you use a higher voltage to connect the stylized connected components on the line (4), a break (Gff_state) is generated. Finish Into the input of 1 "; conversely, without burning the ugly wire, the t crystal connection line still exists and forms an on-state 'that is equivalent to depositing, 0,,. This is burned with high voltage (Mowing The process of the fuse is stylized (four) gramming), and the stylized fuse will permanently form an open state. The stylized process can be used to form a broken fuse and unstylized. The state of the filament in the path state is formed by digital data (4) in the form of postal code (10). 1263367 In the case of 攸4, the 纟4 silk is roughly divided into two types: hot 纟 丝 and eFUse. It means that the thermal fuse is cut off by a step of a laser cutting lamp zip), and then cut by a laser repair process including cutting (cm), connecting nklnk, etc. The broken cell, the word line, or the original electrical connection of the wire, or a new electrical connection to compensate for the discarded memory cell, word line or wire; as for the electric fuse Using the principle of electro-migration (electro-migrati〇n) to open the fuse, The effect of repairing. The current high-profile electric fuses integrate software algorithms and micro-electronic fuses to form a chip, so they can regulate and adapt to their functions, and respond to changes in external conditions and system requirements. Self-adjusting function, no need for manual intervention, a compromise between performance and power consumption, the technology continuously monitors the wafer function and initiates corrective steps by cutting off cheap and simple electronic fuses. Simply put, electricity Fuses help the wafer control the speed of a single circuit to manage power consumption and fix unanticipated, potential defects. For example, the technology can detect that a wafer is performing because of a single circuit. • The speed is too fast or too ('fork, the wafer can be adjusted by adjusting the appropriate local voltage, force, speed or reducing the circuit speed. The electric fuse successfully adopts electromigration characteristics. In the past, electromigration technology has traditionally had a negative impact on wafer performance and was avoided in design, but now it uses electromigration technology to make the electric fuse generate 1263367 open circuit, thus achieving the effect of repairing or staging integrated circuits. 3 Knowing that the electric 纟 丝 1 structure is shown in Fig. 1, which comprises an electrolysis wire 12, and a cathode (Cath〇de) 14, an anode (Anode) 16 is extended to the external circuit, and the fused Where the wire 12 and the cathode 14 are electrically connected, there is a junction 18. In general, the electrical fuse structure is not used, but only a redundant circuit on the integrated circuit, but when repair or When stylized, it is necessary to have an appropriate current through the electric fuse structure 1 to cause electro-discharge of the electric fuse 10. The conventional electric fuse structure 10 acts as shown in Fig. 2, when a large current continues to pass electricity. melt When the structure is 1 ,, the place where the electric fuse 12 is is the higher the current density, and the electric field will be higher, which causes the atom to move along the grain boundary of the material itself in the direction of electron flow. The electromigration continues to increase, and the current density is also increased, which makes the situation worse. If the electromigration is too severe, the junction 18 in Fig. 1 will be broken to cause the disconnection 28, and the open circuit 28 will be formed once it is formed. For the purpose of repairing or stylizing: :,, <,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Because the voltage is too small, the electric fuse will not produce electromigration, so the circuit required by the designer can not be reached. However, when the voltage is too large, the 1263367 electric fuse will generate polysilicon fuse. The bursting situation will not only pollute the integrated circuit, but also cause various short-circuit conditions. In other words, in the past, it is necessary to effectively control the voltage to effectively control the open condition of the electric fuse. The allowable error range of the electrolyzed wire for the highest voltage value is small, and usually needs to be controlled below the 5% range. If the range exceeds this range, the polycrystalline silicon fuse will burst, so it is necessary to spend a lot of testing instruments or equipment to monitor the electrofusion. The voltage of the wire, however, even if it is so laborious, the control situation is not good because of the need to pay attention to the time of the current and the voltage generated. Therefore, how to develop a method or structure can quickly and accurately make the electric fuse It is currently required in the technical field to be blown off, and is not susceptible to voltage changes, and is often required in the technical field. SUMMARY OF THE INVENTION The present invention provides a structure of an electric fuse to solve the above problems. In a preferred embodiment of the present invention, an eFuse structure is provided on a substrate, the substrate includes at least one conductive structure, and the conductive structure includes a first polysilicon layer and a first A metal polycrystalline telluride layer is stacked on top of the first polycrystalline layer. The electrolyzed filament structure comprises a 1263367 second polymorph layer and a second metal polycrystalline layer, stacked on the first layer, and the second metal polycrystal layer The cross-sectional area is smaller than the cross-sectional area of the first metal polycrystalline telluride layer. In another preferred embodiment of the present invention, there is provided an electrical fuse (eFuse) structure disposed on a substrate, the stacked structure of the electrical fuse structure being the same as a stack of gate structures on the substrate The structure can be prepared by almost the same process, but the thickness of the electric fuse is smaller than the thickness of the gate structure. Since the electro-dissolved filament structure of the present invention has a thin metal polycrystalline fragment layer, it is easy to be blown, and can effectively solve the problem that the conventional technology cannot properly control the melting, the 糸 kk/f or not and improve the repair. The yield yieid eliminates the need for very precise voltage control. In addition, the gate of the present invention can make the current flow situation more stable because of the thick metal polycrystalline telluride layer. Further, in the present invention, The structure of the gate and the electric fuse can be integrated into the same process, so the process can be simplified and the cost is lower. [Embodiment] Please refer to Figs. 3 to 7 and Fig. 3 to Fig. 7 are schematic views showing a first embodiment of manufacturing an electric fuse according to the present invention. As shown in Fig. 3, first, a 1263367 half-body wafer 30' semiconductor wafer 30 is provided with a substrate 31, and at least a first region 32 and a second region 33 are defined on the surface of the substrate 31. Then, using a process such as a region oxidation method (i〇cai οχι—, L〇c〇S) or a shallow trench isolation (STI), a plurality of insulating layers are formed in the substrate 31 of the second region 331, for example, a field oxide layer (f]eid oxide layer) or a shallow trench isolation (STI) 34 to surround and isolate the first region 32' such that the region 32 forms an active area for the metal oxide oxidation An element of a semiconductor (M0S) transistor or the like. Then, as shown in Fig. 4, a process such as thermal oxidation or chemical vapor deposition (chemical vap〇r dep〇siti〇n, CVD) is formed on the surface of the first region 32. The layer or the nitride layer is regarded as the interlayer insulating layer 40, and the surface of the second region 33 is formed by the shallow trench isolation Lu 34, and the gate insulating layer composed of the stone oxide is almost coincident with the shallow trench isolation 34. surface. Then, the deposition process of the polycrystalline material (shovel siii·) 42 and the metal polycrystalline consumable layer (pQlysilieide) 44 is carried out in sequence, and then the yellow light gamma process (PEp) is used, and the polycrystalline stone layer 42 is The metal polycrystalline dahnea layer 44 is formed in the first region 32 and the second region 33, respectively, along the gate layer 42a, the gate structure 52 of the metal polycrystal telluride layer 44a, and the Xi Shishi layer. 42b, a stacked structure of the electrolyzed filament structure 56 of the metal polycrystalline lithiate layer 44b, etc., as shown in FIG. So far, the polycrystalline germanium layers 42a, 42b have the same film thickness due to the 11 1263367 relationship of the secondary surname, and the metal polycrystalline dahlia layer 44a, 44b also have the same film thickness, but the film thickness of the metal polycrystalline telluride layers 44a, 44b It is not necessarily equal to the film thickness of the polysilicon layers 42a, 42b, and the polycrystalline layer 42a, 42b and the metal polycrystalline layer 44a, 44b may have the same or different line widths depending on design requirements. In a preferred embodiment of the invention, the polysilicon layers 42a, 42b and the metal poly germanide layers 44a, 44b have the same linewidth. Referring to Figure 6, an ion implantation (i〇nimpiantati〇n) process is then performed to form a lightly doped drain (LDD) 5 8 of the MOS transistor on opposite sides of the gate structure 52. Then, a silicon nitride layer (not shown) is deposited on the surface of the semiconductor wafer 30 by a chemical vapor deposition (CVD) process, and then an anisotropic dry etching process is performed. The nitride layer is nitrided to the surface of the substrate 31 to form a spacer 60 around the gate structure 52 and the electrical fuse structure 56, respectively. As shown in Fig. 7, an ion implantation process is then performed to form the drain 62 and source 62 of the MOS transistor on opposite sides of the gate structure 52. Finally, a self-aligned metal salicide block layer is formed on the second region 33, and a self-aligned silicide (salicide) process is used at the source 62. The surface of the gate electrode 52 and the surface of the gate structure 52 form an auto-aligned metal polycrystalline salide layer 64 such that the total film thickness of the metal polycrystalline germanide layer of the gate structure 52 (metal polycrystalline layer 44 a In addition, the self-aligned metal polycrystalline cleavage layer 64) is larger than the metal polycrystalline crystallization layer of the electrical fuse structure 56 (metal crystallization layer 44b). However, in the preferred embodiment of the present invention, the polysilicon layer 42a, 42b and the metal poly germanide layer 44a, 44b have the same line width, so that the metal polycrystalline germanide layer of the gate structure 52 has a larger cross-sectional area than the electric fuse. The cross-sectional area of the metal polycrystalline germanide layer of the structure 56 is such that the electric fuse structure of the present invention has a thin metal polycrystalline lithiate layer relative to the gate structure, so that it is more easily blown and can be effective. Solving the problem that the conventional technology cannot properly control the fuse blow or not and improve the repair yield. In addition, the gate structure of the present invention can make the current flow situation more stable because of having a thick metal polycrystalline germanide layer. FIG. 8 is a schematic view showing another embodiment of the electrolysis wire according to the present invention, which is mainly different from the first embodiment of FIGS. 3 to 7 in that the metal polycrystalline stone is in the first embodiment. The formation of the layer of yoke. First, a semiconductor wafer 80 is provided. The semiconductor wafer 80 includes a substrate 81, and 13 1263367 has a surface defining at least a first region 82 and a second region. Then, a plurality of shallow trench isolations (STIs) 84 are formed in the substrate 81 of the second region 83 to surround and isolate the first region 82, so that the first region is formed into an active area for metal oxidation. An element such as a semiconductor transistor. A gate insulating layer 86 is then formed on the surface of the first region 82 by a process such as high temperature thermal oxidation or chemical vapor deposition (CVD). Then, a deposition process of a polysilicon layer (not shown) and a metal polycrystalline germanide layer (not shown) is sequentially performed, and a half-tone mask is used to perform a yellow light etch process (PEP), etching. a polycrystalline germanium layer and a metal polycrystalline germanide layer to form a polysilicon layer 88a, a gate structure 92 of the metal polycrystal telluride layer 9a, a polycrystalline layer 88b, and a polycrystalline germanide layer in the first region 82 and the second region 83, respectively. A stacked structure of a 9 〇b electric fuse structure 94 or the like. Wherein, the polycrystalline germanium layers 88a, 88b have the same film thickness, and the metal polycrystalline germanide layers 90a, 90b have different film thicknesses due to the relationship of a half-tone mask, and the metal polysilicon of the gate structure 92 The film thickness of the layer 9〇a is larger than the film thickness of the metal polymorph layer 90b of the electric fuse structure 94. In the present embodiment, the gate structure 92 and the electrical fuse structure 94 have the same line width. In addition, if the film thickness of the different metal polycrystalline germanide layer is to be formed, it is also possible to use multiple depositions plus one etching, or to use a first sinking of 1263367 product plus multiple times, etc., and finally (10) into a gate structure % metal The film thickness of the crystal loss layer 90a is larger than the film thickness of the octagonal smectite layer 90b of the electrospinning structure %, which is not described in detail by those skilled in the art. Compared with the prior art, the electrosurgical wire of the present invention provides a polycrystalline lithiated layer of electrocardiograph which is smaller than the metal polycrystalline Wei layer on the gate: the structure of such a material The structure can be simplified (4) knowing the technology does not control the situation of the tying wire burned or not and improves the repair rate (4) one can), no need for precise voltage control, because the metal polycrystalline crystallization layer of the electrolysis wire Thinner, it is easier to blow, and the gate is more stable due to the thicker polycrystalline Wei-layer, and the structure of the gate is similar to that of the (four) wire. The process is completed through the same process, so the process is more simplified and the cost is lower. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the I& application according to the present invention should belong to the scope of the present invention. 1263367 [Simple description of the drawing] A structural diagram of an electric fuse in the prior art. Fig. 2 is a structural view showing the electromigration of the electric fuse in the prior art. 3 to 7 are schematic views showing a method of fabricating an electric fuse on a semiconductor crystal face in the present invention. Figure 8 is a schematic view showing another method of fabricating an electric fuse on a semiconductor crystal face in the present invention. ► [Main component symbol description] 10, 56, 94 electric fuse structure 12 electric fuse 14 cathode 16 anode 18 junction 28 open circuit 30, 80 semiconductor wafer 3 卜 81 substrate 32, 82 first region 33 > 83 second Region 34, 84 shallow trench isolation 40, 86 gate insulating layer 42, 42a, 42b, 88a, 88b polysilicon layer 44, 44a, 44b, 90a, 90b metal polycrystalline dream layer 52, 92 gate structure 58 lightly doped Nothing 60 Sidewall 62 No/Source 64 Automatic alignment of metal polycrystalline telluride layer 16