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TWI263225B - Circuit and method for built-in self test (BIST) and computer readable recording medium for storing program thereof - Google Patents

Circuit and method for built-in self test (BIST) and computer readable recording medium for storing program thereof

Info

Publication number
TWI263225B
TWI263225B TW94102287A TW94102287A TWI263225B TW I263225 B TWI263225 B TW I263225B TW 94102287 A TW94102287 A TW 94102287A TW 94102287 A TW94102287 A TW 94102287A TW I263225 B TWI263225 B TW I263225B
Authority
TW
Taiwan
Prior art keywords
circuit
bist
test
built
recording medium
Prior art date
Application number
TW94102287A
Other languages
Chinese (zh)
Other versions
TW200627461A (en
Inventor
Chung-Hui Chen
Original Assignee
Faraday Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Faraday Tech Corp filed Critical Faraday Tech Corp
Priority to TW94102287A priority Critical patent/TWI263225B/en
Publication of TW200627461A publication Critical patent/TW200627461A/en
Application granted granted Critical
Publication of TWI263225B publication Critical patent/TWI263225B/en

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a tested circuit in the system. The system further includes a unit circuit having a plurality of input terminal couple to a plurality of signal path respectively, and an output terminal couple to the design under test. A gate circuit of the BIST circuit having an output terminal couple to one of input terminals of the unit circuit, one input terminal couple to a non-timing-critical path of the signal paths, and the other input terminal receives a test signal. When the system operates in a test mode, the BIST controller provides the test signal through the gate circuit and the unit circuit to test the design under test.
TW94102287A 2005-01-26 2005-01-26 Circuit and method for built-in self test (BIST) and computer readable recording medium for storing program thereof TWI263225B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94102287A TWI263225B (en) 2005-01-26 2005-01-26 Circuit and method for built-in self test (BIST) and computer readable recording medium for storing program thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94102287A TWI263225B (en) 2005-01-26 2005-01-26 Circuit and method for built-in self test (BIST) and computer readable recording medium for storing program thereof

Publications (2)

Publication Number Publication Date
TW200627461A TW200627461A (en) 2006-08-01
TWI263225B true TWI263225B (en) 2006-10-01

Family

ID=37966299

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94102287A TWI263225B (en) 2005-01-26 2005-01-26 Circuit and method for built-in self test (BIST) and computer readable recording medium for storing program thereof

Country Status (1)

Country Link
TW (1) TWI263225B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI553648B (en) * 2014-07-07 2016-10-11 瑞昱半導體股份有限公司 Integrated circuit with self-verification function, verification method and method for generating a bist signature adjustment code.

Also Published As

Publication number Publication date
TW200627461A (en) 2006-08-01

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Legal Events

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MK4A Expiration of patent term of an invention patent