[go: up one dir, main page]

TWI261326B - IC three-dimensional package - Google Patents

IC three-dimensional package Download PDF

Info

Publication number
TWI261326B
TWI261326B TW094128166A TW94128166A TWI261326B TW I261326 B TWI261326 B TW I261326B TW 094128166 A TW094128166 A TW 094128166A TW 94128166 A TW94128166 A TW 94128166A TW I261326 B TWI261326 B TW I261326B
Authority
TW
Taiwan
Prior art keywords
substrate
wafer
integrated circuit
assembly
package structure
Prior art date
Application number
TW094128166A
Other languages
Chinese (zh)
Other versions
TW200709307A (en
Inventor
Yu-Pen Tsai
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094128166A priority Critical patent/TWI261326B/en
Application granted granted Critical
Publication of TWI261326B publication Critical patent/TWI261326B/en
Publication of TW200709307A publication Critical patent/TW200709307A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

An IC (integrated circuited) 3D (three-dimensional) package is disclosed, mainly including a first chip sub-assembly, a second chip sub-assembly and an encapsulant. Therein, the second chip sub-assembly is electrically connected to the first chip sub-assembly. The encapsulant combines the first and the second chip sub-assemblies to seal a plurality of chips therein and to allow the second chip sub-assembly is inclined to the first chip sub-assembly at an angle. Since the encapsulant combines the first and the second chip sub-assemblies, the encapsulating process and cost can be reduced. Moreover, it solves the conventional problem of fail of electrical connection resulted from substrate warpage by stress when a plurality of chip packages are vertically stacked.

Description

,1261326 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種積體電路立體封裝構造（Ic package)，特別係有關於一種共用封膠體之積體電路 封裝構造。 【先前技術】 習知積體電路立體封裝構造係將複數個晶片封裝件BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit package structure (Ic package), and more particularly to an integrated circuit package structure of a shared sealant. [Prior Art] A conventional integrated circuit three-dimensional package structure is a plurality of chip packages

縱向堆疊，以達到功能整合或是用以擴充 ^ 日日片 封襞件係個別以一封膠體密封該晶片封裝件之一晶片，並 在該些晶片封裝件之間係設置有一中介元件 (interposer)，例如中介基板或中介銲球，以連接相互堆叠 之該些晶片封裝件。通常該些晶片封裝件及其晶片之厚: 係被要求薄化’然而該些晶片封裝件會有變形或翹曲，導 致電性連接失敗。 言月多閱第1圖，一種已普遍採行之積體電路立體封』 :造100主要包含有可縱向堆疊之一第一晶片封裝件" 第曰曰片封裝件120，該第二晶片封裝件120係縱f 堆疊於該第-晶片封裝件11G上方，並在兩者之間設置_ 中介基板13G。該第―晶片封裝件UG係包含有—第—』 板11卜一第—晶片112及一第一封膠體113,該第一晶| 係設置於該第一基板iu之一上表面ιΐ4，並以複二 銲線116電性連接該卜晶片丄12與該第—基板111，言 第一封膠體113係形成於該第一基板111之該上表3 μ以密封該第—晶片112。該第二晶片封裝件⑽係爸 1261326 含有-第二基才反m、複數個第二晶片122及複數個第二 封膠體12 3，該此篦-曰Η ! 〇，y 一弟一日日片122係設置於該第二基板121 之一上表面1 2 4，並以禎數個捏始1 〇 复要個#線126電性連接該第二晶 片122與該第二基121’該些第二封腾體123係形成於 該第二基才反121之該上表…，以密封該些第二晶片 122。由於在封膠製程中，該第—封膠體⑴與該些第二 封膠體123係個別形成於該第—晶片封裝件11〇與該第二Longitudinally stacked for functional integration or for expansion. The Japanese package is individually sealed with a gel to seal one of the wafer packages, and an interposer is disposed between the chip packages. For example, an interposer substrate or an intermediate solder ball to connect the chip packages stacked on each other. Usually, the thickness of the chip packages and their wafers is required to be thinned. However, the chip packages may be deformed or warped, and the conductive connection may fail. Read more on the first picture, a commonly used integrated circuit three-dimensional seal: the manufacturing 100 mainly includes a first chip package that can be vertically stacked " the first chip package 120, the second chip The package member 120 is stacked vertically above the first chip package 11G with the interposer substrate 13G disposed therebetween. The first chip package UG includes a first-first plate 11 and a first sealing body 113, and the first crystal is disposed on an upper surface ι4 of the first substrate iu, and The first wafer 113 is electrically connected to the first wafer 111 and the first substrate 111. The first sealing layer 113 is formed on the upper surface of the first substrate 111 to seal the first wafer 112. The second chip package (10) is a dad 1261326 containing a second base, an inverse m, a plurality of second wafers 122, and a plurality of second encapsulants 12 3 , which is a day of the day. The sheet 122 is disposed on the upper surface of the second substrate 121 and is electrically connected to the second wafer 122 and the second substrate 121 by a plurality of pinch lines 126. The second sealing body 123 is formed on the upper surface of the second substrate 121 to seal the second wafers 122. In the encapsulation process, the first encapsulant (1) and the second encapsulant 123 are separately formed on the first chip package 11 and the second

晶片封裝件U0,因此該第一晶片封裝件ιι〇與該第二晶 片封裝件12〇之封裝製程需分別進行。此外，射介基板 no係以複數個銲球131、132分別導接至該第一基板⑴ 之該上表面m以及該第二基板121之一下表面125。並 可將複數個銲| 140接合於該第—基板lu之—下表面 115，以供該積體電路立體封裝構造1〇〇對外電性導接。 由於此-封裝堆疊方式對於薄化要求係相當高，該第一晶 片封衣件110與该第二晶片封裝件12G間之應力將使得該 第基板U1與该第二基板121變形翹曲，因此容易導致 應力集中處之部分銲球131或部分銲球132斷裂而造成該 第曰曰片封裝件11 0與該第二晶片封裝件1 20電性連接失 【發明内容】 本lx月之主要目的係在於提供一種積體電路立體封 装構4至^'一第一晶片組件係相對於一第一晶片組件呈 一角度傾斜，並且該第二晶片組件係電性連接該第一晶片 組件，-封膠體係形成於該第一晶片、缸件之一基板上表面 1261326 與该弟二晶片組件一 丨卞炙丞板内表面，以密封該第一晶κ知 件與該第二晶片細I —金 、、、 一曰 、、、牛之複數個㈤片。由於’該封膠體係為 口乂弟一日日片組件盘兮笛-曰Η知/；〇· ζ , ϋ亥第一曰曰片組件所共用，因此能減少封 ^程與成本，並能解決習知縱向堆疊複數個晶片封裝件 、應力使基板輕曲導致電性連接失敗之問題。 ^本發明之次一目的係在於提供一種積體電路立體封 f構k * 了包含有-第-晶片組件與至少-相對傾斜於 人專日日片組件之第二晶片組件，可另包含有一可撓性基 ，，其係電性連接該第一晶片組件之一第一基板與㈣: 曰曰片組件之一第二基板，以該可撓性基板具可彎折之特 ^在封膠‘第二晶片組件可任意傾斜於該第_晶片組 件’即使在封膠後殘留於該第二晶片組件之應力亦不會導 致與該第一晶片組件發生電性連接失敗之問題。 依據本發明，一種積體電路立體封裝構造主要包含一 第一晶片組件、至少一第二晶片組件、以及一封膠體，該 第一晶片組件係電性連接該第二晶片組件。該第一晶片組 件係包含一第一基板以及一設於該第一基板上之第一晶 片，該第一基板係具有一上表面以及一下表面並係包含有 複數個位於該下表面之外連接墊。該第二晶片組件係包含 一第二基板以及一第二晶片，該第二基板係具有一内表 面’該第二晶片係設置於該第二基板之該内表面。該封膠 體係形成於該第一基板之該上表面與該第二基板之該内 表面，並密封該第一晶片與該第二晶片，並且該第二晶片 組件係相對於該第一晶片組件呈一角度傾斜。 8 1261326 【實施方式】 請參閱第2、3及4圖，在本發明之第一具體實施例 ’ 中，一種積體電路立體封裝構造200主要包含—楚一曰u ^ 乐一晶片 組件210、至少一第二晶片組件220、以及一封膠體23〇。 如第3圖所示，在本實施例中四個第二晶片組件22〇係分 別位於該第一晶片組件2 1 0之四側邊，該此第一曰 一 yp _^日/ί、組仵 220係電性連接至該第一晶片組件2 i 〇。該第一晶片組件 210係包含一第一基板211以及一設置於該第一基板Η】 • 上之第一晶片212。該第一基板211係具有_上表面213 以及一下表面214並係包含有複數個位於該下表面214之 外連接墊215，以供該積體電路立體封裝構造2〇〇之對外 電性導接，該第一基板211係可為高密度多層印刷電路 板。該第一基板211之内部線路結構（圖未繪出）係能使該 些外連接墊215電性連接至該第一基板211之該上表Z 213，且該第一基板211之上表面側邊或下表面側邊可形 成有複數個導接指（圖未繪出），以供電性導接該些第二晶 片組件220。在本實施例中，可藉由打線技術形成之複2 個銲線216電性連接該第一晶片212與該第一基板211， 或者，該第一晶片212亦可以覆晶接合（fHp bonding)、内引腳接合（Ιη_ ⑽㈣）、捲帶自動接 合（Tape Automated Bonding)等方式電性連接至該第一基 板 211 。 土 請再參閱第2圖，每一第二晶片組件22〇係包含_第 一基板221以及一第二晶片222，該第二基板係具有 1261326 一内表面223以及一外表面224(如第2及4圖所示）。而 該第二晶片222係設置於該第二基板221之該内表面 . 223，可藉由打線形成之複數個銲線225或其它晶片接合 方式電性連接該第二晶片222與該第二基板221。在本實 施例中，該些第二基板221係為硬質電路板，並可利用軟 硬板接合技術將複數個可撓性基板226連接該些第二基板 221至該第一基板211之側邊，因此即使該些第二晶片組 件220與該第一晶片組件2 1 〇殘留應力，亦不會導致該些 參 第二晶片組件220與該第一晶片組件2 1 0電性連接失敗。 如第3圖所示，在尚未形成該封膠體23〇之前，該些第二 曰曰片組件220係可展開在該第一晶片組件2 i 〇之外側邊， 以利該些可撓性基板226電性連接該些第二基板221與該 第一基板211 ;如第4圖所示，在形成該封膠體23〇時， 係先將该些第二晶片組件220係被往上彎折，並將該第一 晶片組件2 1 0與該些往上彎折之第二晶片組件22〇設置於 參一杈具内或其它治具内（圖未繪出），之後可藉由壓模之方 式形成該封膠體230，以密封該第一晶片組件21〇之第一 晶片212與該些第二晶片組件22〇之該些第二晶片222， 在脫模後係使得該些第二晶片組件22〇相對於該第一晶片 組件210呈一角度傾斜，較佳地，該傾斜角度可介於 3〇〜150度。在本實施例中，該傾斜角度大體為九十度，即 該些第二基板22丨係直立於該第一基板211之一側邊。因 此’在本實施例中，能在該第一基板2丨丨之四側邊直立更 夕數里之该些第二晶片組件22〇,以共用同一封膠體23〇。 1261326 请再參閱第2圖，該封膠體23〇係形成於該第一基板 211之該上表面213與該些第二基板221之該些内表面 223，以結合該第一晶片組件21〇與該些第二晶片組件 220’並密封該第一晶片組# 21〇之該第一晶片叫盥該 些第二晶片組件22G之該些第二晶片222，且使該第= 片組件220係相對於該第_晶片組件川呈—角度傾斜。 該封膠體230係顯露該第—基板211之該下表面214與該 第二基板221之該外表面224。此外，該積體電路立體封 裝構造2GG可另包含有複數個銲球24()，例如錫斜辉球或 無錯銲球，其係接合於該些外連接墊215，可使該積體電 路立體封裝構造200具有球格陣列封裝（BGA)型態。但亦 能以錫膏、引腳、插針、電鍍潤濕層等對外導電物質取代 該些銲球240。 ^由於，該封膠體230係為該第一晶片組件210與該些 第二晶片組件220所共用，該第一晶片組件21〇與每一第 二晶片組件220並不需要形成個別的封膠體，因此，能減 少封膠製程與成本，並能解決習知縱向堆疊複數個晶片封 裝件時因應力使基板翹曲導致電性連接失敗之問題。 請參閱第5及6圖，在本發明之第二具體實施例中， 另一種積體電路立體封裝構造3〇〇主要包含一第一晶片組 件3 1 0、至少一第二晶片組件32〇、以及一封膠體33〇。在 本實施例中，該積體電路立體封裝構造3〇〇係包含有兩個 第二晶片組件320，其係位於該第一晶片組件31〇之兩對 應侧邊。該第一晶片組件3丨〇係包含一第一基板3丨丨以及 1261326 ， 一設置於該第一基板3 11上之第一晶片3 1 2。該第一基板 ^ 3Π係具有一上表面313以及一下表面314並係包含有複 . 數個位於該下表面3 1 4之外連接墊3丨5，以供對外電性導 接。在本實施例中，該第一晶片312係藉由複數個凸塊31 6 覆晶接合至該第一基板311。並可在該第一晶片312與該 第一基板3 11之間形成一底部填充膠材3丨7，以密封該些 凸塊3 1 6，防止應力集中。 清再參閱第5圖，每一第二晶片組件32〇係包含一第 _ 一基板321以及一第二晶片322，該第二基板320係具有 一内表面323以及一外表面324。而該第二晶片322係可 藉由複數個凸塊325設置於該第二基板321之該内表面 323，例如覆晶接合或其它晶片設置方式。在本實施例中， 該些第二基板321係為可撓性基板，其係具有一延伸彎折 部321A，以電性連接該第一晶片組件31〇之該第一基板 311。該些第二晶片組件32〇係能被往上彎折，使其相對 於該第一晶片組件3丨〇呈一角度傾斜。如第6圖所示，較 •佳地，該些第二晶片組件320之該些第二基板321係具有 一扣接部326例如插孔與插梢等，藉由該些第二基板321 之該些扣接部326,使得該些第二基板321相互扣接，以 利該些第二基板321能在無外力辅助下立於該第一基板 3 11之側邊。 可利用點膠液態膠之封裝技術形成該封膠體330,其 係形成於該第-基板3U之該上表自313與該第二基板 321之該内表面323，並且該封膠體33〇係密封該第一晶 12 1261326 片312與該些第二晶片322，並使該第二晶片組件wo係 相對於該第一晶片組件3 i 〇呈一角度傾斜。由於不需要縱 向堆疊複數個晶片封裝件而能整合至少一傾斜於第一基 板3 12側邊之第二晶片組件32〇，該封膠體33〇於該第一 晶片組件310之該第一晶片311上方係可設置一散熱器 3 40或堆疊更多晶片。該散熱器34〇係設置於該第一晶片 3U上並可利用一導熱介面物質341(Thermal Interface Material，TIM)熱耦合至該第一晶片3li之一背面，以利該 積體電路立體封裝構造3〇〇臂欠熱。纟本實施例中，該封膠 體330係顯露該第一基板311之該下表面314，複數個鲜 球350係可接合於該些外連接墊315。由於，該封膠體 係為該第-晶片組彳31G與該些第二晶片組彳32〇所共 用’乂該第-晶片組件31〇與每—第二晶片組件32{)並不需 要形成個別的封膠體，故能減少封膠製程與成本，並能解 ^知縱向堆疊複數個晶片封裝件時因應力使基板魅曲 V致電性連接失敗之問題。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者， — 个脱離本發明之精神和 靶圍内所作之任何變化與修改， J屬於本發明之保護範 圍0 圖式簡單說明】 第1圖：習知積體電路立體封裝構造 ^ 不馎w之截面不意圖。 弟2圖：依據本發明之第一具 貫知例’一種積體電路立 體封裝構造之截面示意圖。 13 1261326The chip package U0, therefore, the packaging process of the first chip package ιι and the second wafer package 12 需 is separately performed. In addition, the dielectric substrate no is guided to the upper surface m of the first substrate (1) and the lower surface 125 of the second substrate 121 by a plurality of solder balls 131 and 132, respectively. A plurality of solders 140 may be bonded to the lower surface 115 of the first substrate lu to be externally electrically connected to the integrated circuit package. Since the thinning requirement is relatively high, the stress between the first wafer package 110 and the second chip package 12G will cause the first substrate U1 and the second substrate 121 to be warped, thus The portion of the solder ball 131 or the portion of the solder ball 132 that is easily damaged at the stress concentration is broken, thereby causing the first chip package 10 0 and the second chip package 1 20 to be electrically disconnected. [Inventive content] The main purpose of the present invention Is to provide an integrated circuit three-dimensional package 4 to a first wafer assembly is inclined at an angle with respect to a first wafer assembly, and the second wafer assembly is electrically connected to the first wafer assembly, a glue system is formed on the inner surface 1261326 of the first wafer and the cylinder member and the inner surface of the slab of the second wafer assembly to seal the first crystal gamma and the second wafer. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Because 'the sealant system is the same as the one-day film component 兮 曰Η 曰Η 曰Η 曰Η 曰Η 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰The problem of conventionally stacking a plurality of chip packages and stresses causing the substrate to be lightly curved causes electrical connection failure. The second object of the present invention is to provide an integrated circuit package having a second wafer assembly including a - wafer assembly and at least - relatively inclined to a human day wafer assembly, which may further comprise a a flexible base, which is electrically connected to one of the first substrate of the first wafer component and (4): a second substrate of the cymbal component, wherein the flexible substrate has a bendable feature The second wafer assembly can be arbitrarily tilted to the first wafer assembly. Even if the stress remaining in the second wafer assembly after sealing is not caused by the failure of electrical connection with the first wafer assembly. According to the present invention, an integrated circuit three-dimensional package structure mainly includes a first wafer assembly, at least one second wafer assembly, and a gel, the first wafer assembly being electrically connected to the second wafer assembly. The first wafer assembly includes a first substrate and a first wafer disposed on the first substrate, the first substrate having an upper surface and a lower surface and including a plurality of connections outside the lower surface pad. The second wafer assembly includes a second substrate and a second wafer, the second substrate having an inner surface. The second wafer is disposed on the inner surface of the second substrate. The encapsulation system is formed on the upper surface of the first substrate and the inner surface of the second substrate, and seals the first wafer and the second wafer, and the second wafer assembly is opposite to the first wafer assembly Tilt at an angle. 8 1261326 [Embodiment] Please refer to Figures 2, 3 and 4, in a first embodiment of the present invention, an integrated circuit three-dimensional package structure 200 mainly includes a Chuyi ^ u ^ music module component 210, At least one second wafer component 220, and a gel 23 〇. As shown in FIG. 3, in the present embodiment, the four second wafer assemblies 22 are respectively located on the four sides of the first wafer assembly 2 1 0, and the first first yp _ ^ day / ί, group The 仵220 is electrically connected to the first wafer component 2i. The first wafer component 210 includes a first substrate 211 and a first wafer 212 disposed on the first substrate. The first substrate 211 has an upper surface 213 and a lower surface 214 and includes a plurality of connection pads 215 outside the lower surface 214 for external electrical connection of the integrated circuit three-dimensional package structure 2 The first substrate 211 can be a high density multilayer printed circuit board. The internal circuit structure (not shown) of the first substrate 211 is configured to electrically connect the external connection pads 215 to the upper surface Z 213 of the first substrate 211, and the upper surface side of the first substrate 211 A plurality of guiding fingers (not shown) may be formed on the sides of the side or the lower surface to electrically connect the second wafer assemblies 220. In this embodiment, the first wafer 212 and the first substrate 211 are electrically connected by a plurality of bonding wires 216 formed by a wire bonding technique, or the first wafer 212 may be flip-chip bonded (fHp bonding). The inner lead is bonded to the first substrate 211 by means of internal pin bonding (Ιη_(10)(4)), tape auto-bonding bonding, or the like. Referring again to FIG. 2, each of the second wafer assemblies 22 includes a first substrate 221 and a second wafer 222 having an inner surface 223 and an outer surface 224 (eg, second). And 4 shows). The second wafer 222 is disposed on the inner surface of the second substrate 221. 223, the second wafer 222 and the second substrate are electrically connected by a plurality of bonding wires 225 formed by wire bonding or other wafer bonding methods. 221. In this embodiment, the second substrate 221 is a rigid circuit board, and a plurality of flexible substrates 226 can be connected to the sides of the second substrate 221 to the side of the first substrate 211 by using a soft and hard board bonding technique. Therefore, even if the second wafer assembly 220 and the first wafer assembly 2 1 〇 residual stress, the second wafer assembly 220 and the first wafer assembly 2 1 0 are not electrically connected to each other. As shown in FIG. 3, before the encapsulant 23 is formed, the second cymbal assembly 220 can be unfolded on the side of the first wafer assembly 2i to improve the flexibility. The substrate 226 is electrically connected to the second substrate 221 and the first substrate 211. As shown in FIG. 4, when the encapsulant 23 is formed, the second wafer assembly 220 is first bent upward. And the first wafer component 210 and the second wafer component 22 that is bent upward are disposed in the cookware or other fixtures (not shown), and then can be pressed by the stamper. The sealing body 230 is formed to seal the first wafer 212 of the first wafer assembly 21 and the second wafers 222 of the second wafer assembly 22, and the second wafers are removed after demolding. The assembly 22 is inclined at an angle relative to the first wafer assembly 210. Preferably, the angle of inclination may be between 3 〇 and 150 degrees. In this embodiment, the angle of inclination is substantially ninety degrees, that is, the second substrate 22 is erected on one side of the first substrate 211. Therefore, in the present embodiment, the second wafer assemblies 22 can be erected on the four sides of the first substrate 2 to share the same encapsulant 23A. 1261326 Please refer to FIG. 2 again, the encapsulant 23 is formed on the upper surface 213 of the first substrate 211 and the inner surfaces 223 of the second substrates 221 to bond the first wafer assembly 21 to The second wafer assembly 220' and the first wafer group of the first wafer assembly #21 are called the second wafers 222 of the second wafer assemblies 22G, and the first wafer assembly 220 is opposite. The _th wafer component is inclined at an angle. The encapsulant 230 exposes the lower surface 214 of the first substrate 211 and the outer surface 224 of the second substrate 221. In addition, the integrated circuit three-dimensional package structure 2GG may further include a plurality of solder balls 24 (), such as tin oblique glow balls or error-free solder balls, which are bonded to the outer connection pads 215, and the integrated circuit can be The three-dimensional package structure 200 has a ball grid array package (BGA) type. However, the solder balls 240 can also be replaced by external conductive materials such as solder paste, pins, pins, and electroplated wetting layers. The first wafer assembly 210 and the second wafer assembly 220 do not need to form an individual sealing body, because the first wafer assembly 210 and the second wafer assembly 220 are shared by the first wafer assembly 210. Therefore, the sealing process and the cost can be reduced, and the problem that the electrical connection failure occurs due to the warpage of the substrate caused by the stress in the conventional longitudinal stacking of the plurality of chip packages can be solved. Referring to FIGS. 5 and 6, in a second embodiment of the present invention, another integrated circuit three-dimensional package structure 3 〇〇 mainly includes a first wafer component 310, at least a second wafer component 32, And a gel 33 〇. In this embodiment, the integrated circuit three-dimensional package structure 3 includes two second wafer assemblies 320 located on opposite sides of the first wafer assembly 31. The first wafer assembly 3 includes a first substrate 3 丨丨 and 1261326 , and a first wafer 312 disposed on the first substrate 311 . The first substrate has an upper surface 313 and a lower surface 314 and includes a plurality of connection pads 3丨5 outside the lower surface 314 for external electrical connection. In this embodiment, the first wafer 312 is flip-chip bonded to the first substrate 311 by a plurality of bumps 31 6 . An underfill material 3丨7 may be formed between the first wafer 312 and the first substrate 3 11 to seal the bumps 316 to prevent stress concentration. Referring again to FIG. 5, each of the second wafer assemblies 32 includes a first substrate 321 and a second wafer 322 having an inner surface 323 and an outer surface 324. The second wafer 322 can be disposed on the inner surface 323 of the second substrate 321 by a plurality of bumps 325, such as flip chip bonding or other wafer placement. In this embodiment, the second substrate 321 is a flexible substrate having an extended bent portion 321A for electrically connecting the first substrate 311 of the first wafer assembly 31. The second wafer assembly 32 can be bent upwardly at an angle relative to the first wafer assembly 3A. As shown in FIG. 6 , the second substrate 321 of the second chip assembly 320 has a fastening portion 326 , such as a socket and a spigot, etc., by the second substrate 321 . The fastening portions 326 are configured to fasten the second substrates 321 to each other, so that the second substrates 321 can stand on the side of the first substrate 3 11 without external force assistance. The encapsulant 330 can be formed by using a dispensing technique of a dispensing liquid glue, which is formed on the inner surface 323 of the first substrate 3U from the 313 and the second substrate 321, and the encapsulant 33 is sealed. The first wafer 12 1261326 is 312 and the second wafer 322, and the second wafer assembly is inclined at an angle relative to the first wafer assembly 3 i . The second wafer assembly 32 is inclined to the side of the first substrate 3 12 without the longitudinal stacking of the plurality of chip packages, and the sealing body 33 is disposed on the first wafer 311 of the first wafer assembly 310. A heat sink 340 can be placed on top or more wafers can be stacked. The heat sink 34 is disposed on the first wafer 3U and can be thermally coupled to the back surface of the first wafer 3Li by a thermal interface material 341 (TIM) to facilitate the integrated circuit three-dimensional package structure. 3〇〇 The arm is not hot. In this embodiment, the encapsulant 330 exposes the lower surface 314 of the first substrate 311, and a plurality of fresh balls 350 can be bonded to the outer connection pads 315. Since the encapsulation system is shared by the first wafer set 31G and the second chip sets 32, the first wafer component 31 and each second chip component 32 do not need to be formed individually. The sealing body can reduce the sealing process and cost, and can solve the problem that the substrate fascination V is failed due to the stress when the plurality of chip packages are stacked vertically. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made within the spirit and scope of the invention are known to the skilled artisan. Scope of protection 0 Simple description of the figure] Fig. 1: The stereoscopic package structure of the conventional integrated circuit is not intended. Figure 2 is a schematic cross-sectional view showing a first embodiment of the integrated circuit package structure according to the present invention. 13 1261326

依據本發明之第一具體實施 封裝構造在封膠之前將第-曰 路立體 面示意圖。 —曰曰片組件展開之平 封裝構造在封膠之前將第-日 路立體 立之平面示意圖。 卞$折成直According to a first embodiment of the present invention, the package structure is a schematic view of the first side of the first path before sealing. —The flattening of the cymbal assembly. The package structure is a schematic plan view of the first-day stereo before the seal.卞$ folded into straight

依據本發明之第二具體實施例 立體封裝構造之截面示意圖。 另一種積體電路A schematic cross-sectional view of a three-dimensional package construction in accordance with a second embodiment of the present invention. Another integrated circuit

第6圖：依據本發明之第二具體實施例， 封裝構造在封膠之前將第二曰 接成直立之平面示意圖。【主要元件符號說明】 該積體電路立體 片組件彎折並扣 100積體電路立體封裝構造Figure 6: In accordance with a second embodiment of the present invention, the package construction is a schematic view of the second splicing in an upright plane prior to encapsulation. [Description of main component symbols] The integrated circuit three-dimensional chip assembly is bent and buckled. 100 integrated circuit three-dimensional package structure

11 〇第一晶片封裝件 hi第一基板 112第一晶片 114上表面 Π5下表面 120第一晶片封裝件 121第二基板 122第二晶片 124上表面 125下表面 130中介基板 131銲球 140銲球 11 3第一封膠體 11 6銲線 123第二封膠體 126銲線 1 3 2鲜球 2〇〇積體電路立體封裝構造 2 1 0第一晶片組件 211第一基板 212第一 213上表面 14 126132611 〇 first chip package hi first substrate 112 first wafer 114 upper surface Π 5 lower surface 120 first chip package 121 second substrate 122 second wafer 124 upper surface 125 lower surface 130 intermediate substrate 131 solder ball 140 solder ball 11 3 first encapsulant 11 6 bonding wire 123 second encapsulant 126 bonding wire 1 3 2 fresh ball 2 convolutional circuit three-dimensional package structure 2 1 0 first wafer assembly 211 first substrate 212 first 213 upper surface 14 1261326

214 下表面 215 外連接 塾 216 銲 線 220 第一晶片 組 件 221 第二基板 222 第二晶 片 223 内 表面 224 外表面 225 銲線 226 可撓性基板 230 封膠體 240 銲球 300 積體電路 立 體封裝構造 310 第一晶片 組 件 311 第一基板 312 楚一曰 曰曰 片 313 上 表面 314 下表面 315 外連接 墊 316 凸 塊 3 17 底部填充 膠 材 320 第二晶片 組 件 321 第二基板 3 2 1A延伸彎折部 322 第二晶片 323 内表面 324 外表面 325 凸塊 326 扣 接部 330 封膠體 340 散熱器 341 導熱介面 物 質 350 鍀·球 15214 lower surface 215 outer connection 塾 216 bonding wire 220 first wafer assembly 221 second substrate 222 second wafer 223 inner surface 224 outer surface 225 bonding wire 226 flexible substrate 230 encapsulant 240 solder ball 300 integrated circuit three-dimensional package structure 310 first wafer assembly 311 first substrate 312 曰曰曰 313 313 upper surface 314 lower surface 315 outer connection pad 316 bump 3 17 underfill material 320 second wafer assembly 321 second substrate 3 2 1A extension bend 322 second wafer 323 inner surface 324 outer surface 325 bump 326 fastening portion 330 sealing body 340 heat sink 341 thermal interface material 350 鍀 · ball 15

Claims (1)

1261326 十、申請專利範圍： . 1、一種積體電路立體封裝構造，包含·· - 一第一晶片組件，其係包含一第一基板以及一設於該 第一基板上之第一晶片，該第一基板係具有一上表面 以及一下表面並係包含有複數個位於該下表面之外 連接墊； 至少一第二晶片組件，其係包含一第二基板以及一第 一晶片，该第二基板係具有一内表面，該第二晶片係 _ "又置於忒第一基板之該内表面，該第二基板係電性連 接至該第一基板；以及 一封膠體，其係形成於該第一基板之該上表面與該第 二基板之該内表面，並密封該第一晶片與該第二晶 片，並且該第二晶片組件係相對於該第一晶片組件呈 一角度傾斜。 2、 如申請專利範圍第1項所述之積體電路立體封裝構 造，更包含有一可撓性基板，其係電性連接該第一基 板與該第二基板。 3、 如申請專利範圍第2項所述之積體電路立體封裝構 造’其中該第二基板係為硬質電路板。 4、 如申請專利範圍第2項所述之積體電路立體封裝構 造，其中該可撓性基板係一體形成於該第二基板。 5、 如申請專利範圍第丨項所述之積體電路立體封襄構 造’其中該角度大體為九十度。 6、 如申請專利範圍第1項所述之積體電路立體封装構 16 I261326 造’其中該第二基板係直立於該第一基板之一侧邊。 7、妒申請專利範圍第丨項所述之積體電路立體封裝構 造，其中該封膠體係顯露該第一基板之該下表面與該 第二基板之一外表面。 g、妒申請專利範圍第丨或7項所述之積體電路立體封裝 媾造，另包含有複數個銲球，其係接合於該些外連接 费。1261326 X. Patent application scope: 1. An integrated circuit three-dimensional package structure comprising: a first wafer assembly comprising a first substrate and a first wafer disposed on the first substrate, The first substrate has an upper surface and a lower surface and includes a plurality of connection pads outside the lower surface; at least one second wafer assembly including a second substrate and a first substrate, the second substrate Having an inner surface, the second wafer is placed on the inner surface of the first substrate, the second substrate is electrically connected to the first substrate, and a gel is formed on the The upper surface of the first substrate and the inner surface of the second substrate seal the first wafer and the second wafer, and the second wafer assembly is inclined at an angle relative to the first wafer assembly. 2. The integrated circuit three-dimensional package structure of claim 1, further comprising a flexible substrate electrically connected to the first substrate and the second substrate. 3. The integrated circuit three-dimensional package structure of claim 2, wherein the second substrate is a rigid circuit board. 4. The integrated circuit three-dimensional package structure according to claim 2, wherein the flexible substrate is integrally formed on the second substrate. 5. The integrated circuit structure of the integrated circuit as described in the scope of the patent application, wherein the angle is substantially ninety degrees. 6. The integrated circuit three-dimensional package structure according to claim 1, wherein the second substrate is erected on one side of the first substrate. 7. The integrated circuit three-dimensional package structure of claim 1, wherein the encapsulation system exposes the lower surface of the first substrate and an outer surface of the second substrate. g. 妒 妒 妒 妒 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 妒申明專利範圍第丨項所述之積體電路立體封裝構 造，其中該封膠體係為壓模形成或是點膠形成。 妒申請專利範圍第丨項所述之積體電路立體封裝構 造，另包含有一散熱器，其係設置於該第一晶片上。 妒申睛專利範圍第1項所述之積體電路立體封裝構 造，其中每m组件係具有一扣接冑，以供相 矣扣接。 12、/種積體電路立體封裴構造，包含·· /第一晶片組件，其係包含一第一基板以及一第一晶 • 片； 至少一第二晶片組件，其係包含一第二基板以及一第 二晶片，· 件，並使该第二晶片組件係相對於該 一角度傾斜，該封膠體係為該第一晶 晶片組件所共用。 可撓性基板’其係連接第一基板與該二基板；以及 封膠體，其係結合該第一晶片組件與該第二晶片組 第一晶片組件呈 片組件與該第二 17 1261326 1 3、如申請專利範圍第1 2項所述之積體電路立體封裝構 造，其中該封膠體係為壓模形成。The invention relates to the integrated circuit three-dimensional package structure described in the above paragraph, wherein the encapsulation system is formed by stamping or dispensing. The integrated circuit three-dimensional package structure according to the above aspect of the invention, further comprising a heat sink disposed on the first wafer. The integrated circuit three-dimensional package structure described in claim 1 is characterized in that each m component has a fastening 胄 for snapping. 12. The integrated circuit of the integrated circuit, comprising: a first wafer assembly comprising a first substrate and a first wafer; and at least a second wafer assembly comprising a second substrate And a second wafer, and the second wafer component is tilted relative to the angle, the encapsulation system being shared by the first wafer assembly. a flexible substrate 'which connects the first substrate and the two substrates; and a sealant that is coupled to the first wafer assembly and the second wafer set first wafer assembly to form a sheet assembly and the second 17 1261326 13 The integrated circuit three-dimensional package structure according to claim 12, wherein the encapsulation system is formed by compression molding. 1818
TW094128166A 2005-08-18 2005-08-18 IC three-dimensional package TWI261326B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094128166A TWI261326B (en) 2005-08-18 2005-08-18 IC three-dimensional package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094128166A TWI261326B (en) 2005-08-18 2005-08-18 IC three-dimensional package

Publications (2)

Publication Number Publication Date
TWI261326B true TWI261326B (en) 2006-09-01
TW200709307A TW200709307A (en) 2007-03-01

Family

ID=37876151

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094128166A TWI261326B (en) 2005-08-18 2005-08-18 IC three-dimensional package

Country Status (1)

Country Link
TW (1) TWI261326B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI423405B (en) * 2011-02-18 2014-01-11 鉅景科技股份有限公司 Package structure with carrier

Also Published As

Publication number Publication date
TW200709307A (en) 2007-03-01

Similar Documents

Publication Publication Date Title
US6462412B2 (en) Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
TWI278947B (en) A multi-chip package, a semiconductor device used therein and manufacturing method thereof
TWI277187B (en) Semiconductor device and manufacturing method for the same
TWI290365B (en) Stacked flip-chip package
TWI415201B (en) Multi-wafer stack structure and its preparation method
JP2002353398A (en) Semiconductor device
US20060012018A1 (en) Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
JP2001077294A (en) Semiconductor device
TW201511209A (en) Semiconductor device and method of manufacturing the same
JPWO2002103793A1 (en) Semiconductor device and manufacturing method thereof
JP2014512688A (en) Flip chip, face up and face down center bond memory wire bond assembly
TWI242869B (en) High density substrate for multi-chip package
TW432558B (en) Dual-chip packaging process and method for forming the package
US20110197438A1 (en) Method of manufacturing semiconductor device
TW587325B (en) Semiconductor chip package and method for manufacturing the same
TW201025554A (en) Multiple flip-chip package
TW200529387A (en) Chip package structure
TWI261326B (en) IC three-dimensional package
TWI357653B (en)
CN102779760B (en) Process and Structure of Mounted Substrate Multi-die Package
CN101005062A (en) Vertically packaged MOSFET and ic power devices as integrated module using 3D interconnected laminates
CN112614830A (en) Encapsulation module and electronic equipment
TWI306217B (en) Insertion-type semiconductor device and fabrication method thereof
TWI278049B (en) Stackable back-to-back flip chip package
TW484221B (en) A dual chip package and the wafer level packaging method

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent