1260792 九、發明說明： 【發明所屬之技術領域】 本發明係有關於轉體封裝領域，制是有關於—種可降低晶 片熱應力的晶片封裝體結構。 【先前技術】 • 在現今的封裝技術中，高效率電子元件通常都利用焊錫球 (solder balls)或是焊錫凸塊(solder bumps)來達到彼此之間電性和機 械性連接的目的。舉例來說，超A型積體(_㈣她 integration，VLSI)便是利用焊錫球或是焊錫凸塊而與一電路板 (circuitboard)或其他次級封裝基底相連接。這 種連接技術稱為覆晶接合(flip_chip，FC)。覆晶接合屬於面積陣列式 (areaarmy)的接合，因此能應用於極高密度的構裝連線製程。 _ 單絲，覆晶接合峨念係先在IC晶#的上長成焊錫 凸塊’然後再將1C晶片i放到構裝基板上並完成接墊對位後，並 以回焊_〇W)熱處理配合焊錫溶融時之表面張力效應使焊錫成 球，進而完成1C晶片與構裝基板之接合。這種方式不僅可突破傳 統打線技術的數目限制，適合多腳數元件封裝，而且電性效能也 因具有較短的内連線(connection pass)而大幅提升。 請參考第1 ® ’其_的是習知難觀構的示賴。如第！ 1260792 圖所示，封裝體ίο包含有-晶片12與一基板18，其中晶片η 上具有複數憾塊雜Η分継接相對應之焊接錫球16，並且經 由焊接錫球16連接至基板1S表面。晶片12與基板以之間設有 一底部密封層(underfill layer)20,用來填滿晶片12與基板18之間 的空隙，以使晶片12與基板18緊密結合。 在習知封裝技術中，基板可由塑膠或陶瓷等材料構成，其中陶 瓷基板的價格較為昂貴，因此價格相對低廉的塑膠基板即成為目 前封裝製程之主要材料。然而，使用塑膠基板卻也使得封裝體經 常遭遇到熱應力不均勻的問題，舉例來說，矽晶片的熱膨脹係數 約為2.7ppm/°C，而塑膠基板的熱膨脹係數約為i7ppmrc，因此 畲外界環境的溫度發生變化時，晶片與塑膠基板即可能因為熱膨 脹係數不匹配而導致封裝體結構變形、介電層界面脫層(interface delamination)，甚至導致產品失效。 為了降低熱應力，目前的作法是調整底部密封層20的熱膨脹 係數以及玻璃轉化溫度(Tg)，然而，卻必須在晶片内部的低介電常 數介電層的保護上與熱應力降低之間做取捨，此外，底部密封層 2〇的熱膨脹係數或玻璃轉化溫度的調整十分複雜。由此可知，傳 統覆晶封裝製程在解決熱應力問題上未臻理想，而猶待進一步克 服改善。 1260792 【發明内容】 ‘本变發明之主要目的在提供—種⑼封裝體結構，可解決習知技 藝中覆晶封I的熱應力以及界©脫層問題。 根據本發明之較佳實補，本發明提供—賴晶職體結構， 包含有H基板；-雜電路晶糊定顧職基板上，其中 該積體電路晶方包含有-絲積體電路以及—包猶絲積體電 路的晶方封環，·以及-熱應力釋餘，設於_位於該晶方封環外 侧的-應力職肖落區軸’其巾雜應力釋放墊經由一輝接錫 球與該封錄減錢結，職焊魏賴與以在該封裝基板 内的-虛4散熱金屬板連接，藉此形成—散熱路徑，以在該覆晶 _體結構進行-溫度循環職時能將熱傳導出去，藉此降低教 應力。 #、 a為了使貴審查委員能更進一步了解本發明之特徵及技術内 各《月多閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與輔助說明用，並非用來對本發明加以限制者。 【實施方式】 本發明提供-種製作在積體電路晶片或晶方的四個較脆弱之 角落處的餘雜，可祕覆晶職觀行溫度循賴試過程中 有效地將累積的熱傳導出去’藉此降低晶方四讎跪弱角落處的 熱應力。 1260792 顏-、咅^第―2圖及第3圖，其中第2圖纟會示的是封農體励的上 二=，=3 _示的是第2圖中沿著切線w之剖面示意圖。 回及弟3圖所示’封震體雇具有積體電路晶方⑽，其固 122以2基板⑽上。積體電路晶方12G包含—主動積體電路 的曰方:於積體電路晶方120週邊並且包圍著主動積體電路122 的日日万封環124。 、& 124由許多層的金屬以及介層插塞相互堆疊而成，這 晶片保護結構在該技術領域中乃常見之技術，主要是用來避免 主動積體電路122糾晶圓蝴時的應力破壞 以為單層阻擒牆結構，但亦可以是雙層結構。曰曰方封衣 人=之晶方封環124是在製造主動電路122的同時，以相同的 二電層沈積步驟以及金屬沈顏卿步驟逐步向场疊而成。通 2先在铸縣射’修魏材，軸絲純細未示）， ，、、、、後再將晶方封環124形成在重摻雜區域上，並允許特定的電壓， 例如接地電麗或者Vss經由重摻雜區域提供給晶方封環以。 主動積體電路122可包括有電晶體、電容 體陣繼金械峨蝴。树__她動^ Γ路122具有四鍋落位置的應力釋放區㈣，其位於晶方封 % 124的外側。如第2圖中的虛線所示，在每個應力釋放區域⑶ ’提供有-熱應力釋放墊128，其係與位於晶方封環124内側的 1260792 主動積體電路122的轉接墊同時製作完成。 如第3圖所示，在每個應力釋放區域126内的轉接墊128其周 圍口I5分被保護介電層丨3〇覆蓋。第3圖中並未顯示出填充於積體 電路晶方120與封裝基板18〇之間的底部密封層。被暴露出來的 轉接墊128藉由焊接錫球140與封裝基板180連接，主要是經由 封裝基板180上的轉接墊145以及介層插塞148連接至封裝基板 180内具有較大面積的虛設散熱金屬板15〇。虛設散熱金屬板 的表面積需大於轉接墊128表面積至少50倍以上為佳。 此外’虛設散熱金屬板150亦連接至設於封裝基板18〇另一面 的轉接墊160。在轉接墊160上設有焊接錫球17〇，用來連接至一 印刷電路基板(圖未示）。另外，封裝基板18〇可以由玻璃、樹脂或 其它材料構成，其可以具有多層的電路，彼此藉由介層插塞構成 電連結。 在應力釋放區域126内的轉接墊128下方另設有一散熱金屬堆 疊結構226，其係與主動積體電路122的金屬内連線同時完成。散 熱金屬堆疊結構226的製作與主動積體電路122的金屬内連線的 製作同樣是由層層的介電層與金屬導線層定義而成，在兩金屬導 線層之間則以介層插塞連結。如第3圖所示，散熱金屬堆疊結構 226可包含形成在基底230表面上的接觸插塞231、第一金屬層 232、第一介層插塞233、第二金屬層234、第二介層插塞235、第 1260792 三金屬層236、第三介層插塞237以及連接至轉接墊128的第四金 屬層238。 本發明藉由散熱金屬堆疊結構226、轉接墊128、焊接錫球 140、虛設散熱金屬板150、轉接墊160以及焊接錫球170構成一 散熱路徑，而可以在覆晶封裝體1〇〇進行溫度循環測試過程中有 效地將累積的熱傳導到印刷電路板上，藉此降低晶方12〇四個較 脆弱角落處的熱應力。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均㈣倾修飾，冑觸本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示的是習知封裝體結構的示意圖。 第2圖繪示的是封裝體励的上視示意圖。 第3圖繪示的是第2圖中沿著切線I-Ι之剖面示意圖。 12607921260792 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of swivel packaging, and is related to a chip package structure that can reduce thermal stress of a wafer. [Prior Art] • In today's packaging technology, high-efficiency electronic components usually use solder balls or solder bumps to achieve electrical and mechanical connection between them. For example, a Super A-type integrated body (VLSI) is connected to a circuit board or other secondary package substrate using solder balls or solder bumps. This bonding technique is called flip chip bonding (FC). Flip-chip bonding is an area-area joint and can therefore be applied to very high-density component wiring processes. _ Monofilament, flip-chip bonding mourning first grows solder bumps on IC crystal #', then puts 1C wafer i on the package substrate and completes the pad alignment, and reflows _W The heat treatment is combined with the surface tension effect during solder melting to form the solder into a ball, thereby completing the bonding of the 1C wafer and the package substrate. This method not only breaks through the limitation of the number of traditional wire bonding technologies, but also is suitable for multi-pin component packaging, and the electrical performance is greatly improved by having a short connection pass. Please refer to the 1 ® ’ _ is a well-known demonstration. As the first! As shown in FIG. 1260792, the package ίο includes a wafer 12 and a substrate 18, wherein the wafer η has a plurality of solder balls 16 corresponding to the plurality of solder bumps, and is connected to the surface of the substrate 1S via solder balls 16. . An underfill layer 20 is disposed between the wafer 12 and the substrate for filling the gap between the wafer 12 and the substrate 18 to closely bond the wafer 12 to the substrate 18. In the conventional packaging technology, the substrate may be made of a material such as plastic or ceramic, and the ceramic substrate is relatively expensive, so that the relatively inexpensive plastic substrate becomes the main material of the current packaging process. However, the use of plastic substrates also causes the package to often suffer from thermal stress non-uniformity. For example, the thermal expansion coefficient of the germanium wafer is about 2.7ppm/°C, and the thermal expansion coefficient of the plastic substrate is about i7ppmrc. When the temperature of the environment changes, the wafer and the plastic substrate may cause deformation of the package structure, interface delamination, and even product failure due to a mismatch in thermal expansion coefficient. In order to reduce thermal stress, the current practice is to adjust the thermal expansion coefficient of the bottom sealing layer 20 and the glass transition temperature (Tg). However, it is necessary to do between the protection of the low-k dielectric layer inside the wafer and the reduction of thermal stress. In addition, the adjustment of the coefficient of thermal expansion or the glass transition temperature of the bottom sealing layer 2 is complicated. It can be seen that the conventional flip chip packaging process is not ideal for solving the thermal stress problem, and it is still to be further improved. 1260792 [Disclosed Summary] The main object of the present invention is to provide a (9) package structure which can solve the thermal stress and the boundary delamination problem of the flip chip I in the prior art. According to a preferred embodiment of the present invention, the present invention provides a structure of a Lai crystal body, comprising an H substrate; and a circuit for crystallizing a paste on a substrate, wherein the integrated circuit includes a wire-forming circuit and - the crystal square sealing ring of the circuit, and the thermal stress relief, which is located on the outer side of the crystal ring, the stress-relief release pad The ball is subtracted from the seal, and the welder Wei Lai is connected with the dummy 4 heat sink metal plate in the package substrate, thereby forming a heat dissipation path for performing the temperature cycle in the flip chip structure. It can conduct heat out, thereby reducing the stress. #, a In order to enable the reviewing committee to have a better understanding of the features and techniques of the present invention, each of the following is a detailed description of the present invention and the accompanying drawings. The drawings are to be considered in all respects as illustrative and not restrictive. [Embodiment] The present invention provides a kind of remnant at the four fragile corners of an integrated circuit wafer or a crystal, and can effectively conduct the accumulated heat during the temperature recovery process. 'This reduces the thermal stress at the weak corners of the square. 1260792 颜-, 咅^第第2图和图图3, where the second figure 纟 shows the upper two ===3 _ shows the section along the tangential line in the second figure . Back to the 3rd figure, the seal body employs an integrated circuit crystal (10), which is fixed on the 2 substrate (10). The integrated circuit crystal 12G includes a square of the active integrated circuit: a day-to-day sealing ring 124 surrounding the integrated circuit crystallographic 120 and surrounding the active integrated circuit 122. , & 124 is formed by stacking a plurality of layers of metal and via plugs. This wafer protection structure is a common technique in the art, and is mainly used to avoid the stress of the active integrated circuit 122 during wafer rectification. Destruction is thought to be a single-layer barrier wall structure, but it can also be a two-layer structure. The square sealing ring 124 is formed by stacking the active circuit 122 with the same two-electrode deposition step and the metal sinking step. Pass 2 first in the casting county to 'repair the Wei material, the shaft is pure fine not shown), ,,,, and then form the square sealing ring 124 on the heavily doped area, and allow a specific voltage, such as grounding Li or Vss is supplied to the square ring via a heavily doped region. The active integrated circuit 122 may include a transistor, a capacitor array, and a gold butterfly. The tree __ she moves the road 122 with a stress relief zone (four) at the four-pot position, which is located outside the square seal % 124. As shown by the broken line in Fig. 2, a thermal stress relief pad 128 is provided in each of the stress relief regions (3), which is simultaneously fabricated with the transfer pad of the 1606792 active integrated circuit 122 located inside the square sealing ring 124. carry out. As shown in Fig. 3, the transfer pad 128 in each stress relief region 126 has its peripheral opening I5 covered by a protective dielectric layer 丨3〇. The bottom sealing layer filled between the integrated circuit crystal chip 120 and the package substrate 18A is not shown in Fig. 3. The exposed transfer pads 128 are connected to the package substrate 180 by solder balls 140, and are mainly connected to the dummy substrate having a large area in the package substrate 180 via the transfer pads 145 and the via plugs 148 on the package substrate 180. The heat sink metal plate is 15 turns. The surface area of the dummy heat sink metal plate is preferably at least 50 times larger than the surface area of the transfer pad 128. Further, the dummy heat dissipation metal plate 150 is also connected to the transfer pad 160 provided on the other side of the package substrate 18. Solder balls 17 are provided on the transfer pad 160 for connection to a printed circuit board (not shown). Further, the package substrate 18A may be made of glass, resin or other material, and may have a plurality of circuits which are electrically connected to each other by a via plug. A heat dissipating metal stacking structure 226 is disposed beneath the transfer pad 128 in the stress relief region 126, which is completed simultaneously with the metal interconnect of the active integrated circuit 122. The fabrication of the heat dissipation metal stack structure 226 and the fabrication of the metal interconnection of the active integrated circuit 122 are also defined by a layer of dielectric layers and metal wire layers, with a dielectric plug between the two metal wire layers. link. As shown in FIG. 3, the heat dissipation metal stack structure 226 may include a contact plug 231 formed on the surface of the substrate 230, a first metal layer 232, a first via plug 233, a second metal layer 234, and a second via layer. A plug 235, a 1260792 metal layer 236, a third via plug 237, and a fourth metal layer 238 connected to the transfer pad 128. The heat dissipation metal stack structure 226, the transfer pad 128, the solder ball 140, the dummy heat dissipation metal plate 150, the transfer pad 160, and the solder ball 170 form a heat dissipation path, and can be in the flip chip package 1 The accumulated heat is effectively conducted to the printed circuit board during the temperature cycling test, thereby reducing the thermal stress at the four weaker corners of the crystal 12 。. The above is only the preferred embodiment of the present invention, and all of the four (4) modifications made in accordance with the scope of the present invention are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a conventional package. Figure 2 is a schematic top view of the package excitation. Figure 3 is a cross-sectional view taken along line II-Ι in Figure 2; 1260792
【主要元件符號說明】 10 封裝體 12 晶片 14 凸塊焊墊 16 焊接錫球 18 基板 20 底部密封層 100 封裝體 120 積體電路晶方 122 主動積體電路 124 晶方封壞 126 應力釋放區域 128 轉接墊 130 保護介電層 140 焊接錫球 145 轉接墊 148 介層插塞 150 虛設散熱金屬板 160 轉接墊 170 焊接錫球 180 封裝基板 226 散熱金屬堆疊結構 230 基底 231 接觸插塞 232 第一金屬層 233 第一介層插塞 234 第二金屬層 235 第二介層插塞 236 第三金屬層 237 第三介層插塞 238 第四金屬層 11[Main component symbol description] 10 Package 12 Wafer 14 Bump pad 16 Solder ball 18 Substrate 20 Bottom sealing layer 100 Package 120 Integrated circuit crystal 122 Active integrated circuit 124 Crystal sealing 126 Stress relief area 128 Transfer pad 130 protective dielectric layer 140 solder ball 145 transfer pad 148 via plug 150 dummy heat sink metal plate 160 transfer pad 170 solder ball 180 package substrate 226 heat sink metal stack structure 230 substrate 231 contact plug 232 a metal layer 233 a first via plug 234 a second metal layer 235 a second via plug 236 a third metal layer 237 a third via plug 238 a fourth metal layer 11