TWI260070B - A trench and a trench capacitor and method for forming the same - Google Patents

Abstract

A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. This step is performed in such a way that the topmost layer provided on the trench wall is constructed from a sealing material. A selective epitaxy method is carried out in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate and preferably no semiconductor material grows directly on the sealing material. A partial trench is etched in a surface of the epitaxially grown semiconductor layer. This step is performed in such a way that at least part of the layer made of the sealing material is uncovered. An uncovered part of the layer made of the sealing material is then removed.

Description

1260070 IX. The invention relates to: a trench manufacturing method, a trench capacitor manufacturing method, a memory cell manufacturing method, a trench, a trench capacitor, and the trench The memory unit of the slot capacitor is related. [Prior Art] The memory cells of dynamic random access memories (DRAMs) generally include a storage valley and a selection transistor (selecti〇n廿. The information stored in the storage capacitor expresses the logic quantities 0 and 1 in the form of charges. By word line, the word line is used to drive the read-out transistor or the transistor, and the data stored in the age capacitor can be read from the bit line (10) line. For the reliability of charge storage and the distinguishability of data readout, the storage capacitor must have the lowest capacitance value. At present, the capacitance of the storage capacitor memory density - generation - generation increase, - f crystal memory unit needs the lowest capacitance value up to the generation of t, read (four) crystal and electricity. From the 4Mbit memory generation to the + face 兀 以 进 进 进 进 进 进 进 进 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In it Π Π 储存 储存 储存 储存 储存 储存 储存 it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it Cross-sectional area - resulting. Reducing the cross-sectional area of the trench while increasing the depth of the trench further increases the density of the encapsulation. In the past, many methods have been developed to increase the value of the storage capacitance of the trench capacitor, which is the thickness of the fine storage dielectric layer. Further, step through the internal surface of the trench capacitor (bottle) using Cheng chemical expansion. In addition, the roughness is varied to increase the area within the trench, for example, by coating a hemispherical grain (HSG).

Advanced methods include increasing the doping to reduce the electron consumption of the capacitor electrode, or using a metal electrode to greatly reduce the resistance. In addition, in order to increase the capacitance of the trench capacitor, the previous-oxygen dielectric can be replaced by a tapped dielectric. It may be related to the high dielectric constant dielectric, or metal electrodes, especially the temperature sensitivity of these metals. In addition, in fact, new technologies need to be developed first to get new materials. In order to produce a high aspect ratio trench structure, ie a ratio of depth to diameter or width, it is necessary to optimize the parameters of the etch stack hard mask and the etch trench, for example by energy, plasma density, frequency, bias, Etching gas: The most suitable parameters of pressure 'flow, side time and so on. In addition, the thickness and material of the individual layers of the hard mask are also optimized. However, current etching methods for fabricating trench capacitors are increasingly approaching technical and economic limits. For example, because the etch rate and etch selectivity decrease as the etch depth increases. As a result, the surface of the hard mask used to etch the trench has been etched away by a large area. At the same time, the maximum aspect ratio that the current technology can achieve is estimated to be about 60 to 70. U.S. Patent Application Serial No. 102 02,140, the entire disclosure of which is incorporated herein by reference. German and U.S. patents are incorporated herein by reference. For example, the method can be formed by filaments--the trenches of the capacitors, which are completed only after the high temperature (four) is applied, and the trenches are laterally epitaxially grown only after the high temperature step is implemented. [Description of the Invention] This invention is intended to provide a method for producing a high aspect ratio trench. Another object of the present invention is to provide a method of producing a high aspect ratio trench. . Another object of the present invention is to specifically refer to a method of manufacturing a memory cell having the above-described trench capacitor. Moreover, embodiments of the present invention provide a trench, a trench capacitor', and a memory cell having the trench capacitor.

In accordance with a preferred embodiment of the present invention, a trench manufacturing method basin includes a semiconductor substrate that provides - in the form of a rotating body, the semiconductor substrate having a surface. The surface of the semiconductor substrate is covered by an opening, and the two openings are -. At least a layer or fill is provided to mask the sidewalls and to make the surface of the opening scream. The semiconductor layer is formed on the surface of the semiconductor substrate, and the surface of the opening covered by the sealing material is grown to complete a selective silicidal method. Reading 曰, = growing the surface of the semiconductor layer on the surface side of the local trench, so that the sealing material = eve - part without covering. Finally, the uncovered portion of the sealing material layer is removed, thereby completing the trench. i: In other words, the method of making a trench involves providing a semi-conductive plate that is composed of a semiconductor material. Faceted semi-conductor plate surface ^ 8 1260070

The layer wall is provided on the wall of the trench to provide a top-of-the-line i! L3⁄4 step to form the most crystalline layer provided on the wall of the trench. A selective insect crystal method is implemented to make the monolithic crucible grow longer than the substrate and there is no semiconductor material directly. The epitaxial growth semiconductor layer etches a structural layer composed of a sealing material. The knot is followed by the Kodak, which is composed of the sealing material section. The specific embodiment of the invention provides a method for detecting a groove having a particularly high aspect ratio on the conductor substrate by the developed technique. It is used in the field of reporting a wide range of width-to-depth ratios. The method of manufacturing, the shank is provided as a method of manufacturing a trench capacitor, which includes the method steps of the aforementioned money-groove, and provides a neighboring groove. a manufacturing step of the #1 capacitor electrode '#1 dielectric and an upper capacitor electrode, which is at least partially disposed therein. Therefore, in accordance with a specific embodiment of the present invention, in principle, on a bulk substrate by a conventional method Forming an electric rotating groove, the capacitor groove is covered by appropriate cleaning. The surface of the tube is not exposed. In particular, the groove wall is provided with at least a structural layer, so that the uppermost layer provided on the groove wall is sealed by material Next, after removing the etching mask of the remaining trenches, a single crystal germanium layer by epitaxial growth of the substrate surface by selective epitaxy is performed. In other words, a smoothing is produced on the surface of the base 9 1260070 board. The closed epitaxial layer, the trench etched on the substrate is completely retained. It is understandable that the trench wall is covered by a suitable method, in particular, the advantage of the selective epitaxy method is that the trench wall is not Covered, the selective epitaxy method is constructed from a non-elemental sealing material, which is a single-body dream, a polycrystalline dream or a non-crystalline dream, a non-metallic material, a non-material material, such as ·· And / or bismuth. Further, the crystal layer is selectively used to grow the structural layer in the single crystal germanium layer region.

More specifically, a selective epitaxial method generally uses a gas mixture, for example, containing si lane or dichloromethane (/iChl〇rosilane), and an etching gas such as hydrogen chloride. The selective epitaxy method uses an etching gas to etch an idle speed and different effects on different materials. Therefore, in particular, the parameters of the method are set such that the growth rate of the single crystal is smaller than that of the single crystal, and thus, the thickness of the layer formed by the Shi Xishi is increased. For example, in contrast, the multi-(4) seed layer on the dioxide (5) (8) sealing material is _ much larger than the slave generation rate. As a result, since the region covered by the sealing material grows laterally, the crucible grows only on the surface region of the single crucible - a layer of the stupid crystal single crystal 11 is formed in the region. 2至1· 8倍。 The flow rate of the gas is usually 1. 2 to 1.8 times. First, on the μ core cut layer, relying on the transmission, the wealth and the private part of the gully, the sand _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ At least a portion of the mouth layer is not covered. Manufactured by the above method steps, it is possible to manufacture any technique that can be obtained from the target, so that the manufacture of high aspect ratio electric power can be achieved. Because existing manufacturing methods are available, the cost of development is saved. Furthermore, it is possible to achieve higher electrical values without the use of temperature sensitive materials, although the method according to the invention comprises the use of a temperature sensitive material. The method according to the invention can be embodied by various modifications. For example, after each etching step of the trench, a bottom capacitor electrode is provided, and the dielectric layer and the upper capacitor electrode are formed in trenches or portions of the side turns. Similarly, it is possible to start filling the trenches and provide the capacitor and dielectric layers only after all trench stacks have been completed. In addition, however, it is also possible to complete two or any number of partial trenches' or - one trench and one or more partial trenches after providing the capacitor electrode and completing the dielectric layer of the trench, and then down the worm layer Paving, side section grooves, and more. In addition, the steps of forming the bottom capacitor electrode, the dielectric layer and the upper capacitor electrode are implemented, and further, they can be processed in a suitable order. An example of epitaxial growth in an empty trench must be (four) increase the growth of two other methods, it is possible to introduce any sacrificial material: fill === slot stack or partial trench after completion ::::: The sacrificial material may comprise a highly doped dioxide, for example, by heating the step towel to perform the doping-domain. , the side Μ is in the next field...i匕ί 如—The capacitor electrode or a dielectric material shop is only after the gully Feng Yuancheng, in this case then it is possible to provide a sense of heat under the heat load of the stone seal The temperature material, such as: knocking value 1260070, the thickness of the electrode (four) layer is preferably smaller than the groove side of the semiconductor substrate 22 volts for etching the trench sidewall of the epitaxial growth layer can be set as a target. Part of the groove is recorded, and the diameter of the groove in the lower part is = the advanced element of the unit is compatible with the uppermost crystal

Two: two points ' Especially the choice of transistor and bit line contact points. Therefore, the capacitance m is required to be smaller and has a higher capacitance value. f Its 'dielectric layer is a dioxide dioxide / nitrite (Si3N4) stacked layer or only dioxide or nitrite, oxidized (10) (10)), tin oxide (Ti 〇 2), oxidized I (Ta2 〇 5) or other high k dielectrics. Appropriately used as the bottom capacitor f, the material of the capacitor electrode and the material of the t-layer are used as materials. In particular, the material of the capacitor electrode may be a high-doping compound, a metal electrode with a doped layer adjacent to the substrate, a metal stack and The barrier layer' is formed of an insulating layer disposed between the substrate and the metal layer and is occluded, often in a lower region, in order to bring the substrate into contact with the metal layer. In particular, the Wei layer is composed of a metal of H point, such as titanium nitride (TiN), crane (w), group (Ta), _〇, or other materials having a high melting point, which is suitable as a metal. f pole material. Each of the epitaxial growth layers may be doped, which is different from the underlying structural layer. The doping level depends on the electrical properties. In addition, the bottom capacitor electrode and the upper capacitor electrode and the material for storing the dielectric may be used in each of the partial trenches, which is different from the material of the other partial touch or bottommost capacitor electrode. A specific embodiment of the present invention is at least partially disposed in a trench by a trench capacitor having a bottom capacitor electrode, an electrical 12 1260070 dielectric material, and an upper capacitor electrode, wherein the bottom capacitor electrode is adjacent to a groove wall, and said groove has a minimum diameter and a depth, said depth to said diameter ratio being greater than 70, especially greater than 80, particularly greater than or equal to 85. Embodiments of the present invention provide a trench capacitor having a high aspect ratio to provide a trench capacitor having a particularly small space requirement for high storage capacitance. In the flat illustration, the capacitor trench is usually elliptical rather than circular. In other words, there are two diameters along two different cross-sectional directions. If the trench etched onto the semiconductor substrate has the same diameter as all of the trenches, the minimum diameter corresponds to the smallest or smallest width of all of the trenches. On the other hand, if the uppermost groove has a diameter at least one direction smaller than the groove below it, the minimum diameter corresponds to the minimum diameter of the uppermost groove. According to a further aspect, the present invention provides a half-conducting substrate comprising a first substrate portion composed of a single crystal semiconductor material, a second substrate portion composed of the single crystal semiconductor material, the second substrate portion defining a substrate surface; and a plurality of trenches extending toward a vertical substrate surface, the trench being formed on the first substrate portion. In particular, the thickness of the second substrate portion ranges between 6 〇〇 nm and 3 〇〇〇 nm 'mainly between 800 and 1500 nm. [Embodiment] The following is a detailed description of the manufacture and use of the preferred embodiments of the present invention. ^ And it is appreciated that the invention concept of the multi-system of the present invention can be diversified in the form of mosquitoes. The specific embodiments of the present invention are merely illustrative of the use of the invention in its manufacture and use, but do not limit the scope of the invention 13 1260070. According to a first embodiment of the present invention, a total depth of about 11. 8 乜 乜 乜 乜 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In this example, after each trench is etched, the bottom capacitor electrode and the storage dielectric and the upper capacitor electrode are directly provided. However, it is apparent that, in accordance with the present invention, trenches of all depths are first etched, and the bottom capacitor electrode, the storage capacitor dielectric, and the upper capacitor electrode are fabricated by well known methods. According to FIG. 1, the surface 1 of the semiconductor substrate 2 is a ceria layer 3 having a thickness of gnm and a nitride layer 4 having a thickness of 220 nm (for example, tantalum nitride), and a borophosphorus glass layer having a thickness of 62 nm ( Not shown in the figure) is laid on it. The specific thicknesses indicated herein are for illustrative purposes only and other thicknesses may be used. The borophosphonium silicate glass layer, the tantalum nitride layer 4, and the SiO2 layer 3 are defined by a lithography mask (not shown), for example, A/A/Trifluoromethane (CIL/CHF3) The plasma is etched to form a hard mask. The trench 5 is engraved in the main area 1 using the hard shield as the insect shield, for example, further using hydrogen bromide/nitrogen trifluoride (HBr/NFs) plasma etching. A groove wall 31 in the groove 5 is not covered. Thereafter, the boron-filled glass layer is removed, for example, by a sulfuric acid/hydrogen acid (H2SO4/HF) method. For example, the trench 5 has a depth of 6.6 Å, a width of about 1 〇〇 to 250 nm, and a trench pitch of 10 〇〇 nm. The structure as shown in Fig. 1 is thus produced. In the next step, an n + doped region 6 is used to fabricate the bottom capacitor electrode 6a. As shown in Fig. 2, it is a step of heat treatment of 2 sec. at 1 degree Celsius to form a layer of arsenic_d ped silicate glass with a thickness of 50 nm and a thickness. The 20 volt tetraethoxy zexi pit is a second layer of 12 1260070 矽 (TEOS-Si〇2) layer. In this example, the bottom capacitive electrode, such as the doped region 6, of the individual capacitors in the completed memory cell configuration is formed by the outward diffusion of the arsenic doped tellurite glass layer on the conductor substrate 2. A gas phase doping method is another option, for example: the parameters are as follows, Celsius cut, 3 Torr. TBA (tributylarsine) [33%], 12 minutes. – removal of the arsenic-doped tellurite glass layer and the TEOS-31〇2 layer, for example: re-use of ammonium/germanium fluoride (Li 4/hf) etching step selective for tantalum nitride and niobium . After that, the density of 4. 7ηπι nitride and a thickness of 1.5 nm are used as the dielectric layer 7. Alternatively, the dielectric layer 7 comprises oxidized, tin oxide, oxidized buttons or other conventional dielectric materials. Next, a 3 〇〇 nm doped polysilicon layer 8 is deposited as an upper capacitor electrode at the same location. The structure as shown in Fig. 2 is thus produced. Thereafter, the polycrystalline layer 8 is planarized using chemical mechanical _ (CMP). According to Fig. 3, the polycrystalline germanium filler 8 is etched back by 10 nm from the surface of the semiconductor substrate 2. For example, this step is performed with sulfur hexafluoride (SF0). Next, a sealing layer 9 composed of, for example, cerium oxide is formed on the trench filling surface as shown in Fig. 4. For example, this may be filled by a layer The thermal oxidation is completed. In this example, the thickness of the sealing layer 9 is about 9 to 12. The thickness of the layer can also be determined by depositing a layer of sulphur dioxide after the plasma plasma (HDP) method. Approximately 15 nm. Thereafter, the remainder of the hard mask 4 is removed by a conventional method; the structure as shown in Fig. 5 is thus produced. Thereafter, as shown in Fig. 6, a selective epitaxial method is used, for example, A single crystal germanium layer having a thickness of 5 Å is grown on the surface 1 of the US plate. For example, the epitaxial method can be used in a 15 〇〇 26 〇〇 7 〇 chemical vapor deposition (CVD) method using a temperature of Celsius _ degrees and a flow rate of 180 sccm ( Under standard conditions, every cubic centimeter per cubic centimeter of methane and a temperature of celsius, a flow rate of 6Qsccm of hydrogen chloride. In this example, an epitaxial cavity is formed in the center of each sealing layer 9. „ As seen in Section 6®, the semi-conducting plate contains a base-based group of monocrystalline semiconductor lions. a portion 2, a second substrate portion 11 composed of a single crystal semiconductor material, the second substrate portion iM1 being a worm layer, the basin portion being exposed; the portion above, and - the surface of the second substrate portion Defining - the surface of the substrate; the number of the fine 5 directions - extending in the direction of the surface of the silk plate, forming the groove 5 in the first substrate portion 2. In particular, the thickness of the second substrate portion may be between 60 〇 nm and 3 ,, The pattern is defined by the method of 4, and the pattern is defined in the worm-like layer 11 and the side-out groove is adjacent to the groove of the previous side. As shown in Fig. 7, the first thickness is 3 of the cerium oxide layer 3 and a thickness of 22 〇 nm of the nitride material 4 are again and secondly spread on the surface of the selectively grown worm layer 丨i ^ 艺 16, a thickness of 62 〇 之 硼 矽 矽 glass layer 12 After being coated thereon, the photoresist layer 13 is coated according to a conventional method. The mask for defining the first trench pattern is also used for the exposure of the photoresist layer 13, however, the opening may be used. Small reticle. The alignment of the lower trench structure 5 is preferably done by a special alignment mask. The pattern and shift are defined by the hard mask layer lithography. After the photoresist layer 13, then, the etchant (4) RIE trench (10) (4) is freshly transferred onto the insect layer 11 and stopped by the sealing layer 9 of the lower cladding groove 5. Relative to the oxidation After being selectively flanked by a structure such as that shown in Fig. 8, thus 16 1260070 is produced, the ruthenium seal layer 9 is removed using dihydrogen hydrofluoric acid (DHF), as shown in Fig. 9. After that, the bottom capacitor electrode and the storage dielectric are formed on the etched portion of the trench in a manner similar to that described in Fig. 2. However, in general, during the formation of the bottom capacitor electrode, in order to avoid partial trenching Doping must take into account the coverage of a portion of the upper trench region where the insulating ring is formed later. Alternatively, it is of course possible to generate bottom capacitance electrodes and store springs by other conventional methods. Thereafter, as shown in Fig. 10, a spacer material 14, such as ruthenium (no crystal ruthenium), has a conformal deposition thickness of about 15 to 2 Å. As shown in Fig. 11, the spacer layer 14 of the bottom portion trench 5 and the storage dielectric layer 7 are removed by reactive ion etching. The dielectric layer 7 on the vertical trench walls is protected by the spacer layer 14 by reactive ion etching to remove the interlayer. After the spacer layer 14 is removed by selective wet etching, the trench 5 on the epitaxial layer is filled with a polysilicon layer 8 having a thickness of 300 nm. The structure as shown in Fig. 12 is thus produced. • As shown in Fig. 12, a trench 5 having a large depth is formed on the germanium substrate and the monocrystalline germanium layer thereon. The bottom capacitor electrode 6 is formed continuously in two trench regions; in this example, the dielectric layer 7 and the upper capacitor electrode 8 overlap and contact at the trench transistor, but this does not affect the function of the trench capacitor. ^More Steps, as a storage capacitor of a conventional memory cell structure and a manufacturing method for selecting a transistor connected to one of the storage capacitors, the steps of the step and the memory cell structure are well known, and only for completeness Sex appears. Obviously, according to the invention, it can also be represented by any other unit every 17 1260070 as shown in Fig. 13. In the next step, the polycrystalline germanium is filled with 8 etch back to the epitaxial layer 16 under about 〇·9髀. Thereafter, a dielectric layer on the sidewalls of the uncovered trench is etched using conventional methods to define the depth of the insulating ring. Thereafter, a 25 nm thick ruthenium dioxide layer was deposited conformally. The ruthenium dioxide layer is etched anisotropically to form a ruthenium dioxide insulating ring in the upper portion of the trench. The cerium oxide insulating ring 17 serves to prevent the parasitic transistor from developing at this position.

Thereafter, an n+ doped polysilicon layer is deposited to fill the storage capacitor trenches in the annular region. The 14-layer layer of the parent crystal is about 12 () nm under the layered surface to prepare for subsequent embedding. The structure as shown in Fig. 13 is thus produced. The upper erbium oxide insulating ring region 17 is etched to remove the buried cover. To complete the embedding, after the nitridation process of the open stone surface, an n-doped polycrystalline dream layer is deposited again on the nitride layer 4 and planarized by a chemical mechanical polishing method. The deposited layer 8 is etched back by about 40 nm from the surface of the i-layer 11 . (Recess etching) The insulating structure 18 laterally defines the boundary of the active region. For this purpose, a phantom group (not shown) can be formed to freshen the active area. In the non-selective side process, _ drop nitrogen cut and dioxide dioxide and polycrystalline hardness are related to frequency. After that, remove the = cover. Then, by the oxidization of slaves, a thin layer of hot dioxygen is formed. "Next, the μ high-density plasma method deposits a thickness of 25 二 dioxide. The grinding of the nitride is performed using a wheel lion, using a chito-cut, - insulating and clearing, and removing the hard cover layer, namely nitrogen cut and dioxygen layer 3. 18 1260070 ^ „Γ Sacrificial oxide layer—shield oxide (sTM culvert) formed by 彳政影The reticle and implant form a narrow-filled fine-doped and erbium-doped well, and a choice of transistors in the surrounding and early 70-matrix matrices to implement the threshold V〇ltage implant. Further, high-energy ion implantation (so-called "B (4) "ell-Im thin") is performed to form an n-doped region 15 which is connected to the bottom.

# m =, ^ know the method steps, define the inter-oxidation zone and the impurity 21, which is equivalent to the connection and the source/no-pole 22. Next, the configuration of the essay unit is accomplished by forming a metal plate in a known manner. ^ Figure 14 is an overview of the memory unit. The simple dielectric and bottom capacitor electrode 6a, the storage dielectric 7 and the upper capacitor electrode 8 are disposed in each of the trenches 5, and are embodied by a polycrystalline fill. The upper capacitor electrode 8 is coupled to the first source/drain of the selective transistor 29 by a polycrystalline Wei 2g and a dummy region 19. The conductivity of the conductive path between the first and second source/drain electrodes 22a, 22b is a short-term thyristor. Figure 15 is a memory unit 8 F2 unit architecture (8 F2 architecture), a simple memory configuration, each memory configuration - Memory unit, - The storage capacitor is arranged in the - trench 5 and a planar selection transistor. (10) Space requirements 'F is the smallest feature size that can be manufactured in this technology. The bit lines (BL) are strip-shaped and parallel to each other, and have a width F and a pitch of f. In the flat illustration, the word line (the WL bit line, the ground, the width is f, and the distance is F. The active area is placed below the word line and the bit line, and the two character lines are placed on the active area. Adjacent to the bit line, there is an offset between each active area a. The bit line contact point (10) is disposed in the center of the active area A, and 19 1260070 has an electrical connection between each of the active lines and the active area A. . The trench 5 is disposed below the word line. In the active area A, an associated selective transistor gate 21 is formed at the intersection of a word line and a bit line. Active region A extends between the two trenches 5 and includes two select transistors coupled to associated bit lines by a common bit line contact. The information is read from the storage capacitor located in one of the trenches 5 or other trenches 5, as determined by the word line being driven.

Consistent with the second embodiment of the present invention, a trench capacitor is fabricated with a total depth of 22. For this purpose, after defining the bottommost capacitive groove stomach groove 5, the above method for producing an epitaxial growth layer is performed four times in total. However, it is apparent that the crystallization method can be implemented whenever necessary. In this example, a second embodiment is described in which the lower four trench regions are first fabricated, and then the bottom capacitor electric lion' is formed to form the dielectric layer 7, and the upper capacitor electrode 8 is fabricated. Then, the fourth epitaxial layer was thrown after the sealing layer was fabricated. The portion of the trench formed in the fourth crystal layer 25 has a lower groove (5) and a read area. The advantage is that the capacitance area can be greatly reduced while the capacitance value remains unchanged. However, it will be apparent that the methods described herein can be used in the first embodiment. The trench capacitor as shown in Fig. 16 is covered by the acoustic _-groove trench view in the same manner as in the first diagram. Fine, the groove depth is 5·2髀, the width is 2〇〇nm, and the pitch is 6〇nm. After the trench is cleaned, the thermal oxidation axis is used to cover the layer 27 on the fresh wall. Two, for example, = circumference. The cover layer 27 is used as a subsequent selective house crystal method... _ avoiding the a crystal growth in the trench 魄 also as the upper impurity layer u capacitor trench _ terminal two = 3 20 1260070 structure shown . After the cover layer 27 is laid, the hard mask is removed, which comprises the ruthenium dioxide layer 3 and the nitridation layer 4, which is the same as the first embodiment, and the same as the first embodiment is used to generate a single crystal selectivity. Insect crystal method. In particular, a chelate layer having a thickness of 4·3 生成 is produced by a chemical vapor phase/integration method using a temperature of 9 摄 degrees Celsius, a flow rate of 18 〇sccm of dichloro decane and a temperature of 9 摄 degrees, a flow rate of 60 sccm. Hydrogen chloride. The epitaxial layer 11 is grown laterally on the open trench 5, which is completely retained as a cavity. More specifically, the single crystal layer hides from the unfilled trench. The structure shown in Figure 18 is thus generated. In particular, as shown in Fig. 18, a semiconductor substrate comprising a -first semiconductor substrate portion 2 which is difficult to be formed of a single crystal semiconductor, and a second semiconductor substrate portion u composed of the single crystal and a conductor are provided. The second substrate portion U deposited on the surface is an epitaxial layer, and the surface of the second portion defines a surface of the substrate; and the plurality of trenches 5 extend toward a direction perpendicular to the substrate. A trench is formed in the first substrate portion 2. Next, the epitaxial growth layer η is defined in a pattern similar to that described above. In particular, the layer 2 of the oxidized stone layer, the layer of the nitride layer 4, and the layer 12 of the boron-breaking stone layer are again laid as a hard shield. - The photoresist layer 13 is coated and properly aligned to facilitate the return of the light. After the definition - hard fresh, such as the structure of the first Cong. As shown in Fig. 20, the trench is left in the i-layer η by the reactive ion magnetization method, and the etching is terminated by the cap layer 27 of the lower capacitor trench. The cover layer 27 is removed, for example, using dilute hydrofluoric acid to produce a structure as shown in Fig. 21, Fig. 21,600,070. The new retanning layer 27 then covers and covers the entire trench wall 3^. After removing the residual hard-belts 3 and 4, a chemical vapor phase dimerization method is again used to form a selective epitaxial layer having a thickness of 4.3 Å on the epitaxial layer 11. The second smectite layer 23 is also The pattern is defined in the foregoing manner, and the diameters of the worm layer and the worm layer 23 and the groove on the substrate 2 are the same. The capacitor groove is defined to be hard, and the pattern of the hood is generated as shown in Fig. 22. The method engraves a part of the trench on the second insect layer. The cover layer 27 is removed and deposited again on the entire surface of the groove. The hard finger cover is removed and the third crystal layer 24 is formed, and - The selective insect crystal method is completed. The structure as shown in Fig. 23 is thus produced. The second-time spreading-containing the dioxide layer 3, the nitride layer 4, and the stone plate 12 The photoresist layer is coated by a conventional method and exposed by the previous photolithography step. As in the previous step, the pattern of the hard mask is defined by photolithography. A portion of the trench is engraved on the second epitaxial layer. Next, the bottom capacitor electrode 6, the storage dielectric 7 and the upper capacitor electrode 8 are defined. In this example The bottom capacitor electrode is again formed by the n-doped region 6. By way of example, it may be an arsenic phthalic acid glass layer as described in the first embodiment. A subsequent heat treatment step of thickness 20 nm and 1 degree Celsius causes arsenic. The enamel glass layer is diffused outward to the semiconductor substrate 2, and the epitaxial layers u, 23, 24 are deposited thereon. The gas phase doping method is another method, for example, the parameters are as follows, 900 degrees Celsius, 3 Torr TBA (tributylarsine) [33%], 12 minutes. Then 'children's thickness of 4·7ηπι nitride layer and a thickness of 1 12 1260070: oxidized pheno layer as dielectric layer 7, then, co-position deposition of 3GQnm The multi-day stone 〇 〇 第 第 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The plasma method forms a tungsten dioxide seal layer 9 having a thickness of 12 nm to 15 nm, which is similar to the first embodiment. The crystal is smoked in the groove of the fourth crystal layer 25, and its width is smaller than the previous groove. In the XI example, the sealing layer 9 also ensures continuous insulation of the two capacitor electrodes 6, 8. For the final structural diagram, it can be seen that the epitaxial layer of the epitaxial layer deposited by about 4·3髀 is completed again. As shown in Fig. 24, similar to the first embodiment, the crystal is crystallized. The layer 25 is defined by a dioxide chopping layer 3, a nitride layer 4, and a borophosphon glass layer 12 as a hard mask, and the rear photoresist layer 13 is coated and exposed by a trench mask. The last pattern defines the trench. Preferably, the opening of the trough mask is smaller than before. The space requirement of the memory unit can be reduced, and a capacitance value of a high storage capacitor and a high conductivity upper electrode 8 can be obtained, as shown in Fig. 25, similar to The method described in FIG. 8 and FIG. 12 engraves a capacitor trench in the fourth epitaxial layer 25 silver. The region where the sealing layer 9 is not covered is removed, and the region is the portion exposed by etching the partial trench 30. Thereafter, the bottom capacitor electrode is formed in the upper trench region by the method described above, and it is customary to consider that the insulating ring formed by the uppermost trench needs to be properly protected from spreading. Thereafter, the dielectric layer 7 is formed according to a conventional method, and a spacer layer 14 is formed on the upper trench region of 23 1260070. The material of the spacer layer is as follows - the entire upper trench is separated by a spacer layer, 300 nm, as shown in FIG. The structure of the diagram is thus produced. S "full" thickness approximately completes the trench capacitance and is similar to the method of the first embodiment,

The advanced component Q for the memory unit is shown in Figures 26 and 27, according to the invention trench

==版段: The product is large, and the lower groove is defined by the upper groove: two, by the bottom capacitance, a, and the dielectric squeak/layer before the formation, Λ., and the power-up electrode 8 below The grooves are connected. The formation of the ^ shrink hole fills all the structural layers, in particular, the conductivity of the capacitor electrode 8 can be added. The dielectric sonar 7 of the upper and lower groove portions is stabilized by the horizontal part of the seal which is not sealed by the last part of the ditch, and (4) the electric trough groove side of the fourth house layer 25 can also be The upper and lower cross-sectional areas are the same. In this example, the first layer of the second layer of the capacitor electrode 6 and the upper capacitor is defined. In this example, it is advantageous for the capacitor electrode and the material to be incapable of being able to withstand the high thermal load in the process of viewing. In particular, by way of example, a layer of a lithiated layer with a doped layer can serve as Bottom capacitor electrode. - Suitable Wei material layer is - metal impurity layer, for example, refractory gold film layer (refract〇ry coffee is used to ground the underlying doping layer to the substrate. Formed below to replace the method 24 1260070 Furthermore, it is also possible to use a stack comprising a metal layer and a barrier layer. In this example, the barrier layer comprises an insulating layer, in particular cerium oxide, which is applied directly to the trench walls and is intended to be The metal layer is in electrical contact and the lower region is open. The metal layer comprises titanium nitride, tungsten, lift, M, or other refractory metal or metal compound. In particular, the so-called fused material can be used as a storage dielectric 'especially , polycrystalline stone or other metal, or metal debris can be the upper capacitor electrode.

The use of the above materials or a combination of the above materials as the upper capacitor, the dielectric layer 7 and the bottom capacitor electrode 6a can further increase the capacitance value. As another advanced variation method of the second embodiment, after the trench 5 is etched, the trench may also be filled with a sacrificial layer of the earth plate, such as - oxidized stone. As shown in Fig. 17, after a step of a part of the trench 3G, the method of sacrificing > 4, each of the etched starving layers 26 is filled, and the present invention is described in conjunction with the drawings. The meaning of the limit is limited. There are no examples of the embodiments of the present invention, but there is no such thing as a person skilled in the art. The invention is surrounded by various modifications. 25 1260070 [Schematic description of the drawings] Figs. 1 to 12 show the steps of manufacturing a trench capacitor in accordance with the first embodiment of the present invention. Figure 13 is a step of further fabricating a memory unit. Figure 14 is a cross-sectional view of the essential elements of a completed memory unit in a first embodiment of the present invention. Figure 15 is a layout of an 8 F2 unit structure. 16 to 26 are steps for fabricating a trench capacitor in accordance with a second embodiment of the present invention. Figure 27 is a cross-sectional view of the essential elements of a completed memory unit in a second embodiment of the present invention.

26 1260070

2 source / > and polar region [main component symbol description] A active region BLK bit line contact point 1 surface 3 ruthenium dioxide layer 5 trench 6a bottom capacitor electrode 8 capacitor electrode 10 worm cavity 12 borophosphide Glass-lined (BPSG) layer 14 spacer 16 stray layer surface 18 insulating structure 20 polycrystalline germanium filler 22a, 22b first and 23rd second epitaxial layer 25 dihroic layer 27 cladding layer 29 select transistor 31 groove Wall BL bit line WL word line 2 semiconductor substrate 4 tantalum nitride layer 6 n+ doped (n+-doped) region 7 dielectric layer 9 sealing layer 11 selective epitaxial layer 13 photoresist layer 15 n+ doped region 17 Insulation ring 19 doped region 21 gate electrode 24 third epitaxial layer 26 sacrificial layer 28 trench capacitor 30 portion trench 27

Claims (1)

1260070 f, the scope of the patent application is a method for manufacturing a trench, the method comprising: a semiconductor substrate composed of a semiconductor material, the semiconductor substrate wall having an opening on the surface of the semiconductor substrate, the opening having One side a total of one layer or filler' such that the sidewall is masked, and the surface of the opening is composed of a sealing material; the selective crystallization method enables the surface layer of the semiconductor substrate to be The read surface of the opening covered by the sealing material is grown laterally; the semiconductor layer is engraved with a portion of the trench such that at least a portion of the layer consisting of the layer of sealing material is not covered; the layer is uncovered The method of claim 2, wherein the selective insect crystal method is carried out by forming no semiconductor material directly on the sealing material. 3. If the method of applying the item 1 of the scope is applied, it further includes at least one layer of structure on the side wall of the knife groove so that the surface of the groove is composed of - material; The remote selective crystal method causes a second single crystal semiconductor layer to form a surface in which the surface of the portion of the trench covered by the sealing material laterally grows. A second portion of the trench is formed on the surface side of the second single crystal semiconductor layer such that at least a portion of the layer formed by the sealing material is removed from the odd axis. The method of claim 3, wherein at least the second portion of the trench has a diameter different from that of the knives/曰3. Windshield groove or the diameter of the opening of a H application _ _ 4th branch, shooting the part of the groove diameter, or the part of the groove diameter is smaller than the S method of applying for the ploughing Rarely - less than that etched on the rotating substrate, body 曰 7. 7. As claimed in the patent scope! The method of the item ^ a thickness of the mouth ice. Single crystal stone eve. The method of the semiconductor substrate comprises the method of the fourth aspect of the invention, as described in the fourth aspect of the patent application. W early + conductor layer package 9 · If the scope of the patent application scope is the same as the slot. , the towel pin mouth and the portion of the groove = the method of the T-side side of the item, wherein the portion is different from the diameter of the 4 opening diameter. ^曰/,^ (4) method 'the towel has a groove diameter of 12 · If the patent application fine magic slave method, the financial method is formed - adjacent to the opening - the bottom of the wall capacitor electrode; forming - adjacent to the bottom capacitance _ the capacitance Electrically-formed-adjacent to the capacitor electrode above the capacitor dielectric, wherein the bottom capacitor 29 1260070 electrode, the capacitor dielectric and the upper capacitor electrode at least part of the mouth; H, liu open 13. as claimed The method of item 12, wherein the towel is provided or the filler comprises the bottom forming capacitor electrode. The method of claim 13, wherein the method of claim 13 wherein at least - or the filler further comprises providing the capacitor dielectric. The method of claim 14, wherein the method of claim 14 provides at least - or the filler further comprises filling the opening with a filling material and covering the filled with a structural layer composed of a dense layer The surface of the opening. Material 16. If the method of claim 15 is applied, the material of the upper capacitor electrode is combined. 〃, °", is expected to be - suitable = · as in the method of claim 12, wherein the bottom electrode / capacitor dielectric and the upper capacitor electrode step = body layer after etching a part of the trench Implementation. ^Early Day + Guide The method of the first item of the patent scope, the towel is provided with a structure or the filler comprises a sacrificial layer. Ό 层 1 如 如 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Connecting semiconductors, such as applying for a dedicated chest coffee, (4) includes a method of manufacturing a memory cell having a storage capacitor, characterized by a trench 1260070 slot capacitor and a selection transistor, the method comprising: providing - by semiconductor material a semiconductor substrate having a surface; the surface of the semiconductor substrate is etched with an opening, the opening has a sidewall; at least one structural layer or filler is provided such that the sidewall is covered by the sidewall, and A generating surface of the opening is composed of a sealing material; Through-selective m, so that the surface of the conductor substrate is formed - a single crystal semiconductor layer, wherein a surface of the opening covered by the sealing material is laterally grown; and a surface of the semiconductor layer that is grown on the surface is partially engraved such that the layer of the sealing material constitutes the structural layer At least part of it is not covered, / the portion of the capping layer of the county layer shouted by the silk sealing material is removed to form a groove; the bottom is formed as a bottom capacitor electrode adjacent to the wall of the 5H trench; a capacitor dielectric adjacent to the bottom capacitor electrode; six = - adjacent to the tantalum capacitor dielectric - upper capacitor electrode, wherein the bottom gate is at least 5 parts of the dielectric and the upper capacitor electrode at least - part The invention is disposed on the formation-selecting transistor, and has a first source/no-polar, ^ and a second, and a material capacitor, and the upper capacitor is connected to the first source/drain of the electro-selective transistor. H. The method of claim 22, wherein selective epitaxy is performed on the soil without the semiconductor material directly growing on the sealing material. 31 1260070 24. A trench formed on a semiconductor body, the trench having a depth and a minimum diameter, and the ratio of the depth to the minimum diameter is greater than 7 〇. 25. The trench of claim 24, wherein the ratio of the depth to the minimum diameter is greater than 8 〇. 26. The trench of claim 25, wherein the depth is greater than or equal to 85 with respect to the minimum straight. 27. The trench of claim 24, wherein the trench comprises a trench φ trench capacitor portion, the trench capacitor further comprising: a bottom capacitor electrode adjacent to the trench wall; a capacitor dielectric Qualitatively adjacent to the bottom capacitor electrode; an upper capacitor electrode adjacent to the capacitor dielectric, wherein the bottom capacitor electrode, the capacitor dielectric, and the upper capacitor electrode are at least partially disposed in the trench. 28. The trench of claim 27, wherein the trench capacitor comprises a memory cell portion, the memory cell further comprising a selection transistor having first and second sources located in one of the semiconductor bodies a pole/drain φ region, a conduction channel at one of the first and second source/drain regions of the semiconductor body, and a gate above the conduction channel, the first source/drain region Connected to the upper capacitor electrode. 32