TWI259345B - Switching voltage regulator and its control method - Google Patents
Switching voltage regulator and its control method Download PDFInfo
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- TWI259345B TWI259345B TW93137298A TW93137298A TWI259345B TW I259345 B TWI259345 B TW I259345B TW 93137298 A TW93137298 A TW 93137298A TW 93137298 A TW93137298 A TW 93137298A TW I259345 B TWI259345 B TW I259345B
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Abstract
Description
1259345 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種切換式電壓調節器,尤其 可避免操作於不連續桓彳少+ ;~ ^ )+運、,杈式之切換式電壓調節器 功率轉換之效率。 猪以鈇^ 【先前技術】 切換式電壓調節器係用以在一 下供寤邮不亦 過调即的輪出電壓 〜“要的輸出電流至負载。切 控制功率電晶體之切換工作比(DutyR =即益错由 節的輸入電壓源轉換成 )而達成將未調 电&你褥換成所期望之穩定的 不習知的採用+、、六门拉^ 电反。圖1顯 W妹用电机回授控制的同步 電路區堍图J 乂切換式降壓調節器之 鬼圖。如圖所示,上側開關Hs盥 聯耦合於鈐Λ帝P、 /、卜側開關LS係串 、砌電堊源Vin與地面電位間。雷威τ 合於上伽pg M 琢L之一端I禺 開關HS與下側開關Ls間 另—端則从达从 j通即點CN,而jl 、J作為輸出端,用以供應輸出電壓v ’、 輪出端亦得設置有一輸出電容c田£v°ut至負载I。 進行濾浊淖 °用以對於輪出電壓v〇ut μ /处理。上側開關H s與下侧開關 u 邏輯電踗側開關LS係分別由切換 耳电路10所輸出的上側驅動作泸Hn b ”吳 ⑺加以押制“丰 動“虎肋與下側驅動信號 子工制。在同步切換式調節界 側開關T q 的 上側開關HS鱼下 :關LS之操作係彼此反相。振盪 ,、下 疋頻率1輸出一具有固 、羊之脈衝信號PU至切換邏輯電 有口 環開妒夕、 路10。在每一切換楯 σ之仞,切換邏輯電路1()回庫 、盾 應於脈衝信號Ρϋ而使上 1259345 側開關HS導通且下側開關LS*導通。1259345 IX. Description of the invention: [Technical field of the invention] The present invention relates to a switching voltage regulator, in particular, to avoid switching between non-continuous reduction + ;~ ^ ) + transport, 杈 type switching voltage regulation The efficiency of power conversion. Pig 鈇 ^ [Prior Art] Switching voltage regulator is used to turn the voltage out of the 寤 过 〜 〜 “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 Du Du Du Du = that is, the error is converted from the input voltage source of the section to the unconformed & 褥 褥 褥 所 所 所 所 + + + + + + + + + + + + + + + + + + + 。 。 。 。 。 。 The synchronous circuit area controlled by the motor feedback control diagram J 乂 switching type buck regulator ghost diagram. As shown in the figure, the upper side switch Hs is coupled to the 钤Λ P P, /, 卜 side switch LS string, Between the electric source Vin and the ground potential, the Leiwei τ is combined with the upper gamma pg M 琢L one end of the I 禺 switch HS and the lower side switch Ls between the other end, then from the j pass to the point CN, and jl, J as The output terminal is used to supply the output voltage v ', and the output terminal is also provided with an output capacitor c field £v°ut to the load I. The filter is used for the output voltage v〇ut μ / processing. The upper switch H s and the lower side switch u logic electric side switch LS are respectively driven by the upper side of the switching ear circuit 10 as 泸Hn b ” ⑺ charge to be made "Feng movable" Tiger rib-side driving signal at the sub-station system. At the upper side switch HS of the synchronous switching type side switch Tq, the operation of the LS is reversed from each other. Oscillation, the lower 疋 frequency 1 output has a solid, sheep pulse signal PU to the switching logic, the mouth is open, and the road 10 is. After each switching σ σ, the switching logic circuit 1 () is switched back to the bank, and the shield is applied to the pulse signal Ρϋ so that the upper 1259345 side switch HS is turned on and the lower side switch LS* is turned on.
Vin供應能量至電感L,電产j因而給 别入包壓源 私概IL因而線性增大。一 、 電流iL增加至由電壓回授信 一電感 vfb,、芬考電壓信梦ν 間之經過電流斜率補償的誤差則虎v…所設定:ref 時,比較器12被觸發而從低位準輸出轉態成高 限 回應於比較器12之觸發,切換邏輯電路!。使上側開:出,Vin supplies energy to the inductor L, which in turn gives the individual source voltage IL a linear increase. 1. The current iL is increased to the voltage vfb, and the error of the current slope compensation between the Fenwick voltage and the signal is set by the tiger v... When the ref is set, the comparator 12 is triggered to switch from the low level output. The state is in a high limit in response to the trigger of the comparator 12, switching the logic circuit!. Make the upper side open: out,
變成不導通且下側開關LS變 'HS 中之能量釋放至負載Rl,、,H 果,儲存於電感匕 一貝戰’造成電感電流1線性減少。 圖2頒不圖1之同舟+ # U步切換式降壓調節器之電感雷、、☆ τ 之波形時序圖。如圖所示,曲線2ι代表在連續模l (C__S Mode)之操作中電感電流II之波形。在每^ 換週期Ts中’電感電流U變化呈現為三角形波,其: 性上升部分係對應於上側開_ HS處於導通狀態而 電壓源Vin供應能量至電《L,❿其線性下降部分則:廡 於上側開II HS處於不導通狀態而使儲存於電感l中之处 量釋放至負載RL。曲線21之平均值。即經由輸出級: 路而供應至負載Rl之電流。 ^ 線22代表在不連續模式(Disc〇ntinu⑽s M〇(je)之择 作中電感電流IL之波形。在時間u,一個切換循環開始, 因此上側開關HS導通使電感電流八線性上升。在時間 t2,當電感電流1L上升至由經過斜率補償的誤差信號Ve〜 所α又疋的峰值1Peak2時,上側開關HS即變成不導通,造成 電感電流iL隨後開始線性減少。在時間t3,電感電流k 7 1259345 已經降低至零,然而下一切換 刀換循%仍須等待至時間 開始。在此情況下,電减雷泣τ μ ] μ才月匕 电α電机IL將在時間t3與t4區間内 發生極性反轉之現象,亦即 丌即電感電流IL之流動方向發 180度之轉變。因此,習 力门毛生 白$的冋步切換式降壓調節器 額外設置一電流反轉偵測電路 Ρσ。必須 7 如圖1所示,使得者雷 感電流IL降低至零時立g人人 田窀 才即〒令切換邏輯電路10使下側開 關LS變成不導通,藉 忧卜側開 笔感電流II發生極性反轉現 象而減損整體的電能供應效率。 專見 即使設置電流反轉偵 」甩峪Ρ或甚至改用非同步 :_us)切換式電壓調節器(亦及使用功率電曰 體與飛輪二極體之組 力革“ 流】,發生極性反轉現象^ 路),可有效防止電感電 … 轉現象。然而’如圖2所示,在不連續模 式中電感電流IL在時問P1 思貝模 況下,輸出電壓V ”避二區間内維持於零。在此情 成高頻雜訊。〜了避免地發生持續性上下震盘而形 【發明内容】 有鑑於前述問題, 式電壓調節器,可,敕目的在於提供-種切 續模式起連續料,目而避免不 刀巧 < 各種缺點。 本發明人觀寒^丨丨太 值電流之—杯箄二—切換循環中,當流經電感之 壓調節IM“二 電感之平均值電流時,切換式 *於連績模式與+連續模式間之臨界操 1259345 :::此時流經電感之峰值電流可稱為連續模式之臨界峰 :(Threshold Peak Current)。目此依據本發明之切 換式%壓調節器設置有—臨界峰值電流設定電路,用 土臨界峰值電流信號,其代表連續模式之臨界峰值電流。 當流經電感之峰值電流大於臨界峰值電流時,由於已: =連續模式中,目此無須調整流經電感之電流。然^ 當流經電感之峰值電流被偵測到小於臨界峰值電流時 了防止電壓調節器操作於不連續模式中, * =電流使得其♦值電流仍實質上等於臨界峰值電流、、,= 確保切換式電壓調節器持續操作於連續模式。 曰 勺人㈣本發明之提供—種切換式電壓調節哭, 二-切換電路、—控制電路、以及_設定電路。切 刼作於第一操作狀態與第二操作狀態。在第一摔作狀能 I:切換電路允許一切換電流線性增加。在第二操作狀: 切換允許該切換電流線性減少。控制電路輕合於 1 、:+,用以控制切換電路操作於第一或第二操作狀 °又疋電路產生-臨界信號,使得控制電路回應於萨界 :號而確保切換電流在第一操作狀態中線性增加至:: 〆等於由臨界信號所設定的一電流 ; 在弟二操作狀態中線性減少至極性反轉。 、 之二=發明之另一態樣’提供-種切換式電壓調節器 ::方法’包含下列步驟。控制-切換電路操作於一第 電二用以允許一切換電流線性增加。控制該切換 *於-第二操作狀態,用以允許該切換電流線性減 1259345 少。在控制該切換電路操作於該第一操作狀態之該步驟 中,確保該切換電流線性增加至大於或等於_臨界電流, 藉以在控制該切換電路操作於該第二操作狀態之該步驟 中防止該電流線性減少至極性反轉。 依據本發明之又一態樣,提供一種臨界電流設定電 路,包含-第-電路、一第二電路、以及一第三電路。第 一電路回應於一電壓信號而產生-第-電流信號。第-電 流信號係正比於該電壓信號。第二電路回應於該第—電流 ϋ與-週期信號而產生一第二電流信號。第二電流信號 係代表一週期性變化的電流。第三電路產生-第三電流信 第一电/爪彳§唬係代表一預定的電流值。藉由該第—至 5亥第三電流信號之-組合模擬近似—臨界電流信號。 【實施方式】 下文中之說明與附圖將使本發明之前述與其他目 的、特徵、與優f纟-_ % 斗 發明之較佳實:例月顯。蹲照圖式詳細說明依據本 平均ΓΓΙ人仔細觀察圖2後發現流經電感之峰值電流與 I有1::間之相對關係在連續模式中與不連續模式中 別。具體而言,在連續模式中,例如曲線21 感L·之峰值杂、六了 {甩抓iave丨大於流經黾 例如曲線22:二厂,的—半。然而,在不連續模式中, 小於流經電:Γ :操作,流經電感L之平均值電流“2 、-電感L之峰值電流的一半,此係因為在每 10 1259345 一切換週期Ts中有-部分的時間内電感電流iL實質上為 零(在設有電流反轉防止裝置之情況下)。因此,倘若為了 避免切換式電壓,周卽器操作於不連續模式,則必須確保流 經電感之峰值雷户& _ & ϊ ^ 、 爪的一 +小於或等於流經電感之平均值 電流。如圖3所示,曲飧上 曲線3Q代表在臨界操作狀態中電感 電流IL之波形,在每一切拖施严 ^ ,It becomes non-conducting and the lower side switch LS changes the energy in the 'HS release to the load Rl,,, H, stored in the inductor 匕 a battle, causing the inductor current 1 to decrease linearly. Figure 2 shows the waveform timing diagram of the inductance lightning and ☆ τ of the same boat + # U step switching type buck regulator. As shown, the curve 2ι represents the waveform of the inductor current II in the operation of the continuous mode 1 (C__S Mode). In the change period Ts, the change of the inductor current U appears as a triangular wave, and its: the rising portion corresponds to the upper side open_HS is in the conducting state and the voltage source Vin supplies the energy to the electric "L, and its linear falling portion is: The upper side of the open II HS is in a non-conducting state, and the amount stored in the inductor l is released to the load RL. The average of the curve 21. That is, the current supplied to the load R1 via the output stage: path. ^ Line 22 represents the waveform of the inductor current IL in the discontinuous mode (Disc〇ntinu(10)s M〇(je). At time u, a switching cycle begins, so the upper switch HS turns on to cause the inductor current to rise linearly. T2, when the inductor current 1L rises to the peak value 1Peak2 of the slope-compensated error signal Ve~α and ,, the upper switch HS becomes non-conducting, causing the inductor current iL to then begin to decrease linearly. At time t3, the inductor current k 7 1259345 has been reduced to zero, however, the next switching knife change cycle % still has to wait until the time begins. In this case, the electric deceleration τ μ μ μ μ μ μ μ μ α α α α α α α α α α α α α α α α The phenomenon of polarity reversal occurs, that is, the direction of the flow of the inductor current IL is 180 degrees. Therefore, the Hurricane Switching Buck regulator of Xi Li Men's Whitening is additionally equipped with a current reversal detection. Circuit Ρ σ. Must be 7 as shown in Figure 1, when the lightning sensation current IL is reduced to zero, then the 窀 人 窀 窀 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换 切换II hair The polarity reversal phenomenon detracts from the overall power supply efficiency. Specially, even if the current reversal detection is set, or even the asynchronous: _us) switching voltage regulator (also uses the power electric body and the flywheel diode) The body of the force "flow", the polarity reversal phenomenon ^ road), can effectively prevent the inductance of the electric ... turn phenomenon. However, as shown in Figure 2, the inductor current IL in the discontinuous mode is time P1 In this case, the output voltage V ′ is maintained at zero in the second interval. In this case, high frequency noise is formed. ~ Avoiding the occurrence of a continuous up and down shock disk. [Inventive content] In view of the foregoing problems, the type of voltage regulator can be, in order to provide a continuous mode of continuous material, avoiding inconsistency < Disadvantages. The inventor observes the cold current, the current value of the cup, and the switching cycle. When the voltage of the inductor is adjusted to the average current of the IM "two inductors, the switching type is between the continuous mode and the + continuous mode. The critical operation 1259345::: The peak current flowing through the inductor at this time can be called the critical peak of the continuous mode: (Threshold Peak Current). The switching type % voltage regulator according to the present invention is provided with a critical peak current setting circuit. The critical peak current signal is used to represent the critical peak current of the continuous mode. When the peak current flowing through the inductor is greater than the critical peak current, since: = continuous mode, there is no need to adjust the current flowing through the inductor. When the peak current of the inductor is detected to be less than the critical peak current, the voltage regulator is prevented from operating in the discontinuous mode, * = the current is such that its ♦ value current is still substantially equal to the critical peak current, , = ensuring the switching voltage regulation The device continues to operate in continuous mode. (4) The present invention provides a switching voltage regulation crying, a two-switching circuit, a control circuit, and a _ setting power The switching operation is performed in the first operating state and the second operating state. In the first falling state, the switching circuit allows a switching current to linearly increase. In the second operation state: switching allows the switching current to linearly decrease. The control circuit is light. Combined with 1:, +, to control the switching circuit to operate in the first or second operation state, and the circuit generates a -critical signal, so that the control circuit responds to the Sa-Bound: number to ensure that the switching current is linear in the first operating state. Increased to: 〆 is equal to a current set by the critical signal; linearly reduced to polarity reversal in the second operating state. 2, another mode of the invention 'provided-type switching voltage regulator:: method 'Includes the following steps. The control-switching circuit operates on a second power to allow a linear increase in switching current. The switching is controlled in the second operating state to allow the switching current to be linearly reduced by 1259345. The switching is controlled. The circuit operates in the step of the first operational state to ensure that the switching current linearly increases to greater than or equal to a _critical current, thereby controlling the switching circuit to operate in the second In this step of the state, the current is prevented from linearly decreasing to polarity inversion. According to still another aspect of the present invention, a threshold current setting circuit is provided, including a -th circuit, a second circuit, and a third circuit. A circuit generates a -first current signal in response to a voltage signal. The first current signal is proportional to the voltage signal. The second circuit generates a second current signal in response to the first current and the -cycle signal. The current signal represents a periodically varying current. The third circuit generates a third current signal. The first current/claw 彳 唬 represents a predetermined current value. By the third to the fifth current signal - Combinational Simulation Approximation - Critical Current Signal [Embodiment] The foregoing description of the invention and other objects, features, and advantages of the invention will be apparent. According to the detailed description of the figure, according to the average person, after carefully observing Fig. 2, it is found that the relative relationship between the peak current flowing through the inductor and I has 1: in the continuous mode and the discontinuous mode. Specifically, in the continuous mode, for example, the curve 21 senses the peak value of the L·, and the sixth is {the iave 丨 is larger than the flow 黾, for example, the curve 22: the second half. However, in the discontinuous mode, less than the flow through: Γ: operation, the average current flowing through the inductor L "2, - half of the peak current of the inductor L, because there is a switching cycle Ts every 10 1259345 - The inductor current iL is substantially zero for a part of the time (in the case of a current reversal prevention device). Therefore, in order to avoid the switching voltage, the peripheral device is operated in the discontinuous mode, and the peak of the inductance must be ensured. Leihu & _ & ϊ ^, one of the claws + is less than or equal to the average current flowing through the inductor. As shown in Figure 3, the curve on the curve 3Q represents the waveform of the inductor current IL in the critical operating state. Everything is sloppy ^,
切換循壤之結束前夕電感電流IL 恰降低至零。茲斗瞀、、亡 π々丨L、、、工黾感之峰值電流的一半等 經電感之平均值電产砗夕γ w Ρ 千『口寺於抓 雷泣T y ,丨π之s品界刼作狀態,可發現臨界峰值 电、丨L Ipeak TH係由工作卜μ η 丄·《上今 以及雷片—τ & 作比D、切換週期Ts、輸入電壓源Vin、 以及電感L所共同、、灰$ , 、门决疋,如下列方程式(1)所示:The inductor current IL is reduced to zero just before the end of the switch.瞀 瞀 , , 亡 々丨 々丨 、 、 、 、 、 、 、 、 、 、 、 经 经 经 经 经 γ γ γ γ γ γ γ 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 『 In the state of the boundary state, the critical peak power can be found, and the IL Ipeak TH system is composed of the work μμ 丄 《 "the present and the laser - τ & ratio D, the switching period Ts, the input voltage source Vin, and the inductance L Common, gray $, and threshold, as shown in the following equation (1):
LL
L peak — TH —D). ··· ( 1 ) 由於臨界峰值電流I A主土 峰值電流,故口旅/ 連續模式之最小可允許# r „ S保流經電感之峰值電流大於戋等於jtt g品界峰值電流I 、义寻於itt 連續模式中。—THP可有效避免電壓調節器操作於不 圖4顯示依據本發 降壓調節器之電路區塊+連續模式之同步切換式 侧開關LS係串聯耦合於輪::不’上側開關HS與下 感L之-端搞合於上側二㈣^與地面電位間。電 節點CN,而i ^T側開關LS間之共通 、至‘:::::::=端广供應輪出電壓 於輪出電壓U進行心有—輪出電容C。,用以對 慮波處理。上側開關HS與下側開關 1259345L peak — TH —D). ··· ( 1 ) Due to the critical peak current IA main earth peak current, the minimum allowable port r/s continuous mode # r „ S keeps the peak current of the inductor larger than 戋 equals jtt g The peak current I of the product is in the continuous mode of the itt.—THP can effectively prevent the voltage regulator from operating. Figure 4 shows the synchronous switching side switch LS system according to the circuit block + continuous mode of the buck regulator. Coupling in series with the wheel:: No 'The upper side switch HS and the lower side L are engaged with the upper side two (four)^ and the ground potential. The electric node CN, and the i ^T side switch LS are common, to '::: ::::=Terminal supply voltage is applied to the wheel-out voltage U for the heart-to-round capacitance C. It is used for the wave treatment. The upper switch HS and the lower switch 1259345
LS係分別由切換邏輯電路40所輪ψ & LThe LS system is rotated by the switching logic circuit 40, respectively;
丨别出的上側驅動信號HD 與下側驅動信號LD加以控制。切換 刀換邏軏電路4〇呈有一 SR閂鎖器(Latch)41,用以從反相輪出 别®立而2供應上側驅動信 万虎HD與下側驅動信號LD。在圖4辦-aa 口所不的實施例中,因為 上側開關HS係由PMOS電晶體所實施 具她且下側開關LS係由 NMOS電晶體所實施,所以上侧駆 1t唬HD與下側驅動 信號LD係由同相位的信號所實施。 S R閂鎖器41之設置端s連接於口 j 〇 而連接於反相器42之輸出端。 反相器42之輸入端連接於振盪雷 盈电路1 1,用以接收脈衝信 號P U。S R閂鎖器41之重置端r遠垃 直响κ遷接於NAND邏輯閘43 之輸出女而。]STAND邏輯閘43之室 认 、科问4 3之弟一輸入端連接於比較器 1 2之輸出端,用以接收第一士 平乂、、、口果仏旒CR1。比較器 12 ^反相輪人料接於斜率補償電路13之輸出端。斜率 補W路134二輸人端分別連接於振盪電@ u與誤差放 ^器14之輸出端’用以基於振盈電路"所輸出的据齒波 U RA铃决羞放大器14戶斤輸出的有關電壓回授信號V* 契茶考電壓信,虎Vr』之誤差信號火⑴而產生經過斜率 、千 1〇5虎Verr2。铁差放大器14之反相輸入端連接 :電壓回授電路15之輸出端,用以接收電壓回授信號 …’其代表電壓調節器之輪出電壓v_。誤差放大器.14 之:反相輪入端用以接收一參考電壓信號%。比較器12 j反相輪人端連接於電流回授電路Μ,用以接收電流回 Μ號vifb,其代表電感電流II。 12 1259345 NAND邏輯閘43之第二輸入端連接於比較器44之輸 出h用以接收第一比較結果信號CR2。比較器44之反 相輪入端連接於臨界峰值電流設定電路45,用以接收臨界 峰值5又疋彳§號Vpeak TH。比較器44之非反相輸入端連接於 電流回授電路16 ’用以接收電流回授信號Vifb。由臨界蜂 值電流設定電路45所產生的臨界峰值設定信號VpeakTH 係代表依據前述方程式(1)所計算而得的臨界峰值電流The upper side drive signal HD and the lower side drive signal LD are controlled. The switching knife switching circuit 4 is provided with a SR latch 41 for supplying the upper driving signal and the lower driving signal LD from the reverse rotation wheel. In the embodiment of FIG. 4, the upper switch HS is implemented by a PMOS transistor and the lower switch LS is implemented by an NMOS transistor, so the upper side 駆1t唬HD and the lower side. The drive signal LD is implemented by signals of the same phase. The set terminal s of the S R latch 41 is connected to the port j 〇 and is connected to the output terminal of the inverter 42. An input of the inverter 42 is coupled to the oscillating thunder circuit 1 1 for receiving the pulse signal P U . The reset terminal r of the S R latch 41 is far away from the output of the NAND logic gate 43. ] STAND logic gate 43 room, the brother of the 4 4 brother, an input is connected to the output of the comparator 1 2, for receiving the first gentleman, , and the mouth 仏旒 CR1. The comparator 12^reverse wheel is connected to the output of the slope compensation circuit 13. The slope complements the W channel 134 and the two input terminals are respectively connected to the output of the oscillating electric current @u and the error amplifier 14 for the output of the magnetic wave based on the vibration circuit " U RA ringing shame amplifier 14 kg output The voltage feedback signal V* 契 tea test voltage letter, the tiger Vr 』 error signal fire (1) produced by the slope, thousand 〇 5 tiger Verr2. The inverting input terminal of the iron difference amplifier 14 is connected: an output terminal of the voltage feedback circuit 15 for receiving a voltage feedback signal ...' which represents the voltage of the voltage regulator v_. Error amplifier .14: The inverting wheel input terminal receives a reference voltage signal %. The comparator 12 j inverting wheel is connected to the current feedback circuit Μ for receiving the current return symmetry vifb, which represents the inductor current II. 12 1259345 The second input of the NAND logic gate 43 is coupled to the output h of the comparator 44 for receiving the first comparison result signal CR2. The inverted phase input terminal of comparator 44 is coupled to critical peak current setting circuit 45 for receiving a critical peak value 5 and a § § Vpeak TH. The non-inverting input of comparator 44 is coupled to current feedback circuit 16' for receiving current feedback signal Vifb. The critical peak setting signal VpeakTH generated by the critical-tone current setting circuit 45 represents a critical peak current calculated according to the above equation (1).
Ipeak —TH。 /將參照圖4詳細說明依據本發明之同步切換式降壓 調節器之操作。振蘆電路11所產生的具有週期ts之脈衝 信號印經由反相器42供應至SR閃鎖器41之設置端s。 由於SR閃鎖器41係負向觸發電路,故脈衝信號Pu之上 升邊緣纽反相後觸發SR閂鎖哭 你甘g ^ 口 使其反相輸出端2供 ::、有低位準的上側驅動信號hd與下側驅動信號❿,開 始進行一切換循環。低 關Η… 準的上側驅動信號Μ使上側開 不導通。結果,輸入電壓源1 Γ下側開關1^ 電产;!因 '、1η供應旎里至電感L,電感 私肌II因而線性增大。電流 並產生用以代表^ 感電流lL, ^ U包爪IL之電流回授信號vifb。 授信號Vlfb供應至比較器12 ",L α 44,用U分別比較於妹 斜率補償的誤差信號v 鱼 、、、、二k 〃/、‘界峰值設定信號v 藉由比較器12之作用, 止 Ρ"^'ΤΗ ° v , —旦線性上升的電流回授俨 说池超出經過斜率補償的Μ信號L第-比較; 13 1259345 WTH,才能使重置端Μ皮觸發,所以在 次觸發設置端s以進入下“虎ρυ再 卞自¥之刖,電咸帝、、六Ipeak —TH. / The operation of the synchronous switching type buck regulator according to the present invention will be described in detail with reference to FIG. The pulse signal having the period ts generated by the vibrating circuit 11 is supplied to the set terminal s of the SR flash locker 41 via the inverter 42. Since the SR flash locker 41 is a negative-direction trigger circuit, the rising edge of the pulse signal Pu is inverted and the SR latch is triggered. You can make the inverted output terminal 2 for::, the upper side drive with a low level The signal hd and the lower side drive signal 开始 start a switching cycle. Low Off... The upper side drive signal causes the upper side to be non-conductive. As a result, the input voltage source 1 Γ the lower side switch 1 ^ electricity; Since the ', 1η supply 旎 to the inductance L, the inductance of the private muscle II thus increases linearly. The current generates a current feedback signal vifb for representing the sense current lL, ^ U. The signal Vlfb is supplied to the comparator 12 ", L α 44, and U is compared with the error signal of the sister slope compensation v fish, , , , 2 k 〃 /, 'Boundary peak setting signal v by the function of the comparator 12 , Ρ Ρ quot ^ ^ ^ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Set the end s to enter the next "Tiger υ υ υ ¥ ¥ ¥ 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖
不會降低至極性反轉。因此,伏祕 电从弘/瓜ILWill not reduce to polarity reversal. Therefore, the volts of electricity from Hong / melon IL
依據本發明之同步切拖弋隆 壓調節器有效地避免操作於兀、έ接 換式IV 卞於不連績模式中,解決 電感電流極性反轉及/或輪出電壓 白央的 訊之問題。 下辰盈而形成高頻雜 在圖4所示的實施例中士 比> 由於比較器12與比較器44 白设计為電壓性質比較電路,亦 〇 备入^而用以接收電壓信 號且輸出端用以輸出電壓作 " 故電流回授電路16與臨 界峰值電流設定電路45皆抓土人 白5又计成輪出電壓性質信號Vifb ” Vpeak—TH,用以間接代表所對應的電流物理量II盘 W—TH,而非直接輸出電流性質信號。請注意本發明亦得 μ用於電w回授電路1 6與臨界峰值電流設定電路C設叶 成直接輸出電流性質信號之情況。舉例而言,額外設置電 =至電壓轉換器於電流回授電路16肖臨界峰值電流設定 胃、之輸出鳊,用以將所輸出的電流性質信號轉換成 电壓性貝化唬。另-種可行的方法則是使用電壓至電流轉 換杰將電壓性質的誤差信號U換成電流性質信號,同 日寸將比較态1 2與比較器44設計成電流性質比較電路。此 種情況下’電流回授電路16與臨界峰值電流設定電路45 亦付没计成直接輸出電流性質信號。 從方私式(1)可知,臨界峰值設定信號Vpeak_TH係隨著 工作比之—次乘冪而變動。除了穩定狀態已經建立以外, 15 1259345 工作比係隨著雷懕嘴々々 穩定狀態,,::=;:即時操作狀態而變動。即使在 必須辩大以难拄仏 肊因輸入電壓源Vin逐漸下降而 伊媸士欢叫 ν_於所期望的目標值。因此, 依據本發明之臨界峰 _ 定信號,而必須美於二疋電路45纟非僅產生-固 *要的…調節器之即時操作狀態而調整所 而要的⑪界峰值設定信號vpeakTH。 之第據本發明之臨界峰值電流設定電路叫 之弟一例子之詳細雷 出電壓vln與具有週期;。如圖所示,回應於未調節的輸 流設定電路451^ 鑛齒波信號RA,臨界峰值電 依據H太 臨界峰值設定信號Vpeak_TH,其代表 依據刖述方程式Π ) ^ '⑴所计异而得的臨界峰值電流IpeakTH。 兴ff而吕,輪入帝颅 ' 甩1 in依序經由運算放大器〇P1與〇P2 、 而形成臨界峰值設定信號 下列方程式(2): 」衣不如The synchronous cutting and dragging pressure regulator according to the present invention effectively avoids the problem of inverting the polarity of the inductor current and/or the signal of the round-out voltage in the non-continuous mode. . The lower case is formed to form a high frequency miscellaneous in the embodiment shown in FIG. 4. The comparator 12 and the comparator 44 are designed to be voltage property comparison circuits, and are also used to receive voltage signals and output. The terminal is used for output voltage as "the current feedback circuit 16 and the critical peak current setting circuit 45 are both grasped by the human body 5 and counted as the wheel-out voltage property signal Vifb" Vpeak-TH, which is used to indirectly represent the corresponding current physical quantity. II disk W-TH, instead of directly outputting the current property signal. Please note that the invention is also used in the case where the electric w feedback circuit 16 and the critical peak current setting circuit C are set to directly output current property signals. In other words, an electric=to-voltage converter is additionally provided in the current feedback circuit 16 to set the threshold current of the stomach to the output of the stomach to convert the output current property signal into a voltage-conducting enthalpy. Another feasible method Then, the voltage-to-current conversion is used to replace the error signal U of the voltage property into a current property signal, and the comparator 21 is designed as a current property comparison circuit in the same day. In this case, the current The feedback circuit 16 and the critical peak current setting circuit 45 are also not directly counted as direct output current property signals. From the square (1), the critical peak setting signal Vpeak_TH varies with the duty ratio. Outside the steady state has been established, the working ratio of 15 1259345 is stable with the Thunderbolt, ::=;: The instantaneous operating state changes. Even if it is necessary to argue, it is difficult to reduce due to the input voltage source Vin. And Ishisuke screams ν_ at the desired target value. Therefore, according to the critical peak _ signal of the present invention, it must be better than the second circuit 45 纟 not only produce - solid * the immediate operation of the regulator The 11-th peak setting signal vpeakTH is adjusted according to the state. The critical peak current setting circuit of the present invention is called the detailed lightning-out voltage vln and has a period; as shown in the figure, in response to the unadjusted The current setting circuit 451^ the mineral tooth wave signal RA, the critical peak power is based on the H too critical peak setting signal Vpeak_TH, which represents the critical peak current calculated according to the equation Π) ^ '(1) IpeakTH. Xing ff and Lu, turn into the emperor ' 甩 1 in sequentially through the operational amplifier 〇 P1 and 〇 P2, and form a critical peak setting signal. The following equation (2): ” clothes are not as good
peak (rv2) U.O …(2) 此處Rel為連技 _入⑼ 電壓Vin與運算放大器0P1之反相 輸入端間之固定帝 相輪入端與輪出為連接於運算放大器0P1之反 放大器〇 :間之線性彳變電阻、Rc2為連接於運算 之固定^端與運算放大器〇P2之反相輪入端間 並且Rv2為連接於運算放大器〇P2 入端與輪出端間之線性可變電阻。 反相輸 線性可變雷卩Peak (rv2) UO ... (2) where Rel is the continuous technique _in (9) voltage Vin and the fixed phase of the inverting input of the op amp 0P1, the fixed phase of the wheel and the wheel is connected to the op amp OP1 anti-amplifier 〇: The linear linear varistor, Rc2 is connected between the fixed terminal of the operation and the inverting terminal of the operational amplifier 〇P2, and Rv2 is a linear variable resistor connected between the input terminal and the output terminal of the operational amplifier 〇P2. Inverting input linear variable thunder
Rvl係設計成一時間函數,可表示成方 16 !259345 程式(3):The Rvl system is designed as a time function that can be expressed as a 16 !259345 program (3):
··· I 此處Rvl,t=〇係線性可轡+ 甩阻Rvl在切換循環開始時之最初 電阻值,且D(t) A 一 女、m 、/、 k期Ts之時間函數,其值從零(〇) 線性遞增至壹(1)。線性 ^ 一 又尾阻Rv2亦设計成另一時間函 數,可表示成方程式(4): RM = K2,=〇^l-D)(t) ⑷ 此處R一係線性可變電阻u在切換循環開始時之最初 電阻值,且(1-D)⑴為具有週期之時間函數,其值從壹 (1)線性遞減至零(〇)。4 - Q 4所不之振盪電路丨丨所產生的鋸 齒波信號RA之振幅係隨著時間線性遞增且具有週期I。 因此’線性可變電p且Rvi可藉由振盪電路(i所產生的鋸齒 波信號RA之調變而實施。另-方面,錯齒波信號 過反相斋INV後可形成一反相波形,其振幅隨著時間線性 遞減且具有週期Ts。因此,線性可變電阻‘可藉由該反 相鋸齒波仏號之調變而實施。 藉由將方程式(3)與(4)代入方程式(2),臨界峰值設定 信號Vpeak TH可表示如下列方程式(5): v peak \t) ,/=0··· I where Rvl,t=〇 linear linear 辔+ 甩 resistance Rvl is the initial resistance value at the beginning of the switching cycle, and D(t) A is a time function of a female, m, /, k-phase Ts, The value increases linearly from zero (〇) to 壹(1). The linear ^ and the tail resistance Rv2 are also designed as another time function, which can be expressed as equation (4): RM = K2, = 〇 ^ lD) (t) (4) where R is a linear variable resistor u in the switching cycle The initial resistance value at the beginning, and (1-D)(1) is a time function with a period whose value linearly decreases from 壹(1) to zero (〇). The amplitude of the sawtooth wave signal RA generated by the oscillation circuit of 4 - Q 4 is linearly increasing with time and has a period I. Therefore, the 'linear variable electric power p and Rvi can be implemented by the modulation of the sawtooth wave signal RA generated by the oscillating circuit (i). On the other hand, the wrong tooth wave signal can form an inverted waveform after over-reversing INV. Its amplitude linearly decreases with time and has a period Ts. Therefore, the linear variable resistance ' can be implemented by the modulation of the inverted sawtooth apostrophe. By substituting equations (3) and (4) into the equation (2) ), the critical peak setting signal Vpeak TH can be expressed as the following equation (5): v peak \t) , /=0
R (5) 比較方程式(1)與(5) ’可發現由各個電阻值所構成的比例 常數項需設計成滿足下列條件(6): 17 ··· (6) 1259345R (5) Comparing equations (1) and (5) ', it can be found that the proportional constant term composed of the respective resistance values is designed to satisfy the following condition (6): 17 ··· (6) 1259345
(Rvu=〇) __—一— _ (p 、 ,^c\ J(Rvu=〇) __—一— _ (p , , ^c\ J
TT
~L 在每:切換循環中,當電流回授信號^達到經過斜 率補仏的σ吳差L旒Verr2時,此時刻所對應的臨界峰值設定 仏號Vpeak —TH亦準確地由臨界峰值電流設定電路45、丨所產 生。因此,比較器44可有效地判斷電流回授信號In是 否超出臨界峰值設定信號'Μ —Μ,以避免電壓調節器操 作於不連續模式。 @ 圖6顯示依據本發明之臨界峰值電流設定電路45_2 之第二例子之詳細電路圖。> 圖所示,輸入電壓v…經由 運算放大器0Pa、NM0S電晶體N1、與電阻^所構成之 線性電流調節器而決定-電《1&,可表示如下列方程式 (7): …⑺ 換^之,電流1a係正比於輸入電壓Vin。PMOS電晶體P1 ^冓成夕重輸出級之電流鏡,其輸出級電晶體p2至 曰刀別i、應電流Ia。電晶體P2供應電流至由pM〇s電 曰曰體P5與P6所構成的一差動對(Differential Pair)。電曰 2差1應電流至由PM〇S電晶體P7與P8所構成的另 v 對電晶體之閘極連接於一下邊界參考電壓 “曰而甩晶體P8之閘極連接於一上邊界參考電壓。 〃 ' 6舁P7之閘極相互連接,並且用於接收振盪電路 18 1259345 π所產生的鋸齒波信號RA。 電晶體P3所供應的電流1&依據下邊界表考 與錯齒波信號^間之差異而決定分配 換言之’由電晶體Μ與!>6所構成的差動對係由下邊灭失 考電壓Vbl與錯齒波信號RA所控制,用以波^ 號RA之變化而從電流I中 ^ ^ ^ 、 1&中、取一週期性變化分量,使豆 流經電晶體P5。電晶體P4所供應 /、 J电々丨〔丄a依據銀击、、由户~L In each: switching cycle, when the current feedback signal ^ reaches the σ 差 差 旒 r r r r r r r r r r r r , , , , , V V V V V V V V V V V V V V V V V V V V V V V The circuit 45, 丨 is generated. Therefore, the comparator 44 can effectively judge whether the current feedback signal In exceeds the critical peak setting signal 'Μ-Μ' to prevent the voltage regulator from operating in the discontinuous mode. @ Figure 6 shows a detailed circuit diagram of a second example of a critical peak current setting circuit 45_2 in accordance with the present invention. > As shown in the figure, the input voltage v... is determined by the linear current regulator composed of the operational amplifier 0Pa, the NM0S transistor N1, and the resistor ^-electricity "1&, which can be expressed as the following equation (7): ... (7) ^, the current 1a is proportional to the input voltage Vin. The PMOS transistor P1 is a current mirror of the output stage of the output stage, and its output stage transistor p2 to the i 别 i, the current Ia. The transistor P2 supplies current to a differential pair composed of pM〇s bodies P5 and P6. The electric 曰 2 difference 1 should be current to the other side of the PM 〇S transistor P7 and P8. The gate of the transistor is connected to the lower boundary reference voltage. The gate of the crystal P8 is connected to an upper boundary reference voltage. The gates of 〃 '6舁P7 are connected to each other and are used to receive the sawtooth wave signal RA generated by the oscillating circuit 18 1259345 π. The current supplied by the transistor P3 is 1& according to the lower boundary table and the wrong tooth signal The difference is determined by the distribution. In other words, the differential pair formed by the transistor ! and !>6 is controlled by the lower edge loss test voltage Vbl and the wrong tooth wave signal RA, and is used to change the wave number RA from the current I. In ^ ^ ^ , 1 & middle, take a periodic variation component, so that the bean flows through the transistor P5. The transistor P4 supplies /, J electricity 々丨 [丄a according to silver strike,
號RA與上邊界參考電壓Vbh間之 Μ皮L 电曰曰體Ρ8。換言之,由電晶體Ρ7與 , 由鋸齒波信號RA盥上、真斤構成的差動對係 、上邊界參考電壓Vbh所控制, 循鋸齒波信號RA之變化而從 用以依 八旦你*、 - & S ^取一週期性變化The number L is between the RA and the upper boundary reference voltage Vbh. In other words, it is controlled by the transistor Ρ7 and the differential pair system formed by the sawtooth wave signal RA盥, the real jin, and the upper boundary reference voltage Vbh, and the sawtooth signal RA is changed from the - & S ^ takes a periodic change
刀里,使其流經電晶體P ^ ^ 後,流經電晶體P5與P8 的週期性變化分量彼此相加, , 、’且精由NMOS電晶體N3 與N4所構成的電流鏡而轉換為電流Ib。 臨界峰值設定信號v 汽婉帝阳D peak-TH係猎由電流Ia、Ib、與Ic 爪、、、工屯阻Rb所造成之 (8): 电&差而貫施,可表示如下列方程式After passing through the transistor P ^ ^, the periodic variation components flowing through the transistors P5 and P8 are added to each other, and are converted into a current mirror composed of NMOS transistors N3 and N4. Current Ib. The critical peak setting signal v is the result of the current Ia, Ib, and Ic claws, and the work resistance Rb (8): electric & poorly, can be expressed as follows equation
V peak _ ΤΗ ~h+Ic)^Rb ⑴中之_〜變化。 1“寻適合用於模擬方程a::齒波信號RA而變化,故電 所引起的臨界峰值設之工作比D與輸入電壓、 ^^^^(0ffset)t;7\Vpeak-TH^^b〇t^Ic# I 用以調整臨界峰值設定信: 19 1259345 之直流位準(DC Level)。在本發明之一實施例中, ::界參考電盧Vb]設定為0.5伏特、上邊界參考電塵〜 75伏知'、且鋸齒波#號RA係隨著時間從0伏特 線性雙化至0.8伏特。在此參數條件下,電流Ia、Ib、虚 L之組合可相當滿意地模擬近似在工作比介於〇66至!區 間内之臨界峰值設定信號Vpeak TH之變化。 請注意依據本發明之電路與方法可廣泛應用於各種 型態的切換式電麼調節器’例如同步與非同步、升虔與降 壓、電壓回授控制與電流回授控制、脈衝寬度調變(—Μ) 與脈衝頻率調變(PFM)等等所有習知的電塵調節器類型, 並無特殊型態之限制。圖7顯示依據本發明之避免不連續 模=同步切換式升壓調節器之電路區塊圖。圖7之升壓 ^ ^圖4之降壓调靖器之差異處在於上側開關HS與 :2之連接形態、切換邏輯電路7〇、以及臨界峰值電: 疋甩路75如圖所不’電感L係連接於輸人電壓源Vin 與共通節點⑶間’上側開關HS則連接於共通節點CN鱼 輸出端間。切換邏輯電路7〇係供應SR閃鎖器之正相輸出 Q作為上側驅動信號HD與下側驅動信號ld。臨界峰值· 流設定電路75則係產生臨界峰值設定信號,用:V peak _ ΤΗ ~h+Ic)^Rb (1) _~ change. 1 "The search is suitable for the simulation equation a:: the tooth signal RA changes, so the critical peak caused by the electricity is set to work ratio D and input voltage, ^^^^(0ffset)t;7\Vpeak-TH^^ B〇t^Ic# I is used to adjust the critical peak setting signal: DC level of 19 1259345. In one embodiment of the invention, the :: boundary reference voltage Vb] is set to 0.5 volts, the upper boundary Reference electric dust ~ 75 volts ', and sawtooth wave # RA series linearly doubled from 0 volts to 0.8 volts over time. Under this parameter condition, the combination of currents Ia, Ib, and imaginary L can simulate the approximation quite satisfactorily. The change in the critical peak setting signal Vpeak TH in the working ratio ranged from 〇66 to !. Note that the circuit and method according to the present invention can be widely applied to various types of switching type electric regulators such as synchronous and asynchronous. , ascending and depressurizing, voltage feedback control and current feedback control, pulse width modulation (-Μ) and pulse frequency modulation (PFM), etc., all types of conventional dust regulators, no special type Limitation. Figure 7 shows the avoidance of discontinuous mode = synchronous switching boost regulator according to the present invention. Road block diagram. Figure 7 boosting ^ ^ Figure 4 of the buck adjuster difference between the upper switch HS and: 2 connection form, switching logic circuit 7〇, and critical peak power: 疋甩路75 The figure L is connected to the input voltage source Vin and the common node (3). The upper switch HS is connected between the common node CN fish output. The switching logic circuit 7 is the positive phase output Q of the SR flash lock. The upper side drive signal HD and the lower side drive signal ld. The critical peak/stream setting circuit 75 generates a critical peak setting signal for:
品界狀態電感電流之峰值‘(η,如下列方程 所示: JThe peak value of the inductor current of the boundary state ‘(η, as shown in the following equation: J
‘ peak TH ...(9) 20 1259345 •車乂方式(9)與可知,方程式命 Vout係對應於方铲守,〗、认 )之輪出包反項 於升壓调r - 〇 之剧出電壓源項Vln。因此,應用 電壓U振盈電路::二:,路75係回應於輸出 界峰值設定H ν 生的鑛國波信號RA而決定臨 的臨Μ—Μ 而言,只要對於圖5所示 ,峰值电流設定電路45]或圖6所 設定電路45-2,蔣浯土成成认 介学值私抓 輸出電MV將原先使用輸入電壓、之處改換成使用 2電,即可輕易獲得可應用於圖7所示的升壓調 即σσ之臨界峰值電流設定電路75。 雖然本發明業已藉由較佳實施例作為例示加以說 應瞭解者為·本發明不限於此被揭露的實施例。相反 地,本發明意欲涵蓋對於熟習此項技藝之人士而言係明顯 =t ^修改與相似配置。因&,中請專利範圍之範圍應根 豕取廣的詮釋,以包容所有此類修改與相似配置。 【圖式簡單說明】 上〜圖1顯示習知的採甩電流回授控制的同步切換式降壓 調節器之電路區塊圖。 序圖 圖2顯示連續模式與不連續模式之電感電流之波形時 圖3顯示臨界操作狀態之電感電流之波形時序周。 圖4顯示依據本發明之避免不連續模式之同步切換式 降壓調節器之電路區塊圖。 圖5顯示依據本發明之臨界峰值電流設定電路之第一 21 1259345 例子之詳細電路圖。 圖6顯示依據本發明之臨界峰值電流設定電路之第二 例子之詳細電路圖。 圖7顯示依據本發明之避免不連續模式之同步切換式 升壓調節器之電路區塊圖。 【主要元件符號說明】 10, 40,70 切換邏輯電路 11 振盪電路 12, 14, 44 比較器 13 斜率補償電路 15 電壓回授電路 16 電流回授電路 17 電流反轉偵測電路 21,22, 30 電感電流波形 41 SR閂鎖器 42,INV .反相器 43 NAND邏輯閘 45, 45-1,45-2, 75 臨界峰值電流設定電路 OP1,OP2, OPa 運算放大器 CN .共捕節點 C〇 輸出電容 L 電感 Rl 負載 22 1259345'peak TH ...(9) 20 1259345 • The rut mode (9) and the equation Vout are corresponding to the square shovel, 〗 〖, recognize the round out of the package and the counter-suppressed r - 〇 drama The voltage source term Vln is output. Therefore, the application voltage U oscillating circuit:: 2:, the road 75 system responds to the output boundary peak setting H ν raw mine wave signal RA and decides the Linyi-Μ, as far as the peak is shown in Figure 5 The current setting circuit 45] or the circuit 45-2 set in Fig. 6 can be easily applied to the figure by changing the original input voltage and using the electric power to the MV. The boosting voltage shown in 7 is the critical peak current setting circuit 75 of σσ. The present invention has been described by way of example only, and the invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover such <RTIgt; obvious</RTI> modifications and similar configurations for those skilled in the art. Due to &, the scope of the patent scope should be broadly interpreted to accommodate all such modifications and similar configurations. [Simple Description of the Drawings] Up to Figure 1 shows a circuit block diagram of a synchronous switching buck regulator with conventional pick-up current feedback control. Sequence diagram Figure 2 shows the waveform of the inductor current in continuous mode and discontinuous mode. Figure 3 shows the waveform timing of the inductor current in the critical operating state. 4 is a circuit block diagram showing a synchronous switching buck regulator that avoids discontinuous mode in accordance with the present invention. Figure 5 shows a detailed circuit diagram of an example of the first 21 1259345 of the critical peak current setting circuit in accordance with the present invention. Figure 6 shows a detailed circuit diagram of a second example of a critical peak current setting circuit in accordance with the present invention. Figure 7 is a circuit block diagram showing a synchronous switching boost regulator that avoids discontinuous mode in accordance with the present invention. [Main component symbol description] 10, 40, 70 switching logic circuit 11 oscillation circuit 12, 14, 44 comparator 13 slope compensation circuit 15 voltage feedback circuit 16 current feedback circuit 17 current inversion detection circuit 21, 22, 30 Inductor Current Waveform 41 SR Latch 42, INV. Inverter 43 NAND Logic Gate 45, 45-1, 45-2, 75 Critical Peak Current Setting Circuit OP1, OP2, OPa Operational Amplifier CN. Common Capture Node C〇 Output Capacitor L inductor Rl load 22 1259345
Rc 1, RC2 固定電阻 Rv 1 ? R v2 線性可變電阻 Ra? Rb 電阻 HD 上側驅動信號 LD 下側驅動信號 HS 上側開關 LS 下側開關 PU 脈衝信號 RA 鋸齒波信號 CR1,CR2 比較結果信 Ts 週期 I a,I b, I C 電流 II 電 感電流 I a v e 1 5 I ave2 平均值電流Rc 1, RC2 fixed resistor Rv 1 ? R v2 linear variable resistor Ra? Rb resistor HD upper side drive signal LD lower side drive signal HS upper side switch LS lower side switch PU pulse signal RA sawtooth wave signal CR1, CR2 comparison result letter Ts period I a, I b, IC current II inductor current I ave 1 5 I ave2 average current
Ipeakl, Ipeak2 峰值電流 Iave_TH 臨界平均值電流 Ipeak_TH 臨界峰值電流 Vin 輸入電壓源 Vout 輸出電壓 vref 參考電壓信號 Vvfb 電壓回授信號 Vifb 電流回授信號 Verrl 誤差信號 V err2 經過斜率補償的誤差信號 23 1259345Ipeakl, Ipeak2 Peak current Iave_TH Critical average current Ipeak_TH Critical peak current Vin Input voltage source Vout Output voltage vref Reference voltage signal Vvfb Voltage feedback signal Vifb Current feedback signal Verrl Error signal V err2 Slope-compensated error signal 23 1259345
Vpeak TH 臨界峰值設定信號 Vbh 上邊界參考電壓Vpeak TH critical peak setting signal Vbh upper boundary reference voltage
Vbi 下邊界參考電壓 N1 ~ N4 NMOS電晶體 P1〜P8 PMOS電晶體 24Vbi lower boundary reference voltage N1 ~ N4 NMOS transistor P1 ~ P8 PMOS transistor 24
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