1258196 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置，特別係有關於一種具 有凸塊之半導體裝置。 【先前技術】 習知半導體封裝的高密度表面接合技術中，包含有覆晶 接合（flip-chip bonding)或内引腳接合（inner lead b〇nding)， 均需要在一半導體裝置上設置凸塊，例如，液晶顯示螢幕 ^ (Liquid Crystal Display，LCD)的驅動晶片（driver IC)即設計 有金凸塊，以接合至一 TCP、COF可撓性電路板或玻璃基板 等外電路基板。 習知凸塊係製作於晶圓上，在切割為個別為晶片（chip) 或晶片尺寸封裝構造（Chip Scale Package)之半導體裳置，在 凸塊製作之前，應先在一晶圓上形成一凸塊下金屬層（Under Bump Metallization layer)，再於該凸塊下金屬層上形成一光 φ 阻型遮罩，並經由微影製程，使對應於晶圓之銲墊的位置顯 露出來，再以電鍍方法形成凸塊，接著去除遮罩與顯露之凸 塊下金屬層，以完成凸塊與凸塊下金屬承座（UBM pad)的製 作。 请參閱第1圖，習知具有凸塊之半導體裝置係主要包含 有一晶片1 0，在該晶片丨〇之一表面i i係形成有至少一銲墊 12及一保護層13(passivati〇nlayer，或可稱為鈍態層），該保 濩層1 3係用以保護該晶片丨〇之該表面丨丨及其線路（圖未繪 出），通常該保護層13之開口並不是全部顯露該銲墊12，該 5 1258196 保護層13係覆蓋至該銲墊12之周邊，以避免不當的銲接與 對内層積體電路之污染以及增加銲塾1 2之固定，但該保護 層13會在該銲墊12周邊形成一環唇狀之突起區13&，而顯 得不平坦。而在一凸塊下金屬承座14上之凸塊15目前係以 電鍍方式形成。因此，同樣地使得後續製作之凸塊下金屬承 座14與凸塊15呈不平坦。由第丨圖可知，該凸塊15之頂 面係具有一周邊突起區15a以及一相對之中央凹陷區15b， 即回字效應，該周邊突起區15a與該中央凹陷區15b之高度 差約為2# m，會造成測試時電性探觸之失敗，進而造成測 試的誤差。此外，就錫鉛凸塊而言，則僅能在回銲之後方能 進行電性測試。 «月參閱第2圖，當具有該凸塊15之晶片u利用一異方 性導電膠20覆晶接合至一外電路板3〇時，該外電路板％ 係可為一可撓性電路板、玻璃基板或是增層電路板，該凸塊 15擠壓該異方性導電膠2〇。藉由該異方性導電膜20内之導 電粒子21電性導接至該電路板3〇之連接墊31。為了確保該 異方性導電膠20之異方性導電特性，其導電粒子2ι之外徑 應控制在以下，在特殊應用上，該導電粒子2ι之特 更應縮小至3”。由於回字效應使得在該中央凹陷區w 與該連接塾31之間之導電粒子2u無法有效順利電性導 接’形成斷路或導接雜訊。 美國專利第6,784,089號Let et al.等人提出—種平頂凸塊 結構及其製造方法，其係先將-凸塊下金屬承座圖案化成 形’會使用到次微影成像技術；再形成—第—光阻型遮 6 1258196 罩’利用一第二次微影成像技術，使得該第一光阻型遮罩具 有第一開口；接著形成一第二光阻型遮罩，利用一第三次微 影成像技術，使得該第二光阻型遮罩具有在上述之第一開口 上且較小尺寸之第二開口；最後可在該第一開口與第二開口 内形成一具有中央平頂之金凸塊。然而該樣的方法需要使用 到多道的微影成像，增加製程步驟與製造成本。 【發明内容]1258196 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a semiconductor device having bumps. [Prior Art] In the high-density surface bonding technology of the conventional semiconductor package, including flip-chip bonding or inner lead bonding, it is necessary to provide bumps on a semiconductor device. For example, a driver IC of a liquid crystal display (LCD) is designed with gold bumps to be bonded to an external circuit substrate such as a TCP, COF flexible circuit board or a glass substrate. Conventional bumps are fabricated on a wafer and are diced into individual semiconductor chips or chip scale packages. Before bump fabrication, a wafer should be formed on the wafer. An under bump metallization layer is formed on the underlying metal layer of the bump to form a light φ resistive mask, and the position of the pad corresponding to the wafer is exposed through the lithography process, and then The bumps are formed by electroplating, and then the mask and the exposed under bump metal layer are removed to complete the fabrication of the bump and under bump metal pads (UBM pads). Referring to FIG. 1 , a semiconductor device having bumps mainly includes a wafer 10 on which a surface ii is formed with at least one pad 12 and a protective layer 13 (passivati〇nlayer, or The protective layer 13 is used to protect the surface of the wafer and its wiring (not shown). Generally, the opening of the protective layer 13 does not completely expose the solder. Pad 12, the 5 1258196 protective layer 13 is covered to the periphery of the pad 12 to avoid improper soldering and contamination of the inner layer integrated circuit and to increase the soldering of the solder 12, but the protective layer 13 will be soldered The periphery of the pad 12 forms a ring-shaped projection 13 & and appears uneven. The bump 15 on the metal socket 14 under a bump is currently formed by electroplating. Therefore, the subsequent under bump metal holder 14 and the bump 15 are also made uneven. As can be seen from the figure, the top surface of the bump 15 has a peripheral protrusion portion 15a and an opposite central recess portion 15b, that is, a word return effect, and the height difference between the peripheral protrusion portion 15a and the central recess portion 15b is about 2# m, will cause the failure of the electrical probe during the test, which will cause the error of the test. In addition, in the case of tin-lead bumps, electrical testing can only be performed after reflow. «When referring to FIG. 2, when the wafer u having the bumps 15 is flip-chip bonded to an external circuit board 3 by an anisotropic conductive paste 20, the external circuit board % can be a flexible circuit board. The glass substrate or the build-up circuit board, the bump 15 presses the anisotropic conductive paste 2〇. The conductive particles 21 in the anisotropic conductive film 20 are electrically connected to the connection pads 31 of the circuit board 3. In order to ensure the anisotropic conductive property of the anisotropic conductive paste 20, the outer diameter of the conductive particles 2ι should be controlled below, and in special applications, the conductive particles 2 should be reduced to 3". The conductive particles 2u between the central recessed area w and the connecting port 31 are unable to effectively and smoothly conduct electrical contacts to form an open circuit or conduct noise. U.S. Patent No. 6,784,089, et al. The bump structure and the manufacturing method thereof, the patterning of the metal socket under the bump first will be used to the sub-lithography imaging technology; the second-first photo-resistance type cover is used. The lithography imaging technology, the first photoresist type mask has a first opening; and then a second photoresist type mask is formed, and the second photoresist type mask is used to make the second photoresist type mask have a second opening on the first opening and a smaller size; finally, a gold bump having a central flat top may be formed in the first opening and the second opening. However, the method requires multiple channels. Lithography imaging, adding process steps and Manufacturing cost. [Summary content]
本發明之主要目的係在於提供一種測試時具有中 央平頂凸塊之半導體裝置，利用一保護層具有一鄰近 其開口之塾兩部（lifting p〇rti〇n)，該塾高部係對準於 一基板之銲墊之一中央位置，以利一凸塊下金屬承座 之覆蓋以及一具有中央平頂之凸塊之形成，具有低成 本製作中央平頂之凸塊之功效，有利於測試時之電性 探測。此外，當該半導體裝置運用在覆晶接合（flip-chip bonding)、内引腳接合（inner卜以b〇nding)或異方性導 電膠接合時，以該些平頂凸塊提供最佳之平頂區域以 利接合。 本發明之次一目的係在於提供一種測試時具有中 央平頂凸塊之半導體裝置，在一基板上之一保護層係 具有一個或複數個對稱或非對稱排列之開口，並且該 些開口之尺寸總合係小於該銲墊，並且該保護層之一 墊雨部係位於該些開口之間且對準於該基板之銲墊之 一中央位置，以利一凸塊下金屬層在該銲墊之中央位 置墊高覆蓋。 7 ' 1258196 η 本發明之再一目的係在於提供一種測試時具有中 央平頂ώ塊之半導體裝置，利用該保護層在其相鄰開 口之間形成有複數個繫條，以連接該墊高部，增加該 墊高部在該鋅墊上之固定。 依據本發明，一種測試時具有中央平頂凸塊之半導 體裝置主要包含一基板、一保護層、一凸塊下金屬承 座以及一凸塊，該基板係具有在其一表面之一銲墊， 例如晶圓、晶片或晶片尺寸封裝件（chip scale Package ’ CSP)，該保護層係形成於該基板之該表面， 該保護層係具有一至少一開口以及一墊高部（Ufting portion)，其中該開口係部分顯露該銲墊，該墊高部係 對準於該銲墊之中央位置，該凸塊下金屬承座係設置 於虡銲墊上並覆蓋該保護層之墊高部以及該銲墊顯露 在該開口之部位，該凸塊係設置於該凸塊下金屬承座 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 請參閱第3圖，一種測試時具有中央平頂凸塊之半導體 裝置100主要包含一基板11〇、一保護層12〇、一凸塊下金 屬承座131(UBMpad)以及一凸塊14〇,該基板11〇係可為晶 圓、晶片或晶片尺寸封裝件（Chip Scale Package，csp)。例 如，該基板lio係為面板驅動晶片（driver Ic)，其材質係為 矽或其它半導體材料。該基板11〇係具有在其一表面丨11之 一銲墊112。在本實施例中，該表面丨丨丨係為一晶片之主動 8 1258196 w 面。該料112係可為㈣錢墊。在圖示中，雖然僅緣示 銲墊112，實際上，該銲墊J! 2係為複數個密集排列，其 間距可達到100 # m，甚至50 # m。 該保濩層120(passivationiayer，或可稱為鈍態層）係形成 於忒基板11〇之該表面U1，通常該保護層12〇之材質係為 聚亞酿胺⑽、苯環丁稀（BCB)、磷石夕玻璃（psG)氟石夕玻璃 (FSG)、氮化矽（SIN)等等。該保護層12〇係具有一至少一開 口 12i以及一墊高部122(Hftingp〇rti〇n)，均位於該銲墊ιΐ2 之上方，其中該開口 121係部分顯露該銲墊112，該墊高部 122係對準於該銲墊112之中央位置。除了 _體連接該保護 層120之塾高部122之外，在不同實施例中亦可藉由額外 附加例如聚醯亞胺（PI)等具有介電性材質之墊高件（圖未繪 出）取代該墊高部122,該墊高件係可形成於該凸塊14〇與該 銲墊112之間，其製造成本會稍高一些ι，但無論是該塾高部 122或是墊高件，其目的均在使該凸塊14〇可由電鍍形成並 具有一中央平坦之頂面。此外，該墊高部122係應高於該保 護層120在該基板表面ιη上之其它部位。通常該墊高部a] 係幾乎與該保護層120在該銲墊112周邊之突起部123為等 高。較佳地，該保護層12〇係具有一個或複數個對稱或非對 稱排列之開口 121，並且該些開口 121之尺寸總合係小於該 銲墊112,以增加該墊高部122之中央覆蓋面積。該保護層 120之該墊高部122應不小於該銲墊112之顯露於該開口 121 面積之二分之一為較佳。如第4圖所示，在一具體實施例中， 該保護層1 20係具有兩對稱排列之條狀或L形之開口 ^幻， 9 * Ϊ258196 而該墊高部1 22係位於該些開口 1 2 1之間。如第5圖所示， 在另一具體實施例中，該保護層1 20係具有四個對稱排列之 條狀開口 121A，以定義該墊高部122,並且該保護層12〇 係形成有複數個在該些開口 121A之間之繫條i24(tie bar)， 以連接該墊高部1 22，以增加該墊高部1 22在該銲墊11 2上 之定位性。 該凸塊下金屬承座131係設置於該銲墊112上並覆蓋該 保護層120之墊高部122以及該銲墊112顯露在該開口 121 之部位。而該凸塊140係設置於該凸塊下金屬承座131上， 該凸塊140係選自於金凸塊、鋁凸塊、銅凸塊與錫鉛凸塊之 其中之一，可電鍍形成之，又以呈柱狀為較佳，以增加異方 性導電效果。通常該凸塊下金屬承座丨3 i係為複合式金屬 層，例如鈦-鎢（Ti-W)層並可在表面形成一薄金，其目的在於 增加該凸塊140之結合力與防止該凸塊14〇之金屬污染，減 少對該基板11 0内部線路之損傷。 φ 因此，在上述之半導體裝置100中，藉由該保護層120 具有一鄰近其開口 121之墊高部122，且該墊高部122係對 準於該基板110之銲墊112之一中央位置，以供該凸塊下金 屬承座130之覆蓋。請再參閱第3圖，所形成之凸塊14〇係 具有一中央平坦之頂面，在其頂面之中央墊高區141可以修 正其週邊突起區142之不利效應，有利於測試時之電性探觸 並增加該凸塊140之異方性導電面積。此外，本發明之半導 體裝置1 〇〇係具有在不增加凸塊製程與元件成本之優點下可 得到中央平坦之&塊140，其說明如后。 10 •1258196 首先，凊參閱第6 A圖，複數個例如晶片之基板丨丨〇係被 提供於一晶圓中，在該基板11〇之表面lu上係先形成有該 銲墊112以及被該保護層12〇所覆蓋。在該銲墊112之周邊 與中央係分別形成有該保護層丨2 〇之開口丨2丨與墊高部 122 ;之後，利用氣相沉積或濺鍍方式在該基板丨1〇上保護 層120被覆一凸塊下金屬層13〇,其材質係與上述之凸塊下 金屬承座13 1為相同，但尚未被圖案化成墊塊。該凸塊下金 屬層130係同時覆蓋該墊高部122與該銲墊112被該開口 β 1 2 1顯露之部位。 接著，請參閱第6Β圖，可以貼附、印刷方式將一光阻型 遮罩200形成於該凸塊下金屬層13〇上，通常該光阻型遮罩 2〇〇係為乾膜（dry fllm)或是一厚光阻劑 ph〇t〇resist)。在一次的微影成像之後，該遮罩2〇〇會形成一 開孔210，以顯露該凸塊下金屬層13〇對應於該銲墊^之 部位。利用一金屬電鍍製程，可在該開孔内形成上述具有中 • 央平頂之凸塊I40,再移除該遮罩200之後執行一蝕刻步騾 (圖未繪出），蝕刻該凸塊下金屬層丨3〇之外露部位在該凸 塊140下之凸塊下金屬層13〇將形成為上述之凸塊下金屬承 座13 1，最後，經晶圓切割之後，可得到如第3圖所示之半 導體裝置100’在凸塊製程中不需要使用到多道微影成像步 驟以及額外之元件與耗材，具有中央平頂凸塊之低製造成本 且不需要變更習知凸塊製程之功效。 本發明之保護範圍當視後附之申請專利範圍所界定者為 準，任何熟知此項技藝者，在不脫離本發明之精神和範圍内 1258196 所作之任何響作知 化與修改，均屬於本發明之保護範圍。 【圖式簡單說明】 第1圖·習知具有凸塊之半導體裳置之截面示意圖。 第2圖：習知且士 n人 八有凸塊之半導體裝置在異方性導電連接狀態 之截面示意圖。 第1 2 3 4圖·依據本發明，一種測試時具有中央平頂凸塊之半導 體裝置之截面示意圖。SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor device having a central flat-tipped bump during testing, with a protective layer having a lifting portion adjacent to its opening, the high portion being aligned In the central position of one of the pads of the substrate, the cover of the metal socket under the bump and the formation of the bump having the central flat top have the effect of making the bump of the central flat top at a low cost, which is beneficial for testing Electrical detection of time. In addition, when the semiconductor device is used in flip-chip bonding, inner pin bonding, or anisotropic conductive bonding, the flat top bumps are optimally provided. The flat top area is used for joints. A second object of the present invention is to provide a semiconductor device having a central flat-top bump when tested, wherein a protective layer on one substrate has one or a plurality of openings symmetrically or asymmetrically arranged, and the dimensions of the openings The total length is smaller than the soldering pad, and one of the protective layer is located between the openings and aligned with a central position of the pad of the substrate to facilitate a bump under the metal layer on the pad The central position is covered with a high height. 7 ' 1258196 η A further object of the present invention is to provide a semiconductor device having a central flat-top block during testing, by which a plurality of tie bars are formed between adjacent openings thereof to connect the pad portion And increasing the fixing of the pad portion on the zinc pad. According to the present invention, a semiconductor device having a central flat-top bump during testing mainly includes a substrate, a protective layer, a sub-bump metal holder, and a bump having a pad on one surface thereof. For example, a wafer, a wafer or a chip scale package (CSP), the protective layer is formed on the surface of the substrate, the protective layer having at least one opening and an Ufting portion, wherein The opening portion partially exposes the solder pad, the pad portion is aligned with a central position of the pad, the under bump metal socket is disposed on the solder pad and covers the pad portion of the protective layer and the pad The bump is exposed to the portion of the opening, and the bump is disposed on the under-metal socket. [Embodiment] Referring to the drawings, the present invention will be described by way of the following examples. Referring to FIG. 3, a semiconductor device 100 having a central flat-top bump during testing includes a substrate 11A, a protective layer 12A, a bump-free metal holder 131 (UBMpad), and a bump 14〇. The substrate 11 can be a wafer, wafer or chip scale package (csp). For example, the substrate lio is a driver IC, which is made of germanium or other semiconductor material. The substrate 11 has a pad 112 on one surface 11 of the substrate. In this embodiment, the surface tether is the active 8 1258196 w face of a wafer. The material 112 can be a (four) money pad. In the illustration, although only the pad 112 is shown, in fact, the pad J! 2 is a plurality of dense arrays, and the pitch can reach 100 #m or even 50#m. The passivation layer 120 (which may be referred to as a passivation layer) is formed on the surface U1 of the ruthenium substrate 11 ,. Generally, the material of the protective layer 12 聚 is poly styrene (10), benzocyclobutene (BCB). ), Phosphorus Glass (psG) Fluorite Glass (FSG), Tantalum Nitride (SIN), and the like. The protective layer 12 has an at least one opening 12i and a padding portion 122, both of which are located above the pad ι 2, wherein the opening 121 partially exposes the pad 112. The portion 122 is aligned with the center of the pad 112. In addition to the 体 body connecting the top portion 122 of the protective layer 120, in some embodiments, a spacer having a dielectric material such as polyimine (PI) may be additionally added (not shown) In place of the pad portion 122, the pad member may be formed between the bump 14〇 and the pad 112, and the manufacturing cost thereof may be slightly higher, but the height portion 122 or the pad is high. The purpose of the piece is that the bump 14 can be formed by electroplating and has a central flat top surface. Further, the elevated portion 122 should be higher than the other portion of the protective layer 120 on the substrate surface i. Usually, the pad portion a] is almost equal to the protrusion 123 of the protective layer 120 around the pad 112. Preferably, the protective layer 12 has one or a plurality of openings 121 symmetrically or asymmetrically arranged, and the openings 121 are smaller than the pads 112 to increase the central coverage of the pad portion 122. area. Preferably, the pad portion 122 of the protective layer 120 is not less than one-half of the area of the pad 112 exposed to the opening 121. As shown in FIG. 4, in a specific embodiment, the protective layer 120 has two symmetrically arranged strips or L-shaped openings, 9*Ϊ258196, and the elevated portions 1 22 are located at the openings. Between 1 2 1 . As shown in FIG. 5, in another embodiment, the protective layer 120 has four symmetrically arranged strip openings 121A to define the elevated portion 122, and the protective layer 12 is formed with a plurality of A tie bar i24 between the openings 121A is connected to the pad portion 1 22 to increase the positioning of the pad portion 1 22 on the pad 11 2 . The under bump metal holder 131 is disposed on the pad 112 and covers the pad portion 122 of the protection layer 120 and the portion of the pad 112 exposed by the opening 121. The bump 140 is disposed on the under bump metal holder 131. The bump 140 is selected from one of a gold bump, an aluminum bump, a copper bump, and a tin-lead bump. It is preferably in the form of a column to increase the anisotropic conductivity. Generally, the under bump metal socket 丨3 i is a composite metal layer, such as a titanium-tungsten (Ti-W) layer, and can form a thin gold on the surface, the purpose of which is to increase the bonding force of the bump 140 and prevent it. The bump 14 is contaminated with metal to reduce damage to the internal wiring of the substrate 110. φ Therefore, in the semiconductor device 100 described above, the protective layer 120 has a pad portion 122 adjacent to the opening 121 thereof, and the pad portion 122 is aligned with a central portion of the pad 112 of the substrate 110. For covering the under bump metal holder 130. Referring to FIG. 3 again, the formed bump 14 has a central flat top surface, and the central padding region 141 on the top surface thereof can correct the adverse effect of the peripheral protrusion region 142, which is beneficial to the test. Sexually probes and increases the anisotropic conductive area of the bump 140. In addition, the semiconductor device 1 of the present invention has a central flat & block 140 without the advantages of increased bump processing and component cost, as explained below. 10 • 1258196 First, referring to FIG. 6A, a plurality of substrate rafts such as wafers are provided in a wafer, and the pads 112 are formed on the surface of the substrate 11 lu The protective layer 12 is covered. An opening 丨 2 丨 and a pad portion 122 of the protective layer 丨 2 形成 are respectively formed around the pad 112 and the center; and then the protective layer 120 is deposited on the substrate by vapor deposition or sputtering. The under bump metal layer 13 is covered, and the material is the same as the bump under metal socket 13 1 described above, but has not been patterned into a spacer. The under bump metallization layer 130 simultaneously covers the elevated portion 122 and the portion of the pad 112 that is exposed by the opening β 1 2 1 . Next, referring to FIG. 6 , a photoresist type mask 200 can be attached and printed on the under-metal layer 13 凸 of the bump. Generally, the photoresist type mask 2 is a dry film (dry). Flum) or a thick photoresist ph〇t〇resist). After one lithography, the mask 2 defines an opening 210 to reveal the underlying metal layer 13 of the bump corresponding to the pad. Using a metal plating process, the above-mentioned bump I40 having a central flat top can be formed in the opening, and after removing the mask 200, an etching step (not shown) is performed, and the bump is etched. The under bump metal layer 13 〇 under the bump 140 is formed as the under bump metal holder 13 1 , and finally, after being cut by the wafer, the image is obtained as shown in FIG. 3 . The illustrated semiconductor device 100' does not require the use of multiple lithography imaging steps and additional components and consumables in the bump process, has a low manufacturing cost of a central flat-top bump and does not require modification of the conventional bump process. . The scope of the present invention is defined by the scope of the appended claims. Any knowledge and modification of the present invention, which is known to those skilled in the art, without departing from the spirit and scope of the present invention, is intended to be The scope of protection of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor wafer having bumps. Fig. 2 is a schematic cross-sectional view showing the state in which the semiconductor device having eight bumps is electrically connected in an anisotropic manner. BRIEF DESCRIPTION OF THE DRAWINGS According to the present invention, a schematic cross-sectional view of a semiconductor device having a central flat-tipped bump during testing is shown.
第4圖：依據本發明，該半導體裝置在一具體實施例中之保 護層開口示意圖。 第5圖：依據本發明，該半導體裝置在另一具體實施例中之 保護層開口示意圖。 第6A圖：依據本發明，該半導體裝置在基板提供步驟中之 截面示意圖。 第6B圖：依據本發明，該半導體裝置在凸塊形成步驟中之 截面示意圖。 主要元件符號說明】 11表面 1 3 a突起部 15a周邊突起區 2 1導電粒子 31連接墊 111表面 12銲墊 1 4凸塊下金屬承座 15b中央凹陷區 2 1 a導電粒子 112銲墊 12 1A 開口 121 開口 12 1 〇晶片 2 13保護層 3 15凸塊 4 2〇異方性導電膠 外電路板 5 100半導體裝置 Π0基板 120保護層 1258196 122墊高部 123突起部 124繫條 130凸塊下金屬層131凸塊下金屬承座 140凸塊 141中央塾高區 142週邊突起區 200遮罩 210開孔Figure 4 is a schematic view showing the opening of the protective layer of the semiconductor device in a specific embodiment in accordance with the present invention. Fig. 5 is a schematic view showing the opening of a protective layer of the semiconductor device in another embodiment in accordance with the present invention. Fig. 6A is a schematic cross-sectional view showing the semiconductor device in the substrate supply step in accordance with the present invention. Fig. 6B is a schematic cross-sectional view showing the semiconductor device in the bump forming step in accordance with the present invention. Main component symbol description] 11 surface 1 3 a protrusion 15a peripheral protrusion area 2 1 conductive particle 31 connection pad 111 surface 12 pad 1 4 bump lower metal socket 15b central recessed area 2 1 a conductive particle 112 pad 12 1A Opening 121 opening 12 1 〇 wafer 2 13 protective layer 3 15 bump 4 2 〇 anisotropic conductive plastic outer circuit board 5 100 semiconductor device Π 0 substrate 120 protective layer 1258196 122 high portion 123 protrusion 124 strip 130 under the bump Metal layer 131 under bump metal socket 140 bump 141 central 塾 high region 142 peripheral protrusion region 200 mask 210 opening
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