[go: up one dir, main page]

TWI256121B - Package substrate, method for fabricating the same, and chip package process - Google Patents

Package substrate, method for fabricating the same, and chip package process

Info

Publication number
TWI256121B
TWI256121B TW094110960A TW94110960A TWI256121B TW I256121 B TWI256121 B TW I256121B TW 094110960 A TW094110960 A TW 094110960A TW 94110960 A TW94110960 A TW 94110960A TW I256121 B TWI256121 B TW I256121B
Authority
TW
Taiwan
Prior art keywords
layer
package substrate
fabricating
same
package
Prior art date
Application number
TW094110960A
Other languages
Chinese (zh)
Other versions
TW200636961A (en
Inventor
Jung-Kun Kang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094110960A priority Critical patent/TWI256121B/en
Application granted granted Critical
Publication of TWI256121B publication Critical patent/TWI256121B/en
Publication of TW200636961A publication Critical patent/TW200636961A/en

Links

Classifications

    • H10W72/884—
    • H10W90/734—
    • H10W90/754—

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

A package substrate, a method for fabricating the same, and a chip package process applying the package substrate are provided. The package substrate comprises a stack layer, a first circuit layer, a first solder mask layer, a patterned photo-resist layer, and a solder block. The stack layer has a first surface and a second surface corresponding thereto. The first circuit layer is disposed on the first surface of the stack layer, and the first circuit layer has at least one bonding pad. The first solder mask layer is disposed on the first surface of the stack layer, and the patterned photo-resist layer is disposed on the first solder mask layer, wherein the patterned photo-resist layer and the first solder mask layer have at least one first opening for exposing the first bonding pad. The solder block is disposed on the first bonding pad in the first opening. The package substrate, the method for fabricating the same, and the chip package process can improve the processing yields and the reliability of package structure.
TW094110960A 2005-04-07 2005-04-07 Package substrate, method for fabricating the same, and chip package process TWI256121B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094110960A TWI256121B (en) 2005-04-07 2005-04-07 Package substrate, method for fabricating the same, and chip package process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094110960A TWI256121B (en) 2005-04-07 2005-04-07 Package substrate, method for fabricating the same, and chip package process

Publications (2)

Publication Number Publication Date
TWI256121B true TWI256121B (en) 2006-06-01
TW200636961A TW200636961A (en) 2006-10-16

Family

ID=37614086

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094110960A TWI256121B (en) 2005-04-07 2005-04-07 Package substrate, method for fabricating the same, and chip package process

Country Status (1)

Country Link
TW (1) TWI256121B (en)

Also Published As

Publication number Publication date
TW200636961A (en) 2006-10-16

Similar Documents

Publication Publication Date Title
TWI268564B (en) Semiconductor device and fabrication method thereof
TW200733275A (en) Semiconductor device and method of manufacturing the same
TW200737383A (en) Substrate with built-in chip and method for manufacturing substrate with built-in chip
TW200518354A (en) Device package and methods for the fabrication and testing thereof
WO2008099327A3 (en) Embedded inductor and method of producing thereof
WO2006115649A3 (en) Multi-chip module and method of manufacture
TW200739854A (en) Substrate structure having solder mask layer and process for making the same
TW200614395A (en) Bumping process and structure thereof
US8987060B2 (en) Method for making circuit board
TW200729371A (en) Semiconductor device and manufacturing method of the same, camera module
TW519727B (en) Semiconductor wafer, semiconductor device and manufacturing method therefor
TW200725859A (en) Structure and method for packaging a chip
CN104465575A (en) Semiconductor package and manufacturing method thereof
TW200729429A (en) Semiconductor package structure and fabrication method thereof
WO2006008701A3 (en) Assembly and method of placing the assembly on an external board
TWI256121B (en) Package substrate, method for fabricating the same, and chip package process
TW200603353A (en) Chip structure with redistribution circuit, chip package and manufacturing process thereof
WO2006087686A3 (en) Method and arrangement for contact-connecting semiconductor chips on a metallic substrate
WO2006063044A3 (en) Method and device for wafer scale packaging of optical devices using a scribe and break process
TW200707605A (en) Substrate for manufacturing semiconductor device, semiconductor device manufacturing method
TW200802637A (en) Semiconductor package substrate, semiconductor package structure and the method for forming thereof
TW200621106A (en) Method of packaging flip chip and method of forming pre-solders on substrate thereof
TWI257136B (en) Method for manufacturing a bump of wafer level package
TW200741921A (en) Chip package and method for fabricating the same
TW200633096A (en) Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees