!9twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的製作方法，且特 別是有關於一種閘極、薄膜電晶體以及畫素結構的製作方 法。 【先前技術】 薄膜電晶體液晶顯示器主要由薄膜電晶體陣歹^丨爲 板、彩色濾光陣列基板和液晶層所構成，其中薄膜電曰土 陣列基板包括多個以陣列排列之薄膜電晶體，以及與^體 薄膜電晶體對應配置之畫素電極（pixelelectr〇de) 了薄— 電晶體之操作原理與傳統的半導體M〇S元件相類似/，膜 是具有三個端子（閘極、汲極以及源極）的元件，而都 曰曰體之功能制以作為液晶顯示畫素單元關關元件。、電 叙而a，薄膜電晶體陣列基板之製程通常夕 ii!L(ph0t0lit^^(etchin^ ^ ΐ 作並r將光罩上的圖案轉移至先前形成； 利用此===的步驟圖案化光阻層，之後再 敍刻，以料觸===雌f進行 電性2之大尺寸發展，通常使用導 一來，卻發生閘極容易極，以降低配線阻抗，但如此 原有之金屬層上冉匕之問題。因此，現有技術係於 成—抗氧化層，例如一金屬合金 ：9twf.doc/006 (metal alloy)層或一金屬氮化物μ廿此）層，以 避免下層之金屬層因過度氧化而影響面板之電性表現。然 而，由於金屬層與抗氧化層之濕式蝕刻速度具有差異性， 因此應用f知製程形成_時，往往會發生金屬層裏切 (under cut)的現象。 請參考圖1A〜1D，其依序緣示習知之一種具有抗氧 化層之閘極的製作流程示意圖。 ^首先，如圖1A所示，提供一基底1〇〇，其中基底1〇〇 亡係形成有一金屬層l〇2a與一抗氧化層1〇2b，並且於抗 氧化層102b上形成圖案化之一光阻層11〇。 、接著，如圖1B所示，藉由化學侧液進行濕式姓刻， 以將金屬層隐與抗氧化層_之未被光阻層ιι〇覆蓋 的部分移除。其中，由於金屬層職與抗氧化層襲之 間因材質不_而具㈣刻速率的差異性，因此在侧 後’金屬層102a將因為過度爛，而發生裏切112的 象。 然後’如圖1C所示，移除光阻層11〇，而金屬層i〇2a /、抗氧化層102b之剩餘部分係構成一閘極1〇2。 接著，如圖1D所示，於抗氧化層職上沉積一絕 、、彖層104’其中由於閘極102侧壁無法具有良好之階梯狀， 因而使得絕緣層104無法具有良好的覆蓋性，而後續沉積 之膜層亦可能受到影響。此外，在覆蓋絕緣層1〇4後，亦 可能因為金屬層102a之過度钮刻，而在抗 凸出部位產生尖端放電的問題。 U2b之 :9twf.doc/006 【發明内容】 有鑑於此，本發明的目的就是在提供一種閘極、薄 膜電晶體以及晝素結構的製作方法，其係以舉離法（lift_ off)形成閘極，以改善習知之階梯覆蓋性不佳與尖端放 電等問題。 基於上述目的，本發明提出一種閘極的製作方法。 首先，於一基底上形成一圖案化之罩幕層，其中罩幕層係 暴露出一預定形成閘極之區域。接著，於罩幕層所暴露之 區域中形成一閘極。然後，移除罩幕層。 此外，基於上述之閘極的製作方法，本發明提出一 種薄膜，晶體的製作方法。在完成上述之閘極的製作之 後，接著於基板上形成一絕緣層，覆蓋住閘極。然後，於 閘極上方之絕緣層上形成一通道層。之後，於通道層上形 成一源極與'-沒極。 另外，上述之薄膜電晶體的製作方法例如可結合於 二I ΪΪ晶體陣列基板的製程之中，而進行畫素結構的製 _源極與没極之後，可於基板上形成1 铁;/、，韻具有―開口，用以暴露出部分之及極。 而盥ΪΓ濩層上形成—晝素電極，並使晝素電極藉由開 口而與>及極電性連接。 1 槿的述J本發明之閘極、薄膜電晶體以及晝素結 成閘極的方形成問極。與習知利用蝕刻; ，層與抗氧刻因 12535¾ twf.doc/006 4本發明之閘極、薄膜電晶體以及晝素結構的製作方法 極側壁維持良好之階梯狀’而使得後續沉積之膜層 /、有良好的覆蓋性，並可避免閘極之尖端放電的問題。 為讓本發明之上述和其他目的、特徵和優點能更明 ^隱，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 明參考圖2A〜2D，其依序繪示本發明之較佳實施例 之^專膜電曰曰體之閘極的製作流程示意圖。 首先，如圖2A所示，提供一基底2〇〇，並且於基底 2上形成-罩幕材f層22()。在—較佳實施例中，罩幕 才貝層220之材質例如是光阻材料。 ，後，如圖2B所示，圖案化罩幕材質層22〇，以於 ，材質層220中形成一開口 222,而形成圖案化之罩幕 P^2〇a/且開口 222係暴露出基底上之一預定形成 域島°在—較佳實施例中，若罩幕材質層220 ，光阻材才斗，則圖案化罩幕材質層22〇之方法 光罩對罩幕材f層22()進行曝光及顯影製程。在一 實施例中，於罩幕材質層22()中所形成之開口 如疋開口内縮之型態。 例 ，著’如圖2C所示，於基底上預 ^域脈中形成-閘極搬。形成閘極撤之方^之 ==製程、蒸鍍製程等物理氣相沉積製程，而形成 閘極2〇2時，例如可先於基底上沉積-金屬層202a 12535¾¾ 以使金屬層2G2a覆蓋住罩幕層2施與預定形成閘極之區 域鳥。之後，再於金屬層施上沉積一抗氧化層纖， 其中抗氧化層2G2b之材質例如可為金屬合金或金屬氮化 物等，其作用在於防止下方之金屬層2〇2a過度氧化。值 得注意的是，由於罩幕層220a與基底2〇〇之間具有一高 度差，因此形成於罩幕層220a上之金屬層2〇2a與抗氧化 層202b將會與形成在區域2〇〇a内的金屬層2〇2a與 化層202b分離開來。 、 然後，如圖2D所示，移除罩幕層22〇a。在移除罩 幕層220a的時候，罩幕層22〇a上之金屬層2〇2&與抗氧 化層202b亦同時被移除，而留下來的金屬層2〇2&與抗氧 化層202b即構成一閘極202。 、 幕，且更可藉 幕層。 且更可藉由例如薄膜貼覆或噴塗等其他方式形成此BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a gate, a thin film transistor, and a pixel structure. [Prior Art] A thin film transistor liquid crystal display mainly comprises a thin film transistor array, a color filter array substrate and a liquid crystal layer, wherein the thin film bauxite array substrate comprises a plurality of thin film transistors arranged in an array, And the pixel electrode (pixelelectr〇de) corresponding to the thin film transistor is thin - the operating principle of the transistor is similar to that of the conventional semiconductor M〇S element, and the film has three terminals (gate, drain) And the source element, and the function of the body is used as the liquid crystal display pixel unit. , the circuit is a, the process of the thin film transistor array substrate is usually eve ii! L (ph0t0lit ^ ^ (etchin ^ ^ ΐ and r transfer the pattern on the mask to the previous formation; use this === step to pattern the light The resist layer, then re-engrave, to the material touch === female f for the development of the size of the electrical 2, usually using a guide, but the gate is easy to reduce the wiring impedance, but the original metal layer The problem of the upper layer. Therefore, the prior art is based on an anti-oxidation layer, such as a metal alloy: 9twf.doc/006 (metal alloy) layer or a metal nitride layer, to avoid excessive metal layer of the lower layer. Oxidation affects the electrical performance of the panel. However, due to the difference in the wet etching rate between the metal layer and the oxidation resistant layer, when the application process is formed, the undercut of the metal layer tends to occur. Referring to FIGS. 1A to 1D, a schematic diagram of a fabrication process of a gate having an anti-oxidation layer is shown in sequence. First, as shown in FIG. 1A, a substrate 1 is provided, in which a substrate 1 is formed. a metal layer l〇2a and an anti-oxidation layer 1〇2b, and a patterned photoresist layer 11〇 is formed on the oxidation resistant layer 102b. Then, as shown in FIG. 1B, wet etching is performed by chemical side liquid to hide the metal layer from oxidation resistance. The portion of the layer that is not covered by the photoresist layer ιι is removed, wherein the metal layer 102a is behind the side due to the difference in the rate of the (4) etch rate between the metal layer and the anti-oxidation layer. The image of the cut 112 will occur due to excessive rot. Then, as shown in Fig. 1C, the photoresist layer 11 is removed, and the remaining portion of the metal layer i 〇 2a / and the oxidation resistant layer 102b constitutes a gate 1 〇 2. Next, as shown in FIG. 1D, a photoresist layer 104' is deposited on the anti-oxidation layer, wherein the sidewall of the gate 102 cannot have a good step shape, so that the insulating layer 104 cannot have good coverage. However, the film layer which is subsequently deposited may also be affected. In addition, after covering the insulating layer 1〇4, the problem of tip discharge may occur at the anti-bumping portion due to the excessive buttoning of the metal layer 102a. U2b: 9twf .doc/006 [Invention] In view of this, the object of the present invention is Provided is a method for fabricating a gate electrode, a thin film transistor, and a halogen structure, which is formed by lift_off to improve problems such as poor step coverage and tip discharge. The invention provides a method for fabricating a gate. First, a patterned mask layer is formed on a substrate, wherein the mask layer exposes a region where a gate is formed. Then, the exposed region of the mask layer A gate is formed in the middle. Then, the mask layer is removed. Further, based on the above-described method for fabricating the gate, the present invention provides a method for fabricating a thin film, which is formed on the substrate after the fabrication of the gate is completed. An insulating layer is formed to cover the gate. Then, a channel layer is formed on the insulating layer above the gate. Thereafter, a source and a 'no pole are formed on the channel layer. In addition, the method for fabricating the above-mentioned thin film transistor can be incorporated into a process of a two-electrode crystal array substrate, for example, and after the source and the immersion of the pixel structure, 1 iron can be formed on the substrate; The rhyme has an "opening" to expose the part of the pole. A ruthenium electrode is formed on the ruthenium layer, and the ruthenium electrode is electrically connected to > and the electrode through the opening. 1 槿 J J The gate of the present invention, the thin film transistor, and the surface of the gate formed by the halogen form a pole. And conventionally using etching; layer and anti-oxidation engraving 125353⁄4 twf.doc/006 4 the gate of the invention, the thin film transistor and the structure of the halogen structure are maintained in a good stepped shape, and the film is subsequently deposited. Layer /, has good coverage, and can avoid the problem of tip discharge of the gate. The above and other objects, features, and advantages of the present invention will be apparent from the description of the appended claims. [Embodiment] Referring to Figures 2A to 2D, a schematic diagram showing the manufacturing process of the gate electrode of the preferred embodiment of the present invention is shown. First, as shown in Fig. 2A, a substrate 2 is provided, and a layer 22 of masking material f is formed on the substrate 2. In the preferred embodiment, the material of the mask layer 220 is, for example, a photoresist material. Then, as shown in FIG. 2B, the mask material layer 22 is patterned so that an opening 222 is formed in the material layer 220 to form a patterned mask P^2〇a/ and the opening 222 exposes the substrate. One of the upper ones is intended to form a domain island. In the preferred embodiment, if the mask material layer 220 and the photoresist material are bucketed, the mask material layer 22 is patterned. The mask mask layer f layer 22 ( ) Perform exposure and development processes. In one embodiment, the opening formed in the mask material layer 22 () is such that the opening of the opening is retracted. For example, as shown in Fig. 2C, a gate-transfer is formed in the pre-domain pulse on the substrate. Forming the gate of the gate ^== process, evaporation process, etc. physical vapor deposition process, and forming the gate 2〇2, for example, the metal layer 202a 125353⁄43⁄4 can be deposited on the substrate to cover the metal layer 2G2a The mask layer 2 is applied to a bird that is intended to form a gate. Thereafter, an anti-oxidation layer is deposited on the metal layer, wherein the material of the anti-oxidation layer 2G2b is, for example, a metal alloy or a metal nitride, and the like is to prevent excessive oxidation of the underlying metal layer 2〇2a. It is to be noted that, since there is a height difference between the mask layer 220a and the substrate 2〇〇, the metal layer 2〇2a and the oxidation resistant layer 202b formed on the mask layer 220a will be formed in the region 2〇〇. The metal layer 2〇2a in a is separated from the layer 202b. Then, as shown in FIG. 2D, the mask layer 22A is removed. When the mask layer 220a is removed, the metal layer 2〇2& and the oxidation resistant layer 202b on the mask layer 22〇a are simultaneously removed, and the remaining metal layer 2〇2& and the oxidation resistant layer 202b are removed. That is, a gate 202 is formed. , curtain, and more can be used. And can be formed by other means such as film coating or spraying.
基於上述，本發明之閘極的製作方法係利用舉離法， 而以沉積的方式取代習知之濕式蝕刻來形成薄膜電晶體之 閘極，以使閘極之侧壁維持良好的階梯狀。其中，上述之 光阻層係作為一沉積罩幕，而形成此光阻層之方式例^包 括旋塗（spin coating)液態光阻（liquidpR)或使用電^ 光阻（Electro-Deposited PR)等。當然，在一合理的範圍 内，亦可選擇其他有機材質（甚或無機材質）作為沉積罩 素結構的製作方法。請參考圖3A〜3E，其 依序繪示本發明之一種薄膜電晶體的製作^ 12535¾ 9twf.doc/006 程示意® ’，3A〜3E舰精林發 構的製作流程示意圖。 裡—京、、、° 首先，如圖3A所示，基底200上例如已藉由上述之 閘極的製作方法而形成有閘極搬，接著於基底2〇〇上全 面性地沈積-絕緣層2〇4,以使絕緣層綱覆蓋住閑極 202。 材質3B所示’在絕緣層204上形成一半導體 =層(未、，、s吟並且藉由—光罩製程圖案化此 = 道層施。其中，通道層2〇6係位二 絕緣層綱上’且通道層206之材質例如可 為非曰日夕U'Si)。此外’通道層206之表面上更可另外 形成有一歐姆接觸声f去^ ^ 夕#曰& 觸θ (未、、、曰不），其材質例如可為經摻雜 I非日日尽。 屬# 圖3°所：’在基板200之上方形成另-金 # :以於曰甬不酋®並且藉由另一光罩製程來圖案化此金屬 二驟Φ :二二θ兰6上形成一源極/汲極208a/208b。在此 ^時將、雨、曾it藉由源極/沒極208a/208b作為遮罩，而 同時將通道層2〇6之部分厚度移除。 $ t亡所述’在完成上述之薄膜電晶體的製程之後， 可再繼續進行本發明之查去 在基板上形t圖㈣示’ 208a/208b，並且藉由—先置制曰 以蓋源極/沒極 光罩製程來圖案化保護層21〇，而 於保護層210中形成一開〇 口日日^ 9 極·。 開口 2U，且開口 212係暴露出沒 ：9twf.doc/006 /、之後，如圖3E所示，在保護層21〇上與開口 2i2中 幵y成銦錫乳化物電極層（未繪示），並且藉由一光罩製 程/而將銦錫氧化物層定義成一畫素電極 214。其中，畫 素電極214與汲極2〇8a之間係藉由開口 212而相互電性 連接。 綜上所述，本發明之閘極、薄膜電晶體以及畫素結 構的裝作方法係以舉離法形成閘極，因此可避免習知在金 屬層與抗氧化層之邊緣接合處的裏切現象，並可使閘極之 侧土維持良好的p0b梯狀。如此—來，在形成薄膜電晶體$ φ 晝素結構時，將可使後續沉積之膜層具有較佳之覆蓋性， 並可避免閘極之尖端放電的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限^本發明，任何熟習此技藝者，在不脫離本發明之精 神=範圍内，當可作些許之更動與潤飾，·本發明之保 濩範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A〜1D依序繪示為習知之一種具有抗氧化層之 閘極的製作流程示意圖。 · ^圖〜2D依序繪示為本發明之較佳實施例之—種 薄膜電晶體之閘極的製作流程示意圖。 圖3A〜3E依序繪示為本發明之較佳實施例之一種薄 膜電晶體陣列基板之晝素結構的製作流程示意圖。/ 【主要元件符號說明】 100 :基底 11 12535¾ 29twf.doc/006 102 :閘極 102a ··金屬層 102b ··抗氧化層 104 :絕緣層 110 :光阻層 112 ··裏切 200 :基底 200a :區域 202 :閘極 202a :金屬層 202b :抗氧化層 204 :絕緣層 206 :通道層 208a/208b :源極/汲極 210 :保護層 212 :開口 214 :畫素電極 220 :罩幕材質層 220a :罩幕層 222 ··開口 12Based on the above, the gate electrode of the present invention is formed by a lift-off method in place of a conventional wet etching to form a gate of a thin film transistor so that the sidewall of the gate maintains a good step shape. Wherein, the photoresist layer is used as a deposition mask, and the method for forming the photoresist layer includes spin coating liquid photoresist (liquidpR) or electro-deposited PR (Electro-Deposited PR). . Of course, other organic materials (or even inorganic materials) may be selected as a method of depositing the cap structure within a reasonable range. Please refer to FIG. 3A to FIG. 3E , which are a schematic diagram showing the fabrication process of a thin film transistor of the present invention in the form of a thin film transistor of the present invention. First, as shown in FIG. 3A, a gate electrode is formed on the substrate 200 by, for example, the above-described gate fabrication method, and then a comprehensive deposition on the substrate 2 is performed. 2〇4, so that the insulating layer covers the idle pole 202. As shown in the material 3B, a semiconductor = layer is formed on the insulating layer 204 (not, s, s 吟 and patterned by the mask process). The channel layer 2 〇 6 is a two-layer insulating layer. The upper layer and the material of the channel layer 206 can be, for example, U'Si. In addition, an ohmic contact sound f can be additionally formed on the surface of the channel layer 206, and the material can be doped, for example, by doping.属# Figure 3°: 'Forming another - gold # above the substrate 200: to 曰甬 酋 酋 并且 and to pattern the metal by another reticle process Φ: formation on the second θ 兰 6 A source/drain 208a/208b. At this time, it is rain, and it has been used as a mask by the source/dipole 208a/208b, while at the same time removing part of the thickness of the channel layer 2〇6. After the completion of the above-mentioned process of the thin film transistor, the present invention can be further carried out to check the shape of the substrate (4) shown as '208a/208b, and by using the first method to cover the source The pole/no-pole mask process is used to pattern the protective layer 21〇, and an opening is formed in the protective layer 210. Opening 2U, and opening 212 is exposed: 9twf.doc / 006 /, then, as shown in FIG. 3E, on the protective layer 21 与 and the opening 2i2 幵 y into an indium tin emulsion electrode layer (not shown), And the indium tin oxide layer is defined as a pixel electrode 214 by a photomask process. The pixel electrode 214 and the drain electrode 2〇8a are electrically connected to each other through the opening 212. In summary, the gate electrode, the thin film transistor and the pixel structure of the present invention are formed by the lift-off method, so that the conventional tangent phenomenon at the edge of the metal layer and the oxidation resistant layer can be avoided. And can maintain a good p0b ladder shape on the side of the gate. In this way, when the thin film transistor $ φ 昼 结构 structure is formed, the subsequently deposited film layer can be better covered, and the problem of tip discharge of the gate can be avoided. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit of the invention. The scope of the invention is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are sequentially schematic views showing a manufacturing process of a gate having an anti-oxidation layer. FIG. 2D is a schematic view showing the manufacturing process of the gate of the thin film transistor according to the preferred embodiment of the present invention. 3A to 3E are schematic views showing the manufacturing process of a pixel structure of a thin film transistor array substrate according to a preferred embodiment of the present invention. / [Main component symbol description] 100 : Substrate 11 125353⁄4 29twf.doc / 006 102 : Gate 102a · · Metal layer 102b · Anti-oxidation layer 104 : Insulation layer 110 : Photoresist layer 112 · · Lie 200 : Substrate 200a : Area 202: gate 202a: metal layer 202b: oxidation resistant layer 204: insulating layer 206: channel layer 208a/208b: source/drain 210: protective layer 212: opening 214: pixel electrode 220: mask material layer 220a : Cover layer 222 ·· Opening 12